{"id":"6028955c-bca4-467d-827a-937b1a64d131","arxiv_id":"2502.05090","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Croc is an end-to-end open-source RISC-V MCU platform, validated by a two-student tapeout in IHP's open 130nm node, that lets students implement and fabricate their own ASICs.","lead":"Croc is an open-source RISC-V microcontroller platform built for students to learn chip design from end to end, with a demonstration chip called MLEM taped out by two bachelor students in eight weeks. It bundles a small processor, peripherals, open-source EDA tools, and coursework so that a class can design, implement, and even send chips to fabrication.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Silicon-proven claim rests on unimplemented post-silicon tests; missing functional correctness evidence for taped-out MLEM leaves the strongest claim conditionally supported.","rationale":"Good-faith reading: Croc is an extensible RISC-V MCU platform with a documented open EDA flow, and the eight-week MLEM tapeout by two students demonstrates that the platform enables physical implementation in an open PDK. The future VLSI2 course plans and the release of lecture notes under CC are supporting evidence for the educational mission. The reader's verdict is CONDITIONAL, and the condition is precisely that the 'silicon-proven' language be tempered or backed by post-silicon measurements. My analysis identifies the same load-bearing assumption: the strongest claim ('production-ready', 'silicon-proven') requires functional correctness of the fabricated MLEM chip, which is not demonstrated anywhere in the paper. The paper does provide independent support: MLEM's physical implementation metrics (5mm2, 350kGE, 56% density, 80MHz clock, one-hour flow) are concrete, reproducible-sounding numbers, and the use of the industry-maintained CVE2 core and a documented OS flow (IIC-OSIC-TOOLS container, Yosys, OpenRoad) adds credibility. However, none of this verifies silicon functionality. The concern is not that the paper is internally inconsistent; it is a precision-of-claim issue: the evidence supports 'tapeout feasibility' but not 'silicon-proven'. This is exactly the kind of concern that a conditional verdict should address, and it is already captured by the reader's weakest_assumption. I therefore keep the verdict UNCHANGED rather than escalate, because the risk is moderate rather than fatal: the pedagogical claim of enabling students to complete an ASIC flow end-to-end is substantially supported even if MLEM silicon has not been measured. The concrete test is straightforward and proportionate: obtain post-silicon test results or re-scope the claim. No theatrical language or ad hominem is needed; the issue is a factual-evidence gap in the paper's own contribution statement.","tokens_in":3479,"tokens_out":2975,"duration_ms":23767,"concrete_test":"Contact the authors or check the MLEM chip gallery (asic.ethz.ch/2024/MLEM.html) for post-silicon bring-up results, specifically whether the fabricated MLEM chip has been tested on a board and passed functional tests (e.g., UART loopback, GPIO toggle, NeoPixel output, and a CVE2 software benchmark such as Dhrystone or a memory BIST). If no post-silicon measurements exist, ask the authors to replace 'silicon-proving' with wording scoped to 'physical implementation feasibility demonstrated by a taped-out chip' and to state the pre-silicon verification status (simulation and FPGA validation) of the exact MLEM design. A positive measurement, or an explicit scoping of the claim together with a description of pre-silicon verification coverage, would settle whether the central claim is overstated.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's headline contribution is that Croc is a production-ready, silicon-proven platform whose viability is demonstrated by MLEM, an eight-week student tapeout. The strongest claim thus requires that the taped-out MLEM silicon actually functions as designed. The paper provides physical implementation data: 5 mm2, 350kGE, 56% density, 80 MHz top clock speed at 58 logic levels under typical conditions, and an under-one-hour, sub-8-GiB implementation run. However, it reports no post-silicon bring-up results, no functional test measurements, no UART/GPIO/NeoPixel loopback tests, and no software execution on the fabricated chip. Section 'MLEM Student Tapeout' says the students 'independently designed, implemented, and verified their designs' through the physical design flow, but 'verified' here refers to pre-silicon verification, which the paper does not describe in detail. The term 'silicon-proving the SoC platform' in the contributions list is therefore only supported by the tapeout's physical completion, not by evidence that the chip works. This distinction matters because physical implementation success is necessary but not sufficient: a fabricated chip can pass DRC/LVS and still fail functionally due to a design bug, a missing constraint, or a timing corner issue. The paper also relies on 'silicon-proven production-ready SV IPs' (CVE2) and future VLSI2 enrollment (80 students, up to 40 layouts, up to five tapeouts) as credibility anchors, but the central, load-bearing evidence for 'silicon-proven' is the MLEM silicon, whose functional status is unverified. For the paper's educational-viability claim, this gap is real but not fatal: the platform's pedagogical utility is largely established by the successful physical completion of MLEM; however, if MLEM comes back non-functional or is never measured, the 'silicon-proven' label and the implied industrial-readiness of the flow would be overstated.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents Croc, an open-source RISC-V microcontroller platform designed for hands-on VLSI education. The platform includes a minimal MCU built around the CVE2 core, a set of peripherals, a user domain for student extensions, and a streamlined open-source RTL-to-GDS implementation flow using Yosys, OpenROAD, and the IHP 130 nm open PDK. The authors report an eight-week tapeout of a demonstrator chip, MLEM, by two bachelor students, and they plan to use Croc in an ETH Zurich VLSI course for up to 80 students. The paper claims that Croc is 'silicon-proven' and that the tapeout demonstrates the platform's viability for education.","tokens_in":3701,"tokens_out":5344,"duration_ms":53797,"significance":"If the central claims are substantiated, this work is a valuable contribution to open-source hardware education. The platform is fully open, built on industry-maintained IPs (CVE2), and is accompanied by lecture notes and exercises under a Creative Commons license. The reported tapeout of MLEM in an open PDK by two students in eight weeks is strong evidence that the RTL-to-GDS flow is accessible and reproducible. Practical details such as the sub-hour implementation run with a memory footprint below 8 GiB are concrete and useful for academic settings. However, the paper's most prominent claim—that Croc is 'silicon-proven'—is not supported by functional post-silicon measurements, which weakens the significance until such evidence is supplied or the claim is appropriately qualified.","major_comments":[{"comment":"The paper claims that the MLEM tapeout 'silicon-proves' the SoC platform, but it reports only physical implementation metrics (die area, gate count, density, and clock frequency) and no post-silicon functional test results. There are no measurements from the fabricated chip, no UART/GPIO/NeoPixel loopback tests, and no evidence that software executes correctly on the silicon. Physical fabrication success is necessary but not sufficient for functional correctness; a chip can pass DRC/LVS and still fail due to a design logic error, a missing constraint, or a timing corner issue. The contribution should be downgraded to 'successful tapeout and physical implementation' or the authors must provide post-silicon bring-up results to justify the 'silicon-proven' wording.","section":"MLEM Student Tapeout and Contributions list"},{"comment":"The paper states that Croc is built on 'production-ready, industry-proven IPs' and 'silicon-proven SystemVerilog code,' but it provides no evidence or citations that the CVE2 core or the other integrated IPs have been functionally silicon-proven in this or a comparable configuration. The phrase 'industry-proven' appears in the introduction and the platform description, and it is part of the paper's implied credibility argument. The authors should either supply references to prior functional tapeouts of these IPs or rephrase to 'open-source IPs with active industry maintenance' to avoid an unsupported claim.","section":"Croc Platform"}],"minor_comments":[{"comment":"There is a missing space in 'extensibleRISC-V' in the abstract; it should read 'extensible RISC-V.'","section":"Abstract"},{"comment":"Figure 1 contains the informal text 'I am Doug Dimmadome, owner of the Dimmsdale Dimmadome!' which appears to be a meme and is not appropriate for a formal publication. It should be removed or replaced with a neutral watermark or annotation.","section":"Figure 1"},{"comment":"The claim that the implementation completes in 'less than one hour' on a '6th Generation Intel Core i7' is underspecified. The authors should give the exact CPU model, number of cores, RAM capacity, and storage type to allow reproducibility and fair comparison.","section":"MLEM Student Tapeout"},{"comment":"The assertion that CVE2 'achieve[s] its ideal performance of one instruction per cycle' is not backed by cycle-accurate simulation data or benchmark results. A short note about the instruction throughput measured in simulation would strengthen the claim.","section":"Croc Platform"},{"comment":"The term 'verified' in the sentence 'they independently designed, implemented, and verified their designs' is ambiguous. It could refer to simulation-based functional verification, logic equivalence checking, or physical verification; the paper should clarify what verification steps were performed.","section":"MLEM Student Tapeout"}],"recommendation":"major_revision","confidential_remarks":"The paper is a short, workshop-style contribution. As a journal submission, it would benefit from a more complete description of the RTL-to-GDS flow, the verification methodology, and the educational context. The load-bearing issue is the unsupported 'silicon-proven' claim; adding even minimal post-silicon functional measurements would resolve it. The presence of the 'Doug Dimmadome' meme in Figure 1 is unprofessional and should be addressed before any publication. The planned future tapeouts in the VLSI2 course are not evidence for the current claims and should be presented only as outlook."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Worth a look, and worth a serious referee. What's actually new: the Croc platform as a packaged, single-repo RISC-V MCU for teaching, the yosys-slang SV frontend, and the MLEM tapeout — two bachelor students going from RTL to layout in eight weeks in IHP 130nm. That is real evidence that the educational flow works for physical implementation. The paper is honest about building on prior work (Basilisk, PULP IPs, IHP open PDK) and ships the repository, lecture notes, and exercises under a CC license.\n\nThe soft spot is the 'silicon-proven' language. The paper says MLEM 'silicon-proves the SoC platform', but it reports no post-silicon test measurements: no UART loopback, no GPIO toggle, no code execution on silicon. Physical completion is necessary but not sufficient for silicon-proven; the chip could pass DRC/LVS and still be non-functional. The stress-test note is right: this is a genuine gap, not a manufactured one. It doesn't sink the pedagogical claim, which only really depends on the flow being completable by students, but it does mean the headline claim is overstrong as written. The authors should either add bring-up data or re-scope the claim to 'silicon-implementation feasibility.'\n\nMinor: the paper leans on future VLSI2 enrollment (80 students, up to 5 tapeouts) as a credibility anchor. That's forward-looking, not evidence. Also, no commit-level artifacts or detailed reproduction instructions; the public repo helps, but the paper alone isn't a self-contained reproduction recipe.\n\nWho's this for? Faculty running hands-on VLSI courses, and the open-source EDA community. It deserves a serious referee; a workshop paper with a real tapeout and an addressable gap is exactly what peer review is for.","headline":"A solid educational chip-design platform with a real student tapeout, but 'silicon-proven' is one overstatement until the MLEM chip is actually tested.","tokens_in":4455,"tokens_out":2230,"would_cite":true,"duration_ms":22719,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Croc is an open-source RISC-V MCU platform that takes student designs from RTL to tapeout.","keywords":["RISC-V","microcontroller","open-source hardware","ASIC tapeout","chip design education","open PDK","electronic design automation","SystemVerilog"],"falsifier":"Take the fabricated demonstrator chip from the reported tapeout, load the same firmware used in RTL simulation, and exercise the UART, GPIO, timer, and LED-controller peripherals at the reported 80 MHz operating point; if the silicon does not boot or peripheral traffic is corrupted, the claim that Croc is silicon-proven for classroom tapeouts fails.","tokens_in":3224,"feed_emoji":"🔌","tokens_out":7898,"duration_ms":76844,"temperature":0.7,"pith_summary":"The paper tries to establish that a compact, extensible, open-source RISC-V microcontroller platform can carry a student from a digital circuit description to fabricated silicon using only open-source tools and an open fabrication-technology kit. Its evidence is a demonstrator chip that two undergraduate students taped out in an open 130 nm node in eight weeks. If the claim holds, a university class can teach real ASIC design and tapeout at scale, not just FPGA emulation, which is what the paper says an upcoming 80-student course will do. The authors frame this as a step toward silicon democratization: removing proprietary-tool and licensing barriers so more people can enter chip design.","feed_headline":"Two students tape out a RISC-V chip in eight weeks","feed_subtitle":"An open-source MCU platform and a fully open EDA flow put real tapeouts within reach of a classroom.","key_machinery":"The load-bearing mechanism is the Croc platform as a complete minimal starting point: one repository holding the RTL, software setup, and documentation, plus a streamlined open-source implementation flow in which a new lightweight SystemVerilog frontend for the synthesis tool replaces a complicated preprocessing step. The CVE2 core is the workhorse; its single-cycle tightly coupled memory banks let it retire one instruction per cycle, and its RV32I(EMC) base leaves room for students to add custom instructions. A containerized toolchain bundles the open EDA tools and the open PDK, so every student works in the same reproducible environment, and an FPGA flow provides low-cost verification before tapeout.","core_discovery":"Croc is a minimal RISC-V microcontroller system-on-chip built entirely from open, production-ready SystemVerilog blocks: a single-issue in-order CVE2 core implementing RV32I(EMC), a tightly coupled interconnect, two SRAM banks, a small set of peripherals, and a user domain where students can attach their own accelerators or instruction-set extensions. The paper's central claim is that this design, together with a documented, containerized open-source synthesis and place-and-route flow and an open 130 nm PDK, is enough for a small student team to complete a physical chip implementation. The demonstrator MLEM confirms the claim at the layout level: a 5 mm², 350-thousand-gate-equivalent chip at 56% density, closing timing at 80 MHz under typical conditions, implemented in under an hour on a single machine with less than 8 GiB of memory.","pith_inferences":["If the reported eight-week timeline holds generally, the bottleneck in student chip design shifts from tool access and licensing to verification and design bring-up, so course time may be better spent on those skills.","The paper's evidence stops at tapeout, so a direct next step is post-silicon bring-up of the fabricated demonstrator; functional measurements would turn 'tapeout demonstrated' into 'silicon verified'.","The same flow should transfer to other open PDK nodes and to larger student chips; whether the one-hour, 8 GiB implementation budget scales to multi-core designs is an open question.","An open analog PDK layer, if added, would let the same educational model cover sensors or radio front ends, widening the hands-on scope beyond digital logic."],"forward_implications":["A two-person student team can turn RTL into a physical 130 nm chip layout in eight weeks using only open-source tools and an open PDK.","A university course can assign real tapeouts at scale: the paper reports an upcoming class of 80 students producing up to 40 ASIC layouts and up to five student-led SoC tapeouts.","Students can experiment with custom ISA extensions and accelerators without leaving the mainline flow, because the baseline design is small enough to close timing quickly.","The same platform doubles as a starting kit for commercial RISC-V MCU products in security, control, or edge machine learning, since it is built on production-ready IP cores.","Because the PDK and tools are open and the teaching material is openly licensed, the course can be replicated outside the host institution."],"supporting_citations":[{"why":"supplies the production-ready open-source CVE2 RISC-V core that is the heart of the Croc MCU.","marker":"[11]"},{"why":"supplies the open 130 nm PDK that makes an end-to-end open tapeout possible.","marker":"[8]"},{"why":"is the prior open-source SoC implementation flow that Croc's synthesis and place-and-route flow streamlines.","marker":"[9]"},{"why":"bundles the open EDA toolchain and PDK into a container, giving students a reproducible environment.","marker":"[13]"},{"why":"establishes the silicon-proven lineage of the CVE2 core, supporting the paper's claim that Croc uses industry-proven IP.","marker":"[10]"},{"why":"defines the OBI on-chip interconnect protocol that the Croc crossbar and peripherals implement.","marker":"[12]"},{"why":"is the existing educational chip-design platform that Croc compares against and aims to surpass.","marker":"[5]"}],"fun_headline_variants":["Two students tape out a RISC-V chip in eight weeks","Open-source RISC-V chip built by two students in two months","Student duo creates RISC-V chip in eight weeks with open tools","RISC-V tapeout in eight weeks: a two-student open-source feat","From classroom to silicon: RISC-V chip in eight weeks by two students"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central claim assumes the fabricated MLEM chip actually works as designed: the paper reports a successful physical implementation and tapeout but provides no post-silicon test measurements.","fun_headline_variants_meta":{"raw":{"variants":["Two students tape out a RISC-V chip in eight weeks","Open-source RISC-V chip built by two students in two months","Student duo creates RISC-V chip in eight weeks with open tools","RISC-V tapeout in eight weeks: a two-student open-source feat","From classroom to silicon: RISC-V chip in eight weeks by two students"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000256,"raw_usage":{"total_tokens":1595,"prompt_tokens":987,"completion_tokens":608,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":603,"completion_tokens_details":{"reasoning_tokens":513}},"tokens_in":603,"tokens_out":608,"duration_ms":6527,"temperature":1.0,"reasoning_tokens":513,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-08T20:16:18.186022+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take the fabricated demonstrator chip from the reported tapeout, load the same firmware used in RTL simulation, and exercise the UART, GPIO, timer, and LED-controller peripherals at the reported 80 MHz operating point; if the silicon does not boot or peripheral traffic is corrupted, the claim that Croc is silicon-proven for classroom tapeouts fails.","supporting_citations":[{"cited_title":"OpenHW Group CORE-V CVE2 RISC-V IP","cited_arxiv_id":null,"evidence_quote":"supplies the production-ready open-source CVE2 RISC-V core that is the heart of the Croc MCU."},{"cited_title":"Reflections on the First European Open Source PDK by IHP-Experiences After One Year and Future Activities","cited_arxiv_id":null,"evidence_quote":"supplies the open 130 nm PDK that makes an end-to-end open tapeout possible."},{"cited_title":"Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?","cited_arxiv_id":null,"evidence_quote":"is the prior open-source SoC implementation flow that Croc's synthesis and place-and-route flow streamlines."},{"cited_title":"IIC-OSIC-TOOLS","cited_arxiv_id":null,"evidence_quote":"bundles the open EDA toolchain and PDK into a container, giving students a reproducible environment."},{"cited_title":"Ibex RISC-V Core","cited_arxiv_id":null,"evidence_quote":"establishes the silicon-proven lineage of the CVE2 core, supporting the paper's claim that Croc uses industry-proven IP."},{"cited_title":"github.com/openhwgroup/programs/blob/master/TGs/ cores-task-group/obi/OBI-v1.5.0.pdf","cited_arxiv_id":null,"evidence_quote":"defines the OBI on-chip interconnect protocol that the Croc crossbar and peripherals implement."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"is the existing educational chip-design platform that Croc compares against and aims to surpass."}],"review_version":1}