{"id":"25601c9c-6220-4d56-8436-bfca914a7366","arxiv_id":"2502.06304","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"DyPE is a data-aware dynamic scheduler for heterogeneous GPU-FPGA systems that outperforms static scheduling on GNN and sliding-window transformer inference benchmarks.","lead":"A new scheduler called DyPE decides which parts of an inference model run on GPUs and which on FPGAs, changing its choices as input data becomes more or less sparse. On a prototype GPU-FPGA cluster, it reports about 1.5x throughput gains over a static schedule, but the paper's headline numbers are internally inconsistent.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Algorithm 1's DP discards prefixes that are not best in isolation, so even perfect kernel models do not guarantee the reported 'optimal' schedules.","rationale":"The strongest claim is not merely that DyPE improves over static schedules, but that it finds the optimal schedule in 77/86 cases. The reader's concern is that linear regression models trained on synthetic inputs may not generalize to real kernels; that is a real risk. But a more load-bearing concern sits one level deeper: even with perfect kernel and communication models, Algorithm 1's state representation is insufficient for the dynamic program to be optimal. The transition cost when appending a stage depends on the device type and count of the last stage of the prefix, but each DP cell keeps only one prefix schedule, chosen by the current makespan. A prefix that is second-best in isolation can be first-best once the next stage's transfer cost is included, so the optimal-substructure property required for this DP does not hold. Section VI-B's methodology does not resolve this: comparing the scheduler with estimated models against the scheduler with measured runtimes checks whether model errors alter the DP's decision, not whether the DP itself is optimal. If the oracle is instead an exhaustive search, the paper does not say so. The concern is concrete and testable: the evaluated workloads have small kernel counts (GCN: 4 kernels; GIN: a handful; transformer layers are identical, so the effective stage count is small), making exhaustive enumeration feasible. The verdict should remain CONDITIONAL, but the condition must now include either a proof of optimality or an exhaustive comparison showing Algorithm 1 matches the true optimum on the evaluated cases.","tokens_in":18058,"tokens_out":9928,"duration_ms":90626,"concrete_test":"Enumerate all valid pipeline partitions, per-stage device types/counts, and communication costs for a small GNN workload (e.g., GCN-S1 with exact measured kernel and transfer times), and compare the exhaustive optimum with Algorithm 1's output; repeat for all 42 GNN cases. If any case differs, the DP is suboptimal. Alternatively, construct a 3-kernel, 1-FPGA-1-GPU instance where a dominated prefix ending on GPU enables a zero-copy GPU continuation and show Algorithm 1 returns a schedule worse than exhaustive.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The paper's central quantitative claim is that DyPE finds the optimal schedule in 77/86 cases. Section VI-B validates this by 'running the scheduler with the actual measured performance of the kernels' and comparing against the estimation-model output; if that oracle is the same Algorithm 1, it does not establish optimality, because Algorithm 1 is not guaranteed to find a globally optimal schedule even with exact fperf and fcomm. The DP cell dpperf[i][f][g] stores a single best pipeline for each prefix and resource count, selected by makespan (lines 25-27). However, the cost of appending the next stage depends on the previous stage's device type and count: lines 13-21 compute the added transfer time using src_dev and nsrc_dev of the last stage, and add it to the previous stage's duration. Consequently, a prefix schedule that is not best for (i,f,g) in isolation may be the only one that enables a low-cost continuation on the same device, yielding a better full pipeline. The DP discards that prefix, so the returned schedule can be suboptimal independently of any performance-model error. The dpeng energy table has the same missing-state problem. The 77/86 optimality claim therefore conflates model error with algorithmic suboptimality.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces DyPE, a scheduling framework for heterogeneous systems with GPUs and FPGAs. DyPE takes a workload description, system specifications, kernel performance models, and design objectives as inputs, and uses a dynamic-programming scheduler to explore pipeline configurations under different objectives (performance-optimized, balanced, energy-optimized). Kernel execution times are estimated with linear regression models trained on synthetic profiles, with special formulas for sparse SpMM and sliding-window attention. The authors built a real testbed with two MI210 GPUs, three U280 FPGAs, and peer-to-peer FPGA-GPU transfers. They evaluate DyPE on GNN (GCN/GIN) and sliding-window transformer workloads across PCIe 4.0, PCIe 5.0, and CXL 3.0 interconnect assumptions. The headline claims are that DyPE finds the optimal schedule in 77/86 cases (77/84 in the body), that static scheduling is optimal in only 13/86 cases, that the average loss in sub-optimal cases is 3.95%, and that DyPE improves throughput by 1.53x and energy efficiency by 1.09x over a static baseline. The paper also reports that model inaccuracies rarely change the scheduling decision, with sub-optimality rates of 3/42 and 4/42 for throughput- and energy-optimized GNN cases.","tokens_in":18321,"tokens_out":5633,"duration_ms":52876,"significance":"The paper attacks a real problem: input-dependent sparsity and data characteristics can change which device mapping is best, and static or semi-static schedules cannot adapt. The hardware contribution is substantial: the authors built a working FPGA-GPU cluster with peer-to-peer transfers and validated schedules against actual measured kernel times. If the claims held, DyPE would be a valuable instance of data-aware scheduling for irregular workloads. The paper also shows a useful methodology point: evaluating a scheduler by comparing model-based decisions against decisions made with measured kernel timings is a step beyond validating the regression alone. However, the central optimality claim is not yet established: the DP formulation in Algorithm 1 does not have a guaranteed optimal-substructure property, and the experimental sections contain numeric inconsistencies between the abstract and the body. The significance of the contribution depends on fixing these load-bearing issues; the review therefore recommends major revision rather than acceptance.","major_comments":[{"comment":"","section":"Section II-A, Algorithm 1 and Section VI-B"},{"comment":"","section":"Abstract, Section I, Section VI-B and Table III"},{"comment":"","section":"Section V and Section VI-B"}],"minor_comments":[{"comment":"","section":"Section V, Equation (8)"},{"comment":"","section":"Section VI-C, Table IV"},{"comment":"","section":"Section VI-C, Figure 7"},{"comment":"","section":"Section VI-B"},{"comment":"","section":"Section II-A"}],"recommendation":"major_revision","confidential_remarks":"The DP optimality concern is the main correctness risk. The claim that DyPE finds the optimal schedule in 77/84 cases is central to the paper's contribution, and Algorithm 1 as written can discard prefixes that are needed for a globally optimal continuation. This is fixable in principle by augmenting the DP state, providing a proof of optimal substructure, or validating against exhaustive search on small instances, but it must be addressed before the claim can be accepted. The abstract/body number mismatches (77/86 vs 77/84, 13/86 vs 8/108) also suggest the manuscript was revised without fully reconciling the text; the authors should be asked to correct this carefully."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two things to know. The paper is a genuine engineering contribution: a data-aware scheduler that reallocates GNN and transformer kernels between GPUs and FPGAs based on input sparsity, validated on a real cluster with P2P FPGA-GPU transfers. But the headline claim—finding the optimal schedule in 77/86 cases—is not backed by the algorithm as written, and the numbers in the abstract don't match the body.\n\nWhat's new: dynamic device-type selection based on sparsity, not just device count as in FleetRec; and the FPGA-GPU P2P testbed is real, with measured speedup over CPU-mediated transfers. The evaluation compares against actual measured kernel times, which is the right way to test a scheduler. The Pareto exploration across performance, energy, and balanced modes is thoughtful and gives useful engineering insight.\n\nSoft spots. First, Algorithm 1's DP stores only the single best prefix for each (i,f,g), chosen by makespan. But the cost of appending the next stage depends on the last stage's device type and count, so a slightly worse prefix with a different last stage can enable a better continuation. The DP discards it. So even with perfect kernel models, the returned schedule is not guaranteed optimal. Unless they verified by exhaustive search—and they don't say so—the 77/86 claim conflates model error with algorithmic suboptimality. That's load-bearing, but fixable: prove the DP is optimal for their small pipelines or rephrase the claim as \"best found by our scheduler.\"\n\nSecond, the numbers don't line up. Abstract says 77/86 with 3.95% average loss; the intro says 77/84; Table III gives 3/42 and 4/42 sub-optimal, which with equal weights averages to 4.2%, not 3.95%. No error bars, no code or data release, and no regression accuracy metrics, so we can't assess how well the models transfer to unseen workloads.\n\nNone of this kills the core idea. The scheduler is plausible and the testbed work is real. But the paper overstates optimality and the presentation is sloppy in ways that matter.\n\nWho it's for: systems people working on heterogeneous scheduling and FPGA-GPU acceleration. It is a solid empirical paper once the claims are reined in.\n\nRecommendation: send to peer review. The reviewers should demand an exhaustive-search validation or a corrected heuristic claim, plus code/data and consistent numbers. The idea deserves a serious look, but not in its current form.","headline":"A real FPGA-GPU scheduling testbed with a plausible dynamic scheduler, but the optimality claim is not supported by the DP algorithm as written and the headline numbers don't match the body.","tokens_in":18840,"tokens_out":3378,"would_cite":false,"duration_ms":29400,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A data-aware scheduler finds the optimal FPGA-GPU allocation in 77 of 86 workloads.","keywords":["dynamic scheduling","heterogeneous systems","FPGA","GPU","GNN inference","sliding-window transformers","sparsity-aware scheduling","pipeline parallelism"],"falsifier":"Take a set of GNN or transformer inputs whose sparsity and arithmetic intensity fall outside the synthetic training range, run DyPE's chosen schedule on the hardware alongside an exhaustive enumeration of all pipeline-stage and device-count allocations, and compare ranking; if the enumerated optimum beats DyPE's choice by more than the reported few percent in a substantial share of cases, the transferability assumption fails.","tokens_in":1774,"feed_emoji":"⚡","tokens_out":2192,"duration_ms":83135,"temperature":0.7,"pith_summary":"This paper tries to establish that a scheduler which watches the input data can replace manual partitioning on heterogeneous GPU-FPGA systems. Its claim is that static, hand-tuned schedules are optimal only rarely, while the DyPE scheduler—using lightweight kernel performance models and a dynamic-programming search over pipeline stages—finds the optimal device allocation in 77 of 86 evaluated cases and loses only 3.95% on average when it misses. The payoff would matter because irregular workloads like GNN inference and sliding-window transformers change their sparsity and arithmetic intensity at runtime, so no fixed device assignment stays optimal. The paper backs the claim with measurements on a real testbed with direct GPU-to-FPGA data transfers, reporting 1.53x average throughput and 1.09x energy efficiency gains over a static baseline.","feed_headline":"Data-aware scheduler beats static FPGA-GPU splits in 77 of 86 cases","feed_subtitle":"It reallocates kernels as sparsity shifts, lifting throughput 1.53x and energy efficiency 1.09x over static schedules.","key_machinery":"The load-bearing object is the dynamic-programming table $dp[i][f][g]$ (with separate throughput and energy copies), which records the best pipeline for the first $i$ kernels using $f$ FPGAs and $g$ GPUs. The search groups several consecutive kernels into one pipeline stage, looks back at previous table entries for the remaining devices, and evaluates candidate stages through three functions: kernel performance estimation $f_{\\mathrm{perf}}$, communication cost estimation $f_{\\mathrm{comm}}$, and energy estimation $f_{\\mathrm{eng}}$. The performance estimators are built by benchmarking kernels on synthetic input profiles and fitting linear regressions, with FPGA kernels using architecture-derived formulas that add a scaling factor fitted to the measured data. This machinery is what lets the scheduler compare many device allocations cheaply at runtime and re-run when input characteristics change.","core_discovery":"DyPE's central claim is that dynamic, input-aware scheduling is both necessary and sufficient for heterogeneous systems built from GPUs and FPGAs. It argues that the best device for a given kernel depends on data-dependent features such as sparsity and arithmetic intensity, which shift at runtime, so a schedule fixed at design time cannot track the optimum. The scheduler therefore takes a workload description, system specifications, kernel performance models, and user objectives, then builds a dynamic-programming table that groups consecutive kernels into pipeline stages and assigns each stage a number of FPGAs or GPUs, separately optimizing throughput and energy and reading out Pareto-optimal configurations—points where no alternative is better in both throughput and energy—through a balanced mode. On the authors' FPGA-GPU testbed, DyPE reports finding the optimal schedule in 77 of 86 cases, with an average 3.95% throughput or energy-efficiency loss in sub-optimal cases, and average gains of 1.53x throughput and 1.09x energy efficiency over a manually tuned static schedule and 1.44x and 1.66x over GPU-only execution.","pith_inferences":["The same dynamic-programming search should extend to more than two device types and to arbitrary DAG-shaped workloads, since the stage-grouping mechanism only assumes consecutive kernels can be fused and each device type has a performance estimator; the paper does not demonstrate this.","The small average sub-optimality loss suggests the schedule-quality landscape is fairly flat near the optimum, so cheap approximate performance models may be enough for online rescheduling; the paper does not test this flatness directly.","A testable extension not explored in the paper is online re-fitting of the linear regression models from measured kernel times as new data distributions arrive, which could maintain the 77/86 optimal-schedule rate on workloads that drift from the synthetic training profiles."],"forward_implications":["A manually tuned static schedule is optimal in only 13 of the 86 evaluated cases, so any production heterogeneous system facing variable data should treat static allocation as a rarely optimal default.","DyPE recovers most of the gap by dynamic rescheduling: it finds the optimal schedule in 77 of 86 cases and keeps the average loss to 3.95% when it misses.","Over baselines, DyPE reports average 1.53x throughput and 1.09x energy efficiency gains over static schedules, and 1.44x throughput and 1.66x energy efficiency over GPU-only execution.","Faster interconnects such as PCIe 5.0 and CXL 3.0 change the optimal device allocation, so communication-cost modeling is essential, not optional, for the scheduler's decisions.","The balanced mode lets an operator cap throughput loss at 30% while minimizing energy, giving a concrete energy-performance trade-off when QoS targets exist."],"supporting_citations":[{"why":"Defines GIN, the graph isomorphism network used as a GNN case-study workload alongside GCN.","marker":"[2]"},{"why":"Supplies the FPGA sliding-window attention design and its performance parameters, which DyPE adopts for transformer kernels.","marker":"[6]"},{"why":"FleetRec is the hybrid GPU-FPGA scheduling baseline whose fixed device-type assumption DyPE relaxes.","marker":"[17]"},{"why":"Describes direct GPU-FPGA communication over PCIe, the mechanism the testbed uses for peer-to-peer transfers.","marker":"[24]"},{"why":"Defines the GCN layer as SpMM followed by GEMM, the kernel structure DyPE schedules.","marker":"[25]"},{"why":"Provides the ogbn-arxiv and ogbn-products benchmark datasets used in GNN evaluation.","marker":"[26]"},{"why":"Defines BigBird's sliding-window attention, the transformer setting used for the second workload family.","marker":"[28]"},{"why":"Provides the Sextans FPGA SpMM streaming architecture whose hardware design and performance model DyPE adapts.","marker":"[30]"},{"why":"Supplies the FPGA GEMM implementation used to obtain dense-kernel performance.","marker":"[31]"}],"fun_headline_variants":["DyPe finds optimal FPGA-GPU split in 77 of 86 workloads","Dynamic scheduler beats static splits on FPGA-GPU: 77/86","Data-aware DyPe nails optimal GPU/FPGA plan in 77/86 cases","Scheduler adapts to data, hits optimal in 77 of 86 GPU-FPGA runs","DyPe: dynamic scheduling finds optimal GPU-FPGA config 77/86 times"],"cache_read_input_tokens":20992,"weakest_assumption_plain":"The results depend on the kernel performance models: linear regressions fit to synthetic profiles must predict real GNN and transformer runtimes well enough that the scheduler's ranking of device allocations is not inverted.","fun_headline_variants_meta":{"raw":{"variants":["DyPe finds optimal FPGA-GPU split in 77 of 86 workloads","Dynamic scheduler beats static splits on FPGA-GPU: 77/86","Data-aware DyPe nails optimal GPU/FPGA plan in 77/86 cases","Scheduler adapts to data, hits optimal in 77 of 86 GPU-FPGA runs","DyPe: dynamic scheduling finds optimal GPU-FPGA config 77/86 times"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000711,"raw_usage":{"total_tokens":3254,"prompt_tokens":1051,"completion_tokens":2203,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":667,"completion_tokens_details":{"reasoning_tokens":2094}},"tokens_in":667,"tokens_out":2203,"duration_ms":14237,"temperature":1.0,"reasoning_tokens":2094,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-08T15:51:35.818445+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a set of GNN or transformer inputs whose sparsity and arithmetic intensity fall outside the synthetic training range, run DyPE's chosen schedule on the hardware alongside an exhaustive enumeration of all pipeline-stage and device-count allocations, and compare ranking; if the enumerated optimum beats DyPE's choice by more than the reported few percent in a substantial share of cases, the transferability assumption fails.","supporting_citations":[{"cited_title":"SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs","cited_arxiv_id":"2405.17025","evidence_quote":"Supplies the FPGA sliding-window attention design and its performance parameters, which DyPE adopts for transformer kernels."},{"cited_title":"Fleetrec: Large-scale recommendation inference on hybrid gpu-fpga clusters,","cited_arxiv_id":null,"evidence_quote":"FleetRec is the hybrid GPU-FPGA scheduling baseline whose fixed device-type assumption DyPE relaxes."},{"cited_title":"Direct gpu/fpga communication via pci express,","cited_arxiv_id":null,"evidence_quote":"Describes direct GPU-FPGA communication over PCIe, the mechanism the testbed uses for peer-to-peer transfers."},{"cited_title":"Sextans: A streaming accelerator for general-purpose sparse-matrix dense-matrix multiplication,","cited_arxiv_id":null,"evidence_quote":"Provides the Sextans FPGA SpMM streaming architecture whose hardware design and performance model DyPE adapts."},{"cited_title":"Flexible communication avoiding matrix multiplication on fpga with high-level synthesis,","cited_arxiv_id":null,"evidence_quote":"Supplies the FPGA GEMM implementation used to obtain dense-kernel performance."}],"review_version":1}