{"id":"718465de-4e04-426d-a329-b572a039f08e","arxiv_id":"2502.06573","paper_version":2,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":5.0,"correctness_risk":"low","formal_verification":"none","parameter_count":0,"one_line_summary":"Test beam data from the H2M 65 nm CMOS sensor show in-pixel efficiency and timing drop under the analog front-end n-well, an effect tied to n-well size and location.","lead":"A prototype pixel sensor made in a 65 nm CMOS process was tested in a particle beam. The chip works, but measurements show that each pixel responds unevenly: particles hitting near the analog circuitry's n-well are detected less efficiently and more slowly, a layout effect designers need to handle.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The paper's causal claim that the analog n-well causes the non-uniform in-pixel response is not established within the paper; the measured asymmetry is solid, but the mechanism rests on deferred companion simulations.","rationale":"The reader identified the same weakest assumption: causal attribution deferred to the companion paper. I agree. The stress-test does not find a more fundamental flaw. The test-beam measurement is a real empirical result; the efficiency/ToA maps show a clear non-uniformity, and the mitigation (high bias, low ikrum) is directly demonstrated in Fig. 2. The gap is the causal explanation. A conference paper can legitimately defer simulation details, but the verdict should remain conditional rather than accept the mechanism as proven. The concrete test above would settle whether the n-well is indeed the cause. No issue with correctness or internal consistency within the reported data was found.","tokens_in":4875,"tokens_out":4498,"duration_ms":108608,"concrete_test":"Run Allpix2/TCAD simulations of the H2M pixel using the exact analog n-well geometry from the layout, and repeat with the n-well removed while keeping all other implant and well structures unchanged; if the simulated efficiency/ToA map matches the measured asymmetric deficit only when the analog n-well is included, the causal claim is supported. As a separate data-only check, compute the correlation between the measured in-pixel efficiency deficit and the distance to the nearest analog n-well polygon, after masking a 2 µm band around the pixel-boundary implant gap; if the deficit does not peak on the n-well region, the attribution should be revised.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim of the paper is causal: the 4 µm-wide n-well in the analog front-end creates local potential wells that slow charge collection, producing the efficiency and ToA deficit observed in Fig. 3. What the paper actually demonstrates is a spatial correlation: the deficit appears in the region where the analog n-well is drawn in Fig. 1. The quantitative mechanism, including TCAD/Allpix2 simulations with the n-well and electronics, is deferred entirely to reference [11]. Because the explanation is the main forward-looking result (layout guidance for future submissions), this is load-bearing. The observed maps could in principle also be affected by the low-dose n-implant gap at the pixel boundaries, the offset placement of the collection electrode, or the deep p-well edge; the paper dismisses the digital n-wells as thin and uniform but provides no quantitative comparison of the deficit map against these alternative layout features. The empirical non-uniformity is robust; only the causal attribution to the analog n-well is unsupported within this paper. The absence of error bars on the maps and the qualitative overlay of layout and data make the correlation weaker than it could be, though this is secondary to the missing mechanism.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper presents the design, commissioning, and test-beam characterization of H2M, a prototype monolithic active pixel sensor in TPSCo 65 nm ISC technology with 35 × 35 µm² pixels and a digital-on-top architecture ported from hybrid pixel readout. The paper reports agreement of measured single-pixel noise and threshold dispersion with front-end simulations, efficiency/fake-hit curves versus threshold for three bias voltages and two feedback-current settings, and in-pixel maps of efficiency, time-of-arrival, and cluster size obtained by projecting tracks into four pixels. The main reported result is a strongly non-uniform in-pixel response: efficiency and timing degrade asymmetrically toward pixel edges and corners, with the deficit aligned with the analog front-end n-well. The authors attribute this response to potential wells that slow charge collection and to ballistic deficit in the fast front end, noting that detailed simulations are provided in a companion paper [11].","tokens_in":5044,"tokens_out":8078,"duration_ms":65817,"significance":"The empirical beam-test data are useful and timely: they document, for the first time, a clear layout-induced in-pixel non-uniformity in this 65 nm imaging process at 35 µm pitch, and they show an operating regime (high reverse bias, low ikrum, threshold 144 e−, efficiency 99.6%) where the effect is mitigated. The noise and threshold-dispersion results, together with the bias and ikrum dependence, are concrete inputs for future MAPS submissions. The main limitation is that the causal mechanism—the analog n-well as the source of the efficiency/timing deficit—is not demonstrated inside the paper; the quantitative simulations are deferred to [11]. If the mechanism is confirmed there, this will be an important design lesson; the measured non-uniformity remains a robust empirical result regardless.","major_comments":[{"comment":"The efficiency and ToA maps in Fig. 3 are the central evidence for the claimed non-uniformity, but no statistical uncertainty, bin occupancy, or track-count maps are reported. Particularly at the edges and corners, where the efficiency drops below 0.8, the deficit could in part reflect low per-bin statistics. Please add uncertainty maps or per-bin track counts and, if the deficit persists, state the significance of the drop.","section":"§3, Fig. 3"},{"comment":"The causal statement that the efficiency/timing deficit is produced by the 4 µm-wide analog n-well, through local potential wells at the p-well / low-dose n-implant interface, is supported only by a qualitative overlay of the drawn layout (Fig. 1) with the measured maps. Alternative layout features (the low-dose n-implant gap at pixel boundaries, offset of the collection electrode, and the digital n-wells) are not quantitatively excluded, and the TCAD/Allpix2 simulations with the n-well and electronics are only referenced as [11]. Since this mechanism is the main forward-looking conclusion, the paper should present at least one key simulation result (e.g., simulated efficiency/ToA map with and without the analog n-well) or explicitly label the mechanism as a hypothesis pending [11].","section":"§3, after Fig. 3"},{"comment":"The statement that 'at low hit detection thresholds (<180 electrons) and larger bias voltages, the in-pixel response remains uniform' with 99.6 % efficiency at 144 e− and -3.6 V is not accompanied by an in-pixel map at -3.6 V or by a statistical uncertainty for the 99.6 % value. Please show the map (or quantify the residual non-uniformity) and report the number of tracks, to support the claimed uniformity.","section":"§3, efficiency statement"},{"comment":"In Fig. 2a, the Allpix2 simulation with generic profiles is compared to data without an uncertainty band or description of threshold-conversion and model uncertainties; the observed data/simulation difference is then attributed to in-pixel non-uniformity. Reporting the simulated efficiency with statistical and systematic uncertainties would make the discrepancy argument quantitative rather than qualitative.","section":"§3, Fig. 2a"}],"minor_comments":[{"comment":"The axis labels in Fig. 3 appear as 'in-pixel xtrack [ m]' and 'in-pixel ytrack [ m]'; the micrometer symbol is missing and should be typeset as µm.","section":"Fig. 3"},{"comment":"The two ikrum settings are labeled only 'low' and 'high'; give the exact current or DAC values and, if available, the corresponding CSA integration time.","section":"Fig. 2b"},{"comment":"The simulated efficiency curve at -3.6 V would benefit from a caption statement of the simulation conditions (sensor thickness, collection electrode geometry, bias voltage, and whether any well structure is included) to make the comparison reproducible.","section":"Fig. 2a caption"},{"comment":"The cluster-size map is described as symmetric, but no quantitative symmetry measure is provided; a simple asymmetry metric would strengthen the claim.","section":"§3, Fig. 3c"}],"recommendation":"major_revision","confidential_remarks":"This is a conference proceedings contribution, and the main technical deficit is not the quality of the measurements but the deferral of the mechanism to the companion paper [11]. If [11] is published simultaneously and the present paper summarizes one quantitative simulation result, the causal claim would be adequately supported; otherwise the authors should reframe the n-well explanation as a hypothesis. I see no indication of circular analysis or any issue with data provenance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"You should know this paper for one reason: it documents a cleanly measured in-pixel efficiency and timing non-uniformity in a 35 µm-pitch 65 nm MAPS chip, and it shows that the effect can be mitigated by operating at high bias and low feedback current. That is a useful, concrete result for anyone designing large-pitch MAPS in this process. The chip itself is fully functional; noise and threshold dispersion match front-end simulations, and the efficiency/ToA maps directly show the spatial dependence. The paper is refreshingly honest: it says the effect is \"correlated with\" the analog n-well, not that causation is proven here, and it points to the companion simulation paper for the quantitative mechanism.\n\nWhat is genuinely new is the observation itself. Earlier smaller-pitch prototypes in the same technology did not see this, and the authors explain why the larger pitch and fast front-end make H2M more sensitive to field perturbations. The practical takeaway—uniform response at high bias and low ikrum, 99.6% efficiency at 144 e⁻—is well supported by the data.\n\nThe soft spot is exactly where the stress-test note lands. The causal claim—that the 4 µm analog n-well creates local potential wells and ballistic deficit—is not established inside this paper. What you have is a spatial correlation between the deficit and the drawn n-well position, plus a qualitative sketch of the mechanism. Alternative layout features, like the low-dose n-implant gap at pixel boundaries or the offset collection electrode, are mentioned but not quantitatively compared against the deficit map. There are also no error bars on the maps or the headline efficiency numbers, which makes the correlation weaker than it could be. These are real limitations, but they are not fatal: the measured asymmetry itself is robust, and the paper does not overclaim. It says \"correlated with,\" not \"caused by.\"\n\nFor a conference contribution, this is above average. The authors know the limits and have a companion paper for the full simulation. I would send it to peer review—a referee should ask for error bars and a more direct comparison with alternative layout features, but the core observation deserves to be in the literature. If you work on MAPS, cite it for the non-uniformity result and the operating-point guidance.\n\nRecommendation: accept with minor revisions, conditional on the companion paper actually delivering the mechanism.","headline":"A solid, honest test-beam characterization of a new 65 nm MAPS prototype showing a real in-pixel non-uniformity; the causal mechanism is plausible but deferred to a companion simulation paper.","tokens_in":5765,"tokens_out":1110,"would_cite":true,"duration_ms":15217,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["29.40.Gx"],"model":"deepseek-v4-flash","headline":"The H2M monolithic pixel sensor's response is non-uniform because the analog front-end's n-well perturbs charge collection, an effect that can be mitigated by higher bias and slower feedback.","keywords":["monolithic active pixel sensor","65 nm CMOS imaging","in-pixel response non-uniformity","charge collection","test beam characterization","pixel detector","ballistic deficit"],"falsifier":"Build a test structure identical to H2M but with the analog n-well removed or shifted to the pixel edge, and repeat the test beam measurements or a sub-micron laser scan: the slow, inefficient in-pixel region should move with the n-well or disappear entirely. If the drop in efficiency and time of arrival does not track the n-well footprint, the claimed causal mechanism is wrong.","tokens_in":4670,"feed_emoji":"🔬","tokens_out":6637,"duration_ms":55839,"temperature":0.7,"pith_summary":"The paper reports on the H2M test chip, a monolithic active pixel sensor made in a 65 nm CMOS imaging process with 35 µm square pixels, and shows that the chip's detection efficiency and time of arrival vary strongly with the position of the particle hit inside a pixel. The variation is traced to the n-well of the analog front-end circuit, which sits inside the deep p-well and alters the electric field so that charge released beneath it is collected more slowly. Because the front-end's integration time is only a few nanoseconds, those slower signals lose amplitude to ballistic deficit and can fall below threshold, lowering efficiency in that region. The authors show that raising the sensor bias and lowering the front-end feedback current restores a uniform, high-efficiency response, with 99.6% efficiency measured at a 144-electron threshold. The result matters because it identifies a layout-dependent mechanism that can make large-pitch 65 nm MAPS non-uniform unless the analog well is taken into account in the design.","feed_headline":"A chip's own analog wiring slows charge collection in its pixels","feed_subtitle":"Test beam maps show the slow zone sits under the analog n-well; higher bias and lower feedback restore 99.6% efficiency.","key_machinery":"The load-bearing object is the n-well of the analog front-end circuitry, a roughly 4 µm wide well containing PMOS transistors inside the deep p-well. The mechanism is that this well distorts the electric field at the p-well / low-dose n-implant interface, creating local potential wells that slow charge collection along paths underneath it. The second essential component is the charge-sensitive amplifier's feedback current $i_{\\text{krum}}$: it sets the slope of the CSA output's falling edge, i.e., the integration time. Slow signals lose amplitude because the CSA output starts to discharge before all charge is collected (ballistic deficit), so with a fast feedback the slow signals fall below the discriminator threshold. The 35 µm pitch matters because the lateral field components from neighbouring electrodes are farther apart, making the field more vulnerable to the n-well perturbation.","core_discovery":"The central claim is that the H2M sensor's non-uniform in-pixel response is caused by the analog front-end's n-well. The n-well is about 4 µm wide and hosts the PMOS transistors; it sits inside the deep p-well next to the collection electrode. It perturbs the electric field at the interface between the p-well and the low-dose n-type implant, creating local potential wells that slow charge collection along paths crossing that region. The measured efficiency and time-of-arrival maps show the slow, less-efficient region aligned with this n-well, while the cluster-size map remains symmetric, indicating charge sharing is unchanged. The effect is amplified by the 35 µm pitch and the fast front-end: slow signals are attenuated by ballistic deficit because the feedback current sets a short integration time. The paper presents simulations with generic doping profiles that do not include the wells and that predict a higher, uniform efficiency, so the difference with data is taken as evidence for the well's role; detailed simulations including the analog n-well and the electronics are reported in the companion paper [11]. With a bias of -3.6 V and low feedback current, the efficiency reaches 99.6% at a threshold of 144 electrons.","pith_inferences":["If the n-well mechanism is general, then moving or shielding the analog n-well, for example placing PMOS devices in wells outside the active pixel area or behind the collection electrode, should eliminate the slow region; this is a testable design change the paper hints at but does not make explicit.","The same mechanism implies that per-pixel timing corrections or position-dependent thresholds could be needed for 4D tracking with large-pitch MAPS, even when bias and feedback settings restore efficiency.","The ballistic-deficit explanation suggests the effect becomes stronger as the front-end is made faster; future designs targeting high rate capability may need to trade shaping time against the risk of position-dependent inefficiency, a trade-off the paper does not quantify.","Sub-micron laser scans of collection time versus n-well position could turn the qualitative spatial correlation into a quantitative map, directly testing the mechanism before detailed simulations are relied upon."],"forward_implications":["Future 65 nm MAPS designs must account for analog n-well placement and size, since layout-dependent charge-collection non-uniformity emerges once the pixel pitch is large enough.","Operating at higher bias voltage and lower feedback current recovers uniform in-pixel efficiency, making that the recommended operating point for high-efficiency applications.","Timing performance is position-dependent as well as efficiency: time-of-arrival maps show tens of nanoseconds of variation across a pixel, which would degrade time resolution if left uncorrected.","Smaller-pitch prototypes in the same technology do not show this non-uniformity, so the phenomenon is specific to large-pitch designs in this process."],"supporting_citations":[{"why":"Earlier 65 nm prototype with analogue pixel structures; establishes that the process works for MAPS and provides a smaller-pitch baseline.","marker":"[1]"},{"why":"Earlier 65 nm digital pixel test structures; again a smaller-pitch baseline against which H2M's non-uniformity is judged as new.","marker":"[2]"},{"why":"Describes the process modifications, including the low-dose n-implant with a gap at pixel boundaries, that define the sensor's field geometry and deep p-well layout.","marker":"[3]"},{"why":"Defines the feedback circuit whose current sets the CSA discharge slope, the parameter that controls ballistic deficit in the explanation.","marker":"[4]"},{"why":"Provides generic doping-profile simulations of efficiency that, not including the wells, predict a uniform response and therefore set up the discrepancy attributed to the n-well.","marker":"[10]"},{"why":"Companion paper with detailed simulations including the analog n-well and electronics; it supplies the full causal account of the non-uniformity and its amplification by pitch and front-end speed.","marker":"[11]"}],"fun_headline_variants":["Analog n-well slows charge collection in 65 nm pixel sensor","Pixel response uneven due to analog n-well in H2M sensor","H2M chip shows non-uniform pixels: analog n-well is culprit","How a tiny n-well makes some pixel regions slower","N-well's electric field distortion dims pixel response in H2M"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument assumes that the analog n-well—and not some other feature of the pixel layout—is what disturbs the electric field and slows charge collection; the paper's own evidence for this is a spatial correlation, with the detailed proof left to another paper. If the n-well were not the cause, the explanation would collapse even though the measured non-uniformity would remain.","fun_headline_variants_meta":{"raw":{"variants":["Analog n-well slows charge collection in 65 nm pixel sensor","Pixel response uneven due to analog n-well in H2M sensor","H2M chip shows non-uniform pixels: analog n-well is culprit","How a tiny n-well makes some pixel regions slower","N-well's electric field distortion dims pixel response in H2M"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000826,"raw_usage":{"total_tokens":3660,"prompt_tokens":1041,"completion_tokens":2619,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":657,"completion_tokens_details":{"reasoning_tokens":2540}},"tokens_in":657,"tokens_out":2619,"duration_ms":15300,"temperature":1.0,"reasoning_tokens":2540,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-08T15:00:19.175847+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Build a test structure identical to H2M but with the analog n-well removed or shifted to the pixel edge, and repeat the test beam measurements or a sub-micron laser scan: the slow, inefficient in-pixel region should move with the n-well or disappear entirely. If the drop in efficiency and time of arrival does not track the n-well footprint, the claimed causal mechanism is wrong.","supporting_citations":[{"cited_title":"Aglieri Rinella et al., Characterization of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process, Nucl","cited_arxiv_id":null,"evidence_quote":"Earlier 65 nm digital pixel test structures; again a smaller-pitch baseline against which H2M's non-uniformity is judged as new."},{"cited_title":"Aglieri Rinella et al., Digital pixel test structures implemented in a 65 nm CMOS process, Nucl","cited_arxiv_id":null,"evidence_quote":"Describes the process modifications, including the low-dose n-implant with a gap at pixel boundaries, that define the sensor's field geometry and deep p-well layout."},{"cited_title":"Snoeys et al., Optimization of a 65 nm CMOS Imaging Process for Monolithic CMOS Sensors for High Energy Physics, PoS, Pixel2022 (2023) 83","cited_arxiv_id":null,"evidence_quote":"Defines the feedback circuit whose current sets the CSA discharge slope, the parameter that controls ballistic deficit in the explanation."},{"cited_title":"Dannheim et al., Corryvreckan: a modular 4D track reconstruction and analysis software for test beam data, J","cited_arxiv_id":null,"evidence_quote":"Provides generic doping-profile simulations of efficiency that, not including the wells, predict a uniform response and therefore set up the discrepancy attributed to the n-well."},{"cited_title":"Wennlöf et al., Simulating Monolithic Active Pixel Sensors: A Technology-Independent Approach Using Generic Doping Profiles, Accepted for publication in Nucl","cited_arxiv_id":null,"evidence_quote":"Companion paper with detailed simulations including the analog n-well and electronics; it supplies the full causal account of the non-uniformity and its amplification by pitch and front-end speed."}],"review_version":1}