{"id":"3f9e5eb2-adc9-4602-815b-c5698d968267","arxiv_id":"2504.17090","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":3.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A QFT-based adder with X and SWAP pre/post-processing realizes reversible AND, NAND, OR, NOR, and XOR gates, with an asserted but unproven qubit scaling advantage for wide inputs.","lead":"This paper builds reversible quantum versions of AND, OR, XOR, NOR, and NAND gates by reading the sum and carry outputs of a quantum Fourier transform adder and wrapping it with X and SWAP gates. The authors claim the design uses fewer qubits than Toffoli-based gates when the number of inputs grows.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"N-input NAND via carry-out is wrong for non-power-of-two N: the carry of the sum is not the AND of all inputs.","rationale":"The reader's conditional verdict is reasonable for the 2-input circuits, which are verified by truth tables and follow from the known QFT-adder carry/sum mapping. However, the paper's strongest claim is the N-input scalability, and that claim fails under simple arithmetic: the carry-out of adding N one-bit numbers is not the AND of all inputs unless N is a power of two. The paper provides no N-input circuit or derivation, and the quoted N+log2 N count corresponds to an accumulator that records the sum, not to a detection of the all-ones pattern. The failure is a mathematical counterexample, not a matter of style or missing detail. It does not impugn the 2-input gate constructions themselves, and it is independent of whether one trusts the QFT adder's basic carry/sum mapping. A repair would require adding an equality-to-N comparison, which changes the qubit count and is absent from the manuscript. Because the advertised multi-input resource advantage is a central claim of the paper, the current manuscript should be rejected unless that claim is removed or substantially revised.","tokens_in":6710,"tokens_out":11262,"duration_ms":92400,"concrete_test":"Build the N=3 version of the proposed recipe: three data qubits in |1,1,0>, a two-qubit zero accumulator, and a QFT adder. After the addition, take NOT of the carry-out as the claimed NAND output. Binary addition gives accumulator value 2 (binary 10), so carry-out = 1 and the circuit outputs 0, while NAND(1,1,0) = 1. This can be settled by any quantum-circuit simulator or by a pencil-and-paper unitary check. If the authors intended an equality-to-N comparison instead of a raw carry, test separately whether the honest qubit count becomes N + ceil(log2(N+1)) rather than N + log2 N.","verdict_should_be":"REJECT","load_bearing_attack":"The scaling claim in Sec. 3 ('extracting the carry-out bit from a one-bit (n=1) N-input QFT-based adder ... N+log2 N') is not merely underived; as stated it is false for general N. A one-bit N-input adder computes k = sum of its inputs. Its carry-out (equivalently, the most significant bit of the accumulated sum) is high when k reaches a power-of-two threshold, not when k=N. For N=3 and inputs (1,1,0), k=2, so the carry-out is 1, while NAND(1,1,0)=1 and the proposed NOT-carry output would be 0. The same failure occurs for any non-power-of-two N (e.g., N=5 with four ones). The 2-input constructions are not affected, because for two one-bit inputs carry is exactly AND. To implement NAND for arbitrary N, one must compare the accumulated sum with N, a step that is neither described nor included in the N+log2 N qubit count. Thus the central resource-efficiency advantage over Toffoli-based designs is unsupported and, for the stated construction, incorrect.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a quantum Fourier transform (QFT)-based adder circuit used as a half-adder, and it implements two-input reversible Boolean gates (AND, NAND, OR, NOR, XOR) by applying pre- and post-processing gates around that adder. The truth tables for all five two-input gates are verified on the IBM Quantum Composer. The paper further claims that an N-input NAND gate can be obtained by extracting the carry-out bit of a one-bit N-input QFT-based adder, with a total qubit count of N + log2 N, and that this scaling offers a resource advantage over Toffoli-based designs.","tokens_in":6930,"tokens_out":9258,"duration_ms":85124,"significance":"The two-input gate constructions are correct: the carry output of the half-adder yields AND, the sum output yields XOR, and the De Morgan based pre- and post-processing for OR and NOR is sound and matches the expected truth tables for all four input states. The IBM Quantum Composer verification provides concrete evidence for these gates. However, the paper's advertised significance rests on the N-input scaling claim, which is false as stated for general N: the carry-out of the sum of N one-bit inputs does not equal the AND of all inputs except in special cases. This undermines the claimed qubit-count advantage over Toffoli-based designs, which the abstract, Section 3, and the Conclusion all present as the main motivation. The contribution is therefore reduced to a straightforward application of the known QFT half-adder to two-input gates.","major_comments":[{"comment":"The claim that extracting the carry-out bit from a one-bit N-input QFT-based adder implements N-input NAND is incorrect for general N. For N=3 with input state |110> (i.e., q0=1, q1=1, q2=0), the integer sum is 2, so the most significant bit of the sum (carry-out) is 1; inverting it gives 0, whereas NAND(1,1,0)=1. The carry-out of the sum of N one-bit inputs indicates whether the sum has reached a power-of-two threshold, not whether all N inputs are 1. The equality holds only in special cases (e.g., N=2, or N=2^k with an appropriately defined carry), and the paper states no such restriction. Since the N+log2 N qubit claim and the resource-efficiency advantage over Toffoli designs rest on this construction, this is a load-bearing error.","section":"Section 3 (Results and Discussion), paragraph beginning 'Quantum equivalents of classical logic gates have also been…"},{"comment":"The paper does not provide a definition or circuit diagram for the 'one-bit (n=1) N-input QFT-based adder', nor does it prove the carry-out mapping claimed for NAND. The N+log2 N qubit count is asserted by citing the authors' own reference [13], which is listed without volume, page, or year and is not accessible to the reader. Because this scaling claim is the central motivation of the manuscript, the construction should be fully specified and the carry-AND relation either derived or explicitly restricted to the cases where it actually holds.","section":"Section 3 (Results and Discussion), same paragraph; also Section 4 (Conclusion)"}],"minor_comments":[{"comment":"The sentence 'the measurement is applied on the |A⟩ qubit gives the Carry-bit encoded in c1 bit' is ungrammatical and should be revised for clarity.","section":"Section 2.C"},{"comment":"The claim that the approach 'reduces noise arising from interference between quantum channels' is not supported by any data or reference in the manuscript; it should be substantiated or removed.","section":"Introduction and Conclusion"},{"comment":"Reference [13] is incomplete; full bibliographic details (volume, page, year, DOI if available) should be provided.","section":"References"},{"comment":"The formula N + log2 N is used without stating that N must be a power of two; for non-integer log2 N the count is ill-defined, so the intended domain of the claim should be made explicit if it is retained.","section":"Section 3, N-input paragraph"}],"recommendation":"reject","confidential_remarks":"The paper's two-input gate constructions are correct and reproducible, but the manuscript's main significance is tied to an incorrect N-input NAND scaling claim. Removing that claim would leave a rather elementary application of the known QFT half-adder, which may not meet the novelty bar for this journal. The authors may wish to either substantially revise the scaling section or reposition the paper as a short note on two-input gates."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: the 2-input gates in Sec. III are correct, but they are not new, and the paper's advertised scaling advantage—N+log2 N qubits for an N-input NAND—is not merely underived; it is false for N>2. The stress-test is right: in a one-bit N-input adder, the carry-out (most significant bit of the sum) goes high when the accumulated sum reaches a power of two, not when all inputs are one. For N=3, inputs (1,1,0) sum to 2, so carry-out is 1 and NOT-carry is 0, while NAND(1,1,0)=1. The same failure occurs for every non-power-of-two N. So the central resource claim over Toffoli-based designs collapses.\n\nCredit where due: the two-input circuits are sound. The truth tables verified on IBM Composer match all four input states for AND, NAND, OR, NOR, and XOR. The diagrams are clear, and the authors correctly use the QFT adder's carry=AND and sum=XOR, with pre/post X and SWAP gates to get the other functions. That mapping is already in Draper and in Ruiz-Perez & Garcia-Escartin, and OR/NOR follow from De Morgan, but the verification is honest.\n\nSoft spots, in order of severity. First, the N-input NAND claim in Sec. 3 is load-bearing and wrong; it is cited to the authors' own [13] without derivation, and no N>2 circuit or data appear. Second, the conclusion's claim of improved noise resilience has no supporting measurements or argument. Third, the novelty is low: the 2-input constructions are a repackaging of known QFT-adder properties plus textbook Boolean identities.\n\nThis paper is not ready for peer review as a research article. A serious referee would have to flag the false scaling claim immediately. If the authors restricted the work to 2-input gates and removed the multi-input and noise claims, it might survive as a short educational note, but the advertised contribution does not stand. I would not cite it, and I would not bring it to reading group.","headline":"The 2-input QFT-adder gates are correct but known; the N-input scaling claim is false as stated.","tokens_in":7488,"tokens_out":3834,"would_cite":false,"duration_ms":35061,"reading_group":"no","serious_thinker":"no","would_accept_peer_review":false},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper presents a QFT-based adder circuit that implements AND, OR, XOR, NOR, and NAND reversibly, with an $N$-input NAND costing $N+\\log_2 N$ qubits.","keywords":["quantum Fourier transform","QFT-based adder","reversible logic gates","quantum NAND gate","Boolean logic in quantum circuits","De Morgan's laws","quantum half-adder","qubit resource reduction"],"falsifier":"On a statevector simulator, build the $N=3$ QFT-adder circuit exactly as specified and feed it all eight computational basis states; if the measured ancilla does not equal the AND of the three data bits in every case, the carry-out-as-NAND construction and the $N+\\log_2 N$ qubit count collapse.","tokens_in":6510,"feed_emoji":"⚛️","tokens_out":6617,"duration_ms":55366,"temperature":0.7,"pith_summary":"The paper claims that a one-bit, two-input QFT-based adder behaves like a reversible half-adder: its carry-out qubit evaluates the AND of the inputs and its sum qubit evaluates the XOR. From that single circuit, AND, NAND, OR, NOR, and XOR can be produced by adding only NOT gates before or after the adder, or a SWAP, with no change to the adder core. The central resource claim is that extracting the carry-out bit makes an $N$-input NAND gate cost $N+\\log_2 N$ qubits, against $2N-1$ qubits for a Toffoli-based construction. A sympathetic reader would care because, if correct, the same arithmetic block that performs addition also supplies a complete set of Boolean primitives with a qubit count that scales favorably for large input sizes.","feed_headline":"QFT adder yields five logic gates, NAND at N+log2 N qubits","feed_subtitle":"Carry and sum outputs of one reversible adder supply AND and XOR; X and SWAP gates make the rest.","key_machinery":"The central object is the QFT-based adder as a reversible half-adder: input qubits $|q_0\\rangle$ and $|q_1\\rangle$ plus ancilla $|A\\rangle$ initialized to $|0\\rangle$, with QFT, conditional phase gates, and inverse QFT, so that measuring $|A\\rangle$ gives the carry bit and measuring $|q_0\\rangle$ gives the sum bit. This one circuit carries the entire argument because every logic gate in the paper is the same adder with fixed pre- or post-processing: the carry channel already computes AND, the sum channel already computes XOR, and the NOT gates implement De Morgan's identities that convert AND into OR and NAND into NOR.","core_discovery":"The paper's central claim is that the QFT-based adder already contains the Boolean gates it appears to lack. Because the adder's ancillary qubit $|A\\rangle$ carries the AND of the two data inputs and its first data qubit $|q_0\\rangle$ carries their XOR, no new arithmetic structure is needed to realize logic: an X gate on the ancilla turns AND into NAND, X gates on both data inputs turn the carry into OR by De Morgan's law, the same two X gates without the post-processing X give NOR, and a SWAP between the ancilla and the first data qubit moves the XOR to the measured channel. The paper extends the two-input construction to $N$ inputs by reading the carry-out bit, obtaining an $N$-input NAND with $N+\\log_2 N$ qubits.","pith_inferences":["Beyond the paper, the same carry/sum extraction could be applied to a QFT-based full adder to produce multi-bit AND/XOR masks, letting the logic block scale beyond single-bit operations without a separate gate set.","The paper's verification is limited to two-input truth tables; a natural check is to run the stated $N$-input NAND construction for $N=3$ and $N=4$ on a statevector simulator, where any mismatch between the measured ancilla and the $N$-input AND would falsify the resource claim.","If the resource count survives that check, the practical trade-off worth measuring is circuit depth and gate count versus qubit savings, since QFT-based adders use more elementary gates for small inputs."],"forward_implications":["All five basic Boolean functions are reachable from one fixed adder template by choosing which wires get an X gate or a SWAP.","An $N$-input NAND requires $N+\\log_2 N$ qubits rather than the $2N-1$ qubits of a Toffoli-based construction, so the qubit advantage grows with input count.","The same circuit can serve as an arithmetic unit and a logic unit, since addition and Boolean operations share the same QFT-adder core.","Because the output is read from a single ancilla after a fixed set of single-qubit or SWAP gates, the method gives a uniform measurement pattern for all five gates."],"supporting_citations":[{"why":"Supplies the QFT-based addition primitive on which the carry/sum encoding rests.","marker":"[10]"},{"why":"Extends QFT arithmetic and justifies using the QFT adder as a reversible arithmetic block.","marker":"[11]"},{"why":"Prior QFT-based arithmetic logic unit that establishes the adder as an ALU building block and the source of the carry-out extraction idea.","marker":"[13]"},{"why":"Quantum composer used to verify the truth tables of all five constructed gates.","marker":"[20]"},{"why":"Provides the multiple-control Toffoli constructions that set the $2N-1$ qubit baseline the paper compares against.","marker":"[23]"},{"why":"Establishes that quantum gates are reversible, which is the premise for calling the QFT-adder logic gates reversible.","marker":"[6]"}],"fun_headline_variants":["QFT adder's carry and sum yield AND, OR, XOR, NOR, NAND","Five logic gates from one QFT adder's carry and sum","NAND at N+log2 N qubits from QFT adder's carry","QFT adder spawns five gates: AND, OR, XOR, NOR, NAND"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The entire gate set rests on the assumption, taken from prior QFT-adder work and checked only on a two-input composer truth table, that after the inverse transform the ancilla holds the AND (carry) and the first data qubit holds the XOR (sum); if that mapping is wrong for larger inputs, every constructed gate fails.","fun_headline_variants_meta":{"raw":{"variants":["QFT adder's carry and sum yield AND, OR, XOR, NOR, NAND","Five logic gates from one QFT adder's carry and sum","NAND at N+log2 N qubits from QFT adder's carry","QFT adder spawns five gates: AND, OR, XOR, NOR, NAND"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000916,"raw_usage":{"total_tokens":3879,"prompt_tokens":839,"completion_tokens":3040,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":455,"completion_tokens_details":{"reasoning_tokens":2953}},"tokens_in":455,"tokens_out":3040,"duration_ms":18909,"temperature":1.0,"reasoning_tokens":2953,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T10:49:25.975442+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On a statevector simulator, build the $N=3$ QFT-adder circuit exactly as specified and feed it all eight computational basis states; if the measured ancilla does not equal the AND of the three data bits in every case, the carry-out-as-NAND construction and the $N+\\log_2 N$ qubit count collapse.","supporting_citations":[{"cited_title":"Quantum Inf Process","cited_arxiv_id":null,"evidence_quote":"Extends QFT arithmetic and justifies using the QFT adder as a reversible arithmetic block."},{"cited_title":"Annalen der Physik","cited_arxiv_id":null,"evidence_quote":"Prior QFT-based arithmetic logic unit that establishes the adder as an ALU building block and the source of the carry-out extraction idea."},{"cited_title":"IBM Quantum Composer","cited_arxiv_id":null,"evidence_quote":"Quantum composer used to verify the truth tables of all five constructed gates."},{"cited_title":"In: Proc","cited_arxiv_id":null,"evidence_quote":"Provides the multiple-control Toffoli constructions that set the $2N-1$ qubit baseline the paper compares against."},{"cited_title":"Cambridge University Press (2012)","cited_arxiv_id":null,"evidence_quote":"Establishes that quantum gates are reversible, which is the premise for calling the QFT-adder logic gates reversible."}],"review_version":1}