{"id":"dd6614a9-2727-496e-bfa4-6e18d2cf5e27","arxiv_id":"2504.19626","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"The paper presents optimized quantum arithmetic circuits and active-volume block counts for a catalogue of low- and high-level subroutines, using temporary AND gates and orientated ZX diagram counting.","lead":"This paper gives new, cheaper quantum circuits for arithmetic such as multiplication, square root, and logarithms, and estimates their resource use on a fault-tolerant 'active volume' architecture. It offers designers concrete cost numbers for choosing subroutines in large quantum computations.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Eq. (19a) is not derivable from the paper's own arcsine parts list: the explicit CNOT counts and the temporary-AND compute/uncompute accounting do not match the stated sum.","rationale":"The reader identified the Section 2 optimization heuristic as the weakest assumption. That is a scope caveat, but it does not test the literal content of the strongest claim, which is that the displayed formulas give logical block counts for the chosen circuits. A formula can be correct for a chosen design even when the design is not globally optimal. The arcsine formula is different: it should equal the sum of the costs its own construction incurs, and a direct accounting of the stated parts shows discrepancies in the CNOT and temporary-AND contributions. This is the most load-bearing point because Eq. (19a) is one of the formulas explicitly named in the strongest claim and it directly feeds the resource-estimation contribution. If Eq. (19a) is wrong, the arcsin resource count is wrong regardless of the optimization heuristic. I would keep the reader's conditional verdict rather than reject outright, because the T-count reductions and low-level circuits may stand on their own, but the condition must include a corrected, independently checkable derivation of the high-level AV formulas, and ideally accessible simulation code for the high-level constructions. This partially agrees with the reader, who noted equation/table inconsistencies but placed the weakest-assumption weight on the Section 2 optimality claim.","tokens_in":28479,"tokens_out":29326,"duration_ms":282471,"concrete_test":"Independently re-derive Eq. (19a) by summing the six parts of §4.3 using the paper's own elementary costs: CNOT = 4 blocks, temporary-AND compute = 9+C, uncompute = 5, Toffoli = 12+C, and Eqs. (1a), (2a), (3a), (8a), (13a), (14a), (15a). Specifically, add 4(n+1) + 4n + 4(2n+1) for the explicit CNOTs in Parts 1, 4, and 6, and replace the (2n+1)(14+C) temporary-AND term with (n+1)(9+C) + (n+1)(5). If the resummed polynomial differs from Eq. (19a) by any nonzero term, the active-volume formula for arcsin is not derivable from the stated circuit; if it matches, the concern is refuted.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The strongest claim explicitly names Eq. (19a) as giving the logical block count for the arcsin subroutine. In §4.3 the formula is assembled as 2V_poly + 2V_sqrt + 2V_CAS + 2nV_Toff + (2n+1)(V_tmpAND^cmp + V_tmpAND^uncmp) + 2V_cshift + 3V_cincrem. But the same section's parts list contains, outside those components, n+1 CNOTs in Part 1, n CNOTs for the pi/2 initialization in Part 4, and 2n+1 CNOTs in Part 6. Since a CNOT costs 4 logical blocks in the paper's own accounting, Eq. (19a) lacks a 4(4n+2) = 16n+8 block term unless those CNOTs are absorbed by a compression that is not shown. The temporary-AND accounting is also inconsistent: Parts 2, 3, and 5 use n+1 compute gates and n+1 uncompute gates, costing (n+1)(9+C) + (n+1)(5), while Eq. (19a) charges (2n+1)(14+C). These are internal derivability failures, not a dispute about the Section 2 optimality heuristic: a reader using Eq. (19a) as the active volume of the described circuit gets a number that does not follow from the circuit's own stated resources. The claimed AV estimates therefore lack a checkable derivation at exactly the point where the paper promises exact logical block counts.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports new low-level arithmetic circuits (a controlled addition/subtraction CAS adder, a controlled overflow COG adder, an output-carry OG adder, incrementers, controlled shifts, and a k-controlled NOT construction) and assembles them into high-level arithmetic subroutines (square root, piecewise polynomial evaluation, arcsine, and logarithm). For each subroutine it gives a T count, a reaction depth, and an active-volume block-count formula in the Litinski active-volume architecture, using orientated ZX diagrams and the stated assumption that the cheapest baseline circuit in T count and qubit count also gives the smallest active volume. The low-level circuits are reported to have been verified by Qiskit simulation, and a link to the simulation code is provided.","tokens_in":28809,"tokens_out":17545,"duration_ms":167806,"significance":"If the formulas were all correct, this would be a useful catalogue: it extends active-volume accounting to several practical arithmetic blocks and gives concrete, well-defined T-count reductions over earlier designs by Häner et al. and Muñoz-Coreas and Thapliyal. The Qiskit verification of the low-level circuits and the explicit per-block costing are strengths, and the k-controlled NOT construction is a simple and genuinely useful improvement. However, the active-volume numbers are only as reliable as the component algebra, and the arcsine formula fails an internal check; a second formula in the logarithm section also does not match its own component definitions. Because the paper advertises exact logical block counts, these derivability failures are central rather than cosmetic.","major_comments":[{"comment":"The printed arcsine active-volume formula is not derivable from the parts list given in the same section. The parts list contains n+1 CNOTs in Part 1, n CNOTs for the pi/2 initialization in Part 4, and 2n+1 CNOTs in Part 6; at the paper's own cost of 4 blocks per CNOT these contribute 16n+8 blocks, and no term for them appears in Eq. (19a). In addition, Parts 2, 3, and 5 contain n+1 temporary-AND compute gates and n+1 temporary-AND uncompute gates, so their contribution should be (n+1)(9+C|CCZ>) + (n+1)(5) = (n+1)(14+C|CCZ>), not the (2n+1)(14+C|CCZ>) used in the equation. Expanding the left-hand side of Eq. (19a) with Eqs. (3a), (8a), (13a), (2a), and (1a) also does not reproduce the right-hand side of Eq. (19a). The discrepancy therefore cannot be attributed to a missing explanatory sentence; the formula as printed is internally inconsistent, and Section C's summary table inherits the same numbers.","section":"§4.3, Eq. (19a)"},{"comment":"The logarithm multiplication active volume is also not derivable from the stated component costs. Eq. (22a) defines V_log_mult = (alpha-1) V_COGA + n V_Toff and then gives the result as [(27+2C|CCZ>)alpha - 23 - 2C|CCZ>]n + (18+2C|CCZ>)alpha - 18 - 2C|CCZ>. However, substituting V_COGA = (30+2C|CCZ>)n + 15 + 2C|CCZ> from Appendix A.4 and V_Toff = 12 + C|CCZ> from Section 3.4 yields [(30+2C|CCZ>)alpha - 18 - C|CCZ>]n + (15+2C|CCZ>)(alpha-1). These expressions are not equal for general alpha, so Eq. (22a) is unsupported. Since Eq. (22a) feeds Eq. (23a), the log active-volume estimate is likewise not checkable from the manuscript as written.","section":"§4.4, Eq. (22a)"},{"comment":"The claim that the reported active volumes are 'optimised' rests entirely on the stated assumption that the lowest-T-count, lowest-qubit baseline circuit also has the smallest active volume. The paper explicitly identifies this as an assumption and does not test it; it never computes the active volume of a competing baseline design. The paper's own Fig. 10 shows that circuit structure beyond gate counts changes active volume, so the assumption is not a trivial consequence of gate-count minimization. The abstract and conclusion should therefore distinguish the T-count reductions, which are established by construction, from the active-volume estimates, which are resource estimates for the specific circuits presented rather than proven optima. Alternatively, the assumption should be tested on at least one subroutine for which a genuinely different baseline design is available.","section":"§2"}],"minor_comments":[{"comment":"The parenthetical '(20-C|CCZ>)' in the text should presumably read '(20+C|CCZ>)', since the following formula uses a sum rather than a difference; the sign error is confusing in a cost calculation.","section":"§3.2"},{"comment":"The notation C|CZZ> appears in Eqs. (14a), (15a), and the summary tables, while the rest of the paper uses C|CCZ>; please make the notation uniform.","section":"§4.2 and Section C"},{"comment":"There are several typographical and name errors, including 'Muñoz-Coraes' for 'Muñoz-Coreas' in Section 4.1, 'appdendix' in the caption of Fig. 8, and 'Häner’s' inconsistently spelled; a careful proofreading pass is needed.","section":"Throughout"},{"comment":"The final section honestly states that memory requirements and effective reaction depth are ignored, but the abstract and conclusion still describe the results in terms that readers may read as runtime improvements. The caveat that all comparisons are block-count/resource estimates under a fixed reaction-depth model should be stated wherever the AV reductions are summarized.","section":"§5, Limitations"},{"comment":"The sentence 'This is an approximately 8% reduction in active volume' should state which baseline is being used for the percentage; the naïve block cost is given immediately before, but the comparison should be explicit.","section":"§3.3"},{"comment":"The baseline comparison against Li et al. [32] reports no active volume for the competitor and explains why; this is a fair limitation, but the table and text should make clear that the claimed advantage is in T count and reaction depth, not in demonstrated active volume.","section":"§3.4.1"}],"recommendation":"major_revision","confidential_remarks":"The main obstacle is not the Section 2 optimality assumption, which is at least stated openly, but the internal algebraic failures in Eqs. (19a) and (22a). These are fixable in a revision, but they are exactly the kind of error that prevents the paper's central resource tables from being used. I would ask the author to provide a machine-checkable expansion of every V formula from its named components, or to include the expansion script alongside the Qiskit code, before the manuscript is accepted. The T-count comparisons and low-level circuit constructions are worthwhile and should not be lost in revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nQuick take: this paper is worth reading for the new adder and k-controlled NOT constructions, but don't trust the arcsine active-volume number — Eq. (19a) does not follow from the circuit parts list in Section 4.3. I checked the stress-test note and it holds. Part 1 lists n+1 CNOTs, Part 4 lists n CNOTs for the pi/2 initialization, and Part 6 lists 2n+1 CNOTs; at 4 blocks each, that's 16n+8 blocks that appear nowhere in Eq. (19a). The temporary-AND accounting is also off: Parts 2, 3, and 5 contain n+1 compute and n+1 uncompute gates, costing (n+1)(9+C) + (n+1)(5), but the formula charges (2n+1)(14+C). And the bracket in Eq. (19a) has +n where 2Vpoly would give -n. So the flagship high-level formula is internally inconsistent.\n\nWhat's genuinely good: the CAS, COG, and OG adder designs are new, the k-controlled NOT with 4T per Toffoli is a nice construction, and the low-level circuits are verified by Qiskit simulation. The paper is also the first to give active-volume estimates for square root, PPE, arcsine, and log, which is a useful service to the resource-estimation community. The method is a direct application of Litinski's OZX block counting, but that's fine — catalogues need to be built on a consistent counting method.\n\nThe soft spots beyond Eq. (19a): the Section 2 assumption that lowest T-count/qubit circuits give lowest active volume is stated but never tested; the paper even notes that circuit structure matters, so the assumption isn't self-evident. The simulation code is referenced but not linked. The Limitations section honestly flags memory and reaction depth, which is good, but it means the reported improvements are upper-bound-ish in practice.\n\nNet: the low-level T-count reductions look solid and the adder constructions deserve a real referee. The high-level AV formulas need a careful derivation pass before they can be used as reference numbers. I'd send it out — the errors are fixable and the contribution is real.","headline":"Useful new adder constructions and a first active-volume catalogue, but the arcsine active-volume formula does not follow from the paper's own parts list; treat the high-level AV numbers as provisional until the derivations are fixed.","tokens_in":29308,"tokens_out":7555,"would_cite":false,"duration_ms":57567,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Quantum arithmetic subroutines get lower T counts and exact active-volume formulas.","keywords":["active volume architecture","quantum arithmetic circuits","T count optimization","orientated ZX diagrams","fault-tolerant quantum computing","magic state distillation","surface code spacetime blocks","reaction depth"],"falsifier":"Take the alternative multiplier design cited as [32], convert it to an orientated ZX diagram, and count blocks at a fixed width such as $n=8$. If its active volume comes out below Eq. (5a) even though its T count is higher, then the Section 2 assumption is false and the paper's active-volume formulas are not the minimum for that function.","tokens_in":28272,"feed_emoji":"🧮","tokens_out":10003,"duration_ms":98213,"temperature":0.7,"pith_summary":"This paper claims that standard quantum arithmetic operations—controlled addition/subtraction, addition with overflow, multiplication, squaring, square root, piecewise polynomial evaluation, arcsine, and logarithm—can be built with lower T counts than prior designs and that their cost on an active-volume fault-tolerant computer is captured by explicit closed-form formulas. The significance is practical: active-volume architectures charge only for logical blocks that do work, so a catalogue of subroutine block counts turns algorithm-level resource estimation into a sum of known terms. For a reader, the paper's claim is that both gate count and circuit geometry matter, and that orientated ZX diagrams provide a way to see and optimize that geometry.","feed_headline":"New quantum arithmetic circuits cut T counts and shrink active volume","feed_subtitle":"Algorithm designers gain closed-form block counts for arithmetic, roots, arcsine, and logarithm.","key_machinery":"The load-bearing machinery is the orientated ZX diagram (OZX): a ZX-calculus diagram whose spiders may connect only through six direction ports, with each surviving spider corresponding to one surface-code spacetime logical block. The conversion pipeline runs circuit diagram to ZX diagram to compressed ZX diagram to OZX diagram, then counts spiders and adds magic-state distillation costs. The second load-bearing gadget is the temporary AND gate, which replaces Toffoli pairs in addition-type circuits and halves the T count; when its un-compute part commutes with everything in between, a compute/un-compute pair costs the same as one Toffoli and fits in one reaction-depth layer. Long uninterrupted strings of controls and targets merge into fewer Z spiders, which is the structural mechanism behind the block-count savings.","core_discovery":"The central discovery is a collection of arithmetic circuits whose active volume is known exactly on the active-volume architecture. For example, the controlled addition/subtraction (CAS) adder costs $(25+C_{|CCZ\\rangle})n-20-C_{|CCZ\\rangle}$ blocks, the controlled adder with output carry used for multiplication costs $(30+2C_{|CCZ\\rangle})n+15+2C_{|CCZ\\rangle}$, multiplication costs $(30+2C_{|CCZ\\rangle})n^{2}+(C_{|CCZ\\rangle}-3)n-15-2C_{|CCZ\\rangle}$, and the square-root circuit costs $\\frac{1}{4}(25+C_{|CCZ\\rangle})n^{2}+(39+2C_{|CCZ\\rangle})n-46-6C_{|CCZ\\rangle}$, with $C_{|CCZ\\rangle}\\approx 35$ the distillation cost of a CCZ magic state. The same designs carry T-count reductions, for example $4n-4$ for controlled add/subtract and $n^{2}+10n+8$ for square root, and the method extends to piecewise polynomial evaluation, arcsine, and logarithm.","pith_inferences":["A consequence the paper leaves implicit: if the Section 2 assumption is relaxed, every formula here is best read as an upper bound rather than a proven minimum, and structural search over equivalent circuits could lower these block counts further.","The same temporary-AND $k$-controlled NOT construction could be dropped into other multiply-controlled contexts, such as table lookups or exponentiation, where the paper does not apply it, with a similar three-quarter T-count reduction.","The log cost formula omits the classical cost of determining the shift parameters $l$ and $v$; an end-to-end resource estimate would need either a reversible circuit that derives those parameters or an explicit classical pre-processing budget.","Because reaction depths are reported as upper bounds obtained by summing component depths, a layer scheduler for a fixed number of workspace modules could yield lower actual runtimes than the depth formulas suggest."],"forward_implications":["The subroutine costs can be summed modularly: any algorithm built from these pieces has active volume obtained by inserting Eqs. (3a), (5a), (8a), (16a), (19a), and (23a) into the total, enabling resource estimates without re-deriving block counts.","The T-count reductions transfer: controlled addition/subtraction at $4n-4$, an add-with-overflow adder at $4n$, multiplication at $8n^2+4n-8$, square root at $n^2+10n+8$, and a roughly six-fold drop in the leading T-count term for arcsine.","The $k$-controlled NOT built from $k-1$ temporary AND gates has T count $4k-4$, about a quarter of the $16(k-2)$ baseline, and the same construction feeds the NEXT operation in polynomial evaluation.","Shifts are free in the active-volume architecture: a fixed-point shift is just relabelling data-qubit modules, so shift costs disappear from resource estimates.","Circuit structure, not just gate counts, changes active volume: the appendix exhibits two equivalent three-qubit out-of-place additions with identical gate sets that cost 21 and 17 blocks."],"supporting_citations":[{"why":"Defines the active-volume architecture, the orientated ZX diagram block-counting rules, and the elementary gate block costs used throughout.","marker":"[7]"},{"why":"Introduces the temporary-AND adder whose modified segments become the CAS, OG, and COG adders.","marker":"[25]"},{"why":"Supplies the piecewise-polynomial-evaluation construction and its cost equations, which the paper rebuilds with its own subroutines.","marker":"[20]"},{"why":"Supplies the non-restoring square-root algorithm whose parts the paper optimises and sums into a new block-count formula.","marker":"[19]"},{"why":"Provides the T-count-optimised multiplier used as the baseline comparison for the new multiplication cost.","marker":"[21]"},{"why":"Establishes the four-T-gate implementation of a Toffoli gate that converts every Toffoli count to a T count.","marker":"[28]"},{"why":"Provides the reaction-depth model, the CCZ distillation cost, and active-volume costs of elementary operations and adders.","marker":"[12]"},{"why":"Supplies the incrementer circuit that the paper modifies with temporary AND gates for the increment and controlled-increment subroutines.","marker":"[30]"},{"why":"Provides the function-value binary expansion method that the paper generalises into the logarithm subroutine.","marker":"[18]"}],"fun_headline_variants":["Quantum arithmetic circuits cut T counts and trim active volume","Exact active volume formulas for quantum arithmetic subroutines","Quantum adders, multipliers, and sqrt get T-count and volume gains","Lower T counts and known active volume for quantum arithmetic","Quantum arithmetic with exact active volume and reduced T counts"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing assumption is stated in Section 2: a circuit with the lowest T count, fewest qubits, and smallest baseline circuit volume will also have the smallest active volume. If that correlation fails—if a slightly bigger circuit can be arranged in a way that produces far fewer orientated ZX spiders—the reported block counts are upper bounds, not minima.","fun_headline_variants_meta":{"raw":{"variants":["Quantum arithmetic circuits cut T counts and trim active volume","Exact active volume formulas for quantum arithmetic subroutines","Quantum adders, multipliers, and sqrt get T-count and volume gains","Lower T counts and known active volume for quantum arithmetic","Quantum arithmetic with exact active volume and reduced T counts"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001184,"raw_usage":{"total_tokens":4867,"prompt_tokens":902,"completion_tokens":3965,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":518,"completion_tokens_details":{"reasoning_tokens":3884}},"tokens_in":518,"tokens_out":3965,"duration_ms":29260,"temperature":1.0,"reasoning_tokens":3884,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T05:48:16.510345+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take the alternative multiplier design cited as [32], convert it to an orientated ZX diagram, and count blocks at a fixed width such as $n=8$. If its active volume comes out below Eq. (5a) even though its T count is higher, then the Section 2 assumption is false and the paper's active-volume formulas are not the minimum for that function.","supporting_citations":[{"cited_title":"Halving the cost of quantum ad- dition,","cited_arxiv_id":null,"evidence_quote":"Introduces the temporary-AND adder whose modified segments become the CAS, OG, and COG adders."},{"cited_title":"Optimizing quantum circuits for arith- metic,","cited_arxiv_id":null,"evidence_quote":"Supplies the piecewise-polynomial-evaluation construction and its cost equations, which the paper rebuilds with its own subroutines."},{"cited_title":"T- count and qubit optimized quantum circuit design of the non-restoring square root al- gorithm,","cited_arxiv_id":null,"evidence_quote":"Supplies the non-restoring square-root algorithm whose parts the paper optimises and sums into a new block-count formula."},{"cited_title":"Quan- tum circuit design of a t-count optimized integer multiplier,","cited_arxiv_id":null,"evidence_quote":"Provides the T-count-optimised multiplier used as the baseline comparison for the new multiplication cost."},{"cited_title":"Low-overhead constructions for the fault-tolerant toffoli gate,","cited_arxiv_id":null,"evidence_quote":"Establishes the four-T-gate implementation of a Toffoli gate that converts every Toffoli count to a T count."},{"cited_title":"How to compute a 256-bit el- liptic curve private key with only 50 million toffoli gates,","cited_arxiv_id":null,"evidence_quote":"Provides the reaction-depth model, the CCZ distillation cost, and active-volume costs of elementary operations and adders."},{"cited_title":"A class of ef- ficient quantum incrementer gates for quan- tum circuit synthesis,","cited_arxiv_id":null,"evidence_quote":"Supplies the incrementer circuit that the paper modifies with temporary AND gates for the increment and controlled-increment subroutines."},{"cited_title":"Quantum circuits de- sign for evaluating transcendental functions based on a function-value binary expansion method,","cited_arxiv_id":null,"evidence_quote":"Provides the function-value binary expansion method that the paper generalises into the logarithm subroutine."}],"review_version":1}