{"id":"e26c3f61-c8cd-4645-a611-87b1add4fe69","arxiv_id":"2504.19797","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"An FPGA accelerator called DTM trains Vanilla and Coalesced Tsetlin Machines on-chip with runtime reconfiguration, reporting higher energy efficiency than prior FPGA training designs.","lead":"A team at Newcastle University built FPGA hardware that can train Tsetlin Machine models on-device, using logic gates instead of floating-point math. The design can switch between model types and sizes at run time, which could make low-power edge devices easier to recalibrate.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The abstract's 6x power claim appears to compare DTM-S IP-only power (0.424 W) with FireFly's system-level power (2.550 W), an inference-only design; no apples-to-apples row in Table I yields 6x.","rationale":"The architecture itself is described in enough detail that the runtime-reconfigurable Vanilla/CoTM training design appears plausible, and the central algorithmic mapping to LUTs, BRAMs, and PRNGs is internally consistent. The load-bearing weakness is not the logic design but the headline quantitative comparison: the claimed 6x power advantage cannot be derived from any consistent reading of Table I, and the 2.54x GOP/s/W ratio rests on an undefined operation metric. The reader's weakest-assumption analysis identified the same underlying issue, namely that GOP/s and power are not normalized across designs with different algorithmic bases, power boundaries, and training/inference modes. My check sharpens this by showing that the only Table I ratio near 6.0 is the mismatched FireFly-system versus DTM-S-IP pairing. This is a significant concern because the abstract's central claim is exactly that quantitative advantage; the concern can be settled by reconstructing the comparison with explicit operation definitions and consistent power boundaries. Since the reader already issued a conditional verdict asking for such normalization, no verdict change is needed, though the paper would be materially strengthened by adding a reproducible apples-to-apples table.","tokens_in":19822,"tokens_out":5659,"duration_ms":55285,"concrete_test":"Reconstruct the efficiency comparison from Table I and Fig. 11 using one normalized operation definition and consistent power boundaries. First, define operation count for DTM and Conv TM from the architecture's clock cycles per MNIST training update, counting each clause literal evaluation as one operation and each weight multiply-add as one operation, and apply the same rule to FireFly and SNN. Second, recompute all pairwise GOP/s/W ratios using system-level power only and IP-only power only. If the abstract's 6.0x power ratio appears only when FireFly system power is divided by DTM-S IP power, and the 2.54x efficiency ratio does not survive when operation counting and power boundary are held fixed across all compared designs, the headline claim should be revised or replaced with a scope-limited statement.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The headline efficiency claim requires a well-defined 'next-best comparable design' and consistent measurement boundaries. In Section V and Table I, DTM-S/DTM-L report system-level power including the ARM core, with IP-only power in parentheses; Conv TM similarly reports both. The only ratio in Table I that yields the abstract's '6x less power' is FireFly's system power (2.550 W) divided by DTM-S IP-only power (0.424 W), which is 6.01x. FireFly is an inference-only SNN accelerator, and DTM-S IP excludes ARM/SoC power, so this is neither a comparable-design nor a comparable-power-boundary comparison. Under apples-to-apples pairings, the table gives about 4.7x (Conv TM IP vs DTM-S IP), 2.7x (Conv TM SYS vs DTM-S SYS), or 3.1x (SNN SYS vs DTM-S SYS), none equal to 6x. The same Section V text states that system-level power is reported for DTM and Conv TM, making the 6x pairing especially suspect. The 2.54x GOP/s/W claim is also not independently checkable from the text because GOP/s is never defined: no operation count per clause, weight multiplication, or TA update is given, and Fig. 11 mixes training and inference-only designs. These issues do not invalidate the architecture, but they leave the abstract's quantitative superiority claim unsupported by the presented evidence.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper presents a Dynamic Tsetlin Machine (DTM) FPGA accelerator that supports both inference and on-chip training for Vanilla and Coalesced Tsetlin Machines. The architecture uses partial clause computation, a master-slave LFSR PRNG cluster with seed refreshing, runtime reconfiguration through masks and iteration cycles, and an optimized TA-update skipping mechanism. The design is parameterized and instantiated on two platforms (DTM-S on XC7Z020, DTM-L on ZU-7EV). Evaluation reports accuracy on MNIST, FMNIST, KMNIST, and KWS-6, resource utilization, power from Vivado, and comparisons with earlier FPGA accelerators, claiming 2.54x higher GOP/s/W and 6x lower power than the next-best comparable design.","tokens_in":20174,"tokens_out":4884,"duration_ms":42770,"significance":"If the architectural claims are validated, the paper makes a useful contribution: it appears to be the first published CoTM hardware implementation, it demonstrates runtime reconfiguration without resynthesis, and it maps TM training to LUTs/BRAMs with modest DSP use. The architecture description is detailed and internally coherent, with algorithms for clause, class-sum, and feedback computation. However, the two headline quantitative advantages (2.54x GOP/s/W and 6x lower power) are not supported by the evidence in the manuscript as written, because the comparisons mix power boundaries and the GOP/s metric is undefined. The underlying design is valuable, but the paper should be revised to substantiate or properly qualify these claims.","major_comments":[{"comment":"The abstract's claim of '6x less power than the next-best comparable design' is not supported by the table. The only ratio in Table I that yields approximately 6x is FireFly's system-level power (2.550 W) divided by DTM-S's IP-only power (0.424 W). FireFly is an inference-only SNN accelerator, and DTM-S's IP-only power excludes the ARM/SoC power that is included in DTM-S's own system-power column (1.687 W). Apples-to-apples pairings in Table I give roughly 4.7x (Conv TM IP vs DTM-S IP), 2.7x (Conv TM SYS vs DTM-S SYS), or 3.1x (SNN SYS vs DTM-S SYS), none of which is 6x. Please state explicitly which designs and which power boundaries are being compared, and use consistent measurement boundaries for the headline claim.","section":"Section V, Table I and Abstract"},{"comment":"The 2.54x GOP/s/W claim is not checkable from the manuscript because 'operations' is never defined for the DTM or for the compared accelerators. No operation count per clause computation, per weight multiply, or per TA update is given, and Fig. 11 mixes training accelerators with inference-only designs. Without a normalized operation definition, the efficiency ratio cannot be established. The paper should either define the operation count and justify its comparability across papers, or replace the GOP/s/W ratio with a better-specified metric such as training datapoints/s/W, which would align with Table II.","section":"Section V, Fig. 11"},{"comment":"The accuracy results are presented without hyperparameter values (T, s, number of clauses for the specific rows, weight precision) or run-to-run variation, even though the architecture's learning efficacy depends on these parameters. The text states that accuracies are from 250 epochs, but without the exact configurations for each row the comparison is not reproducible. Please provide the hyperparameter configuration used for each reported accuracy, at least in supplementary material.","section":"Section V, Tables I-II"}],"minor_comments":[{"comment":"There are grammatical errors that should be corrected: 'Users does not need' should be 'Users do not need', and 'they will is always 0' should be 'they will always be 0'.","section":"Section IV-A-a and IV-A-f"},{"comment":"Power is reported from Vivado implementation reports, which is simulation-based power and may not reflect board-level measurements; the paper should note this limitation in the comparison.","section":"Section V"},{"comment":"Table I includes SATA, a 65nm ASIC simulation, in an FPGA comparison; while the text acknowledges that SATA is an ASIC, the table caption should also flag it as non-FPGA to avoid misleading readers.","section":"Table I"},{"comment":"The text claims 'the first CoTM hardware' without describing a prior-art search; a brief statement of how this was determined would strengthen the contribution claim.","section":"Section II"},{"comment":"The caption of Fig. 11 appears malformed in the manuscript ('YOLO v3 [23],' is repeated); please clean up the caption.","section":"Fig. 11 caption"}],"recommendation":"major_revision","confidential_remarks":"The architecture appears sound and the work is likely of interest to the TCAS-I readership. The main revision needed is to substantiate the efficiency claims with consistent comparisons; I would support acceptance after that. I also note that a large fraction of the cited baselines are from the same research group, which may have influenced the choice of comparable designs; adding independent baselines (e.g., an open-source TM or SNN accelerator with measured power) would increase confidence."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The architecture is the real contribution here. As far as I can tell from the cited work, this is the first Coalesced Tsetlin Machine hardware, and the runtime reconfiguration between Vanilla and CoTM, the clause-feedback skip, and the LFSR seed-refresh PRNG are all new. The paper gives enough detail in the block diagrams and algorithms that someone could rebuild it. The clause-feedback skip cutting training time by about 40% at similar accuracy is a concrete, believable win.\n\nThe evaluation is where things get shaky. The abstract says 2.54x GOP/s/W and 6x lower power against \"the next-best comparable design,\" but Table I does not support those numbers. The 6x only appears if you divide FireFly's system power (2.550 W) by DTM-S's IP-only power (0.424 W), and FireFly is an inference-only SNN accelerator. That is neither a comparable design nor a consistent power boundary. Apples-to-apples, you get roughly 4.7x against Conv TM's IP power or 2.7x against its system power. The 2.54x GOP/s/W is also not checkable because GOP/s is never defined: no operation count per clause, weight multiply, or TA update is given, and Fig. 11 mixes training and inference-only designs. Power numbers come from Vivado estimates, not board measurements. Accuracy is reported without error bars, hyperparameters, or multiple seeds. These are not fatal to the architecture, but they are fatal to the headline efficiency claims as stated.\n\nThe good news is the central idea does not depend on those ratios. The detailed resource and latency breakdowns, the scalability story across two FPGAs, and the KWS-6 reconfiguration experiments all indicate a functional, well-thought-out design. I would not be surprised if the efficiency is genuinely good once measured consistently.\n\nThe paper is for people working on TM hardware, FPGA-based edge training, and logic-based alternatives to DNN backpropagation. It deserves a serious referee. I would send it out, but I would ask the authors to redo the efficiency comparison with a defined GOP/s metric, consistent power boundaries, and apples-to-apples baselines before acceptance. The architecture is solid enough that a revision should be able to fix the evaluation.","headline":"A genuinely useful TM training accelerator architecture, but the abstract's efficiency claims outrun what Table I actually supports.","tokens_in":20695,"tokens_out":1798,"would_cite":true,"duration_ms":19160,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims one FPGA accelerator, the Dynamic Tsetlin Machine, can train and retrain both Vanilla and Coalesced Tsetlin Machine models on chip with run-time reconfiguration, offering 2.54x GOP/s/W and 6x lower power than the closest…","keywords":["Tsetlin Machine","FPGA accelerator","edge training","runtime reconfiguration","Coalesced Tsetlin Machine","on-chip learning","LUT-based clause computation","keyword spotting"],"falsifier":"Measure actual DC power of the DTM-L on a ZCU104 board during MNIST training while counting a concrete operation, such as one clause-literal AND evaluation, and apply the same operation definition to the Conv TM design. If the measured GOP/s/W ratio is not 2.54x and system power is not 6x lower, the headline claim fails; likewise, if switching from CoTM to Vanilla TM or from 500 to 2000 clauses requires resynthesis, the runtime-reconfiguration claim fails.","tokens_in":19549,"feed_emoji":"⚙️","tokens_out":9797,"duration_ms":91913,"temperature":0.7,"pith_summary":"This paper claims that edge devices can train and retrain machine-learning models on chip using Tsetlin Machines instead of deep neural networks, and that one FPGA accelerator design—the Dynamic Tsetlin Machine (DTM)—can serve both Vanilla and Coalesced Tsetlin Machine algorithms. The central promise is flexibility: the same synthesized bitstream can switch between datasets, model sizes, and algorithm variants at run time, without resynthesis, which matters for privacy-preserving on-field recalibration of IoT sensors. The reported payoff is efficiency: 2.54x more operations per watt and 6x less power than the next-best comparable FPGA design. The argument is that Tsetlin Machine training is logic-based—clauses built from AND, OR, and NOT of Boolean literals updated by finite-state automata—so it maps to LUTs and integer arithmetic instead of floating-point backpropagation.","feed_headline":"Train Tsetlin Machines on-chip without resynthesis","feed_subtitle":"Swaps models and datasets at run time for private on-device retraining of edge sensors.","key_machinery":"The load-bearing object is the partial clause matrix and its partner, the partial weight and class-sum matrix. Instead of computing all clauses in one combinational block, the DTM fixes an x-by-y slice (for example, 32 literals by 27 clauses) and iterates over the model in slices, masking remainder cells. This fixed slice makes the design runtime-programmable: model size, feature count, class count, and TM variant become configuration words rather than hardware parameters. The efficiency claim rests on this reuse plus the feedback-skipping optimization, which skips reading TA RAM slices when no clause in the slice received feedback, giving roughly 40% training-time saving for CoTM as the model converges.","core_discovery":"The discovery is that Tsetlin Machine training and inference can be unified in a single FPGA architecture with a fixed compute array. The DTM decomposes full clause computation into partial slices of x literals by y clauses, applies masks to handle remainders, stores TA states and CoTM weights in BRAM, and computes clause outputs directly in LUT6 elements. Because the array dimensions, masks, and iteration counts are programmable at run time, the same hardware executes Vanilla TMs, where each class has polarity-divided clause teams, and Coalesced TMs, where a shared clause pool feeds class-specific signed integer weights. Training is done through class-level, clause-level, and TA-level feedback using integer comparisons with random numbers from a re-seeded LFSR cluster, and clause groups with no feedback are skipped in the TA update stage. The paper reports that on MNIST, FMNIST, KMNIST, and keyword spotting the accelerator trains to near the accuracy of prior Tsetlin Machine implementations, with the larger DTM-L configuration using 4.359 W system power and claiming 2.54x higher GOP/s/W than the closest comparable design.","pith_inferences":["I would read the 2.54x GOP/s/W and 6x power numbers as design-target estimates rather than a settled ranking, since the comparison benchmarks different platforms and mixes system-level and IP-only power; the deeper claim is the runtime-reconfigurable training capability itself, which a board-level measurement could verify.","The same partial-clause masking and iteration scheme should extend to Convolutional and Regression Tsetlin Machines, making DTM a template for the whole TM family; adding those modules, which the paper lists as future work, would let the accelerator handle CIFAR-class image inputs.","The feedback-skipping optimization suggests a general hardware principle for converging learners: as sparse feedback emerges during training, skipping idle memory reads can cut training time with no accuracy loss; testing this on other automata-based or sparse trainers would show whether it transfers."],"forward_implications":["An edge node can retrain a Tsetlin Machine model on device after deployment, responding to sensor drift or user personalization without sending data to the cloud.","A single FPGA bitstream covers multiple datasets and model configurations, so one product can serve different tasks without recompiling hardware.","CoTM users can cut training time by about 40% as clauses converge, because DTM skips feedback-free clause groups during TA updates.","Small LFSR lengths, such as 8 bits, are sufficient when seed refreshing is used, which reduces PRNG hardware cost while preserving training accuracy.","Training Tsetlin Machines requires very few DSPs, since multiply-accumulate work is replaced by LUT logic and small integer weight updates."],"supporting_citations":[{"why":"Defines the Vanilla TM: Tsetlin automata, clauses, Type I/II feedback, and class sums that DTM implements.","marker":"[8]"},{"why":"Defines Coalesced TM with a shared clause pool and learnable per-class integer weights, the basis of DTM's CoTM mode.","marker":"[9]"},{"why":"The closest prior FPGA Tsetlin Machine accelerator with on-device training; the comparison baseline for DTM's GOP/s/W and power claims.","marker":"[40]"},{"why":"A prior TM accelerator with hard-wired TA actions that cannot be recalibrated without resynthesis; motivates DTM's run-time reconfiguration.","marker":"[39]"},{"why":"Provides the master-slave PRNG cluster design that DTM adapts to LFSRs with re-seeding for training randomness.","marker":"[42]"},{"why":"Shows that feedback to clauses diminishes as TMs converge, the observation behind DTM's clause-group skipping optimization.","marker":"[38]"},{"why":"Supplies MNIST, the benchmark dataset used for accuracy, latency, and the Table I comparisons.","marker":"[14]"},{"why":"Google Speech Commands yields the KWS-6 keyword-spotting task that motivates the edge-recalibration use case.","marker":"[45]"}],"fun_headline_variants":["Train Tsetlin Machines on FPGA without resynthesis","Run-time reconfigurable Tsetlin training on FPGA","Edge AI: Reconfigure Tsetlin machines on the fly","Train Tsetlin on-chip without resynthesis"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The headline efficiency comparison assumes that \"Giga-operations per second\" measures the same thing in every accelerator and that Vivado-reported power matches real board power; if operation counts or power sources are not normalized, the 2.54x and 6x numbers may not hold.","fun_headline_variants_meta":{"raw":{"variants":["Train Tsetlin Machines on FPGA without resynthesis","Run-time reconfigurable Tsetlin training on FPGA","Edge AI: Reconfigure Tsetlin machines on the fly","Train Tsetlin on-chip without resynthesis"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001001,"raw_usage":{"total_tokens":4294,"prompt_tokens":1061,"completion_tokens":3233,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":677,"completion_tokens_details":{"reasoning_tokens":3168}},"tokens_in":677,"tokens_out":3233,"duration_ms":23624,"temperature":1.0,"reasoning_tokens":3168,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T05:43:23.998147+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure actual DC power of the DTM-L on a ZCU104 board during MNIST training while counting a concrete operation, such as one clause-literal AND evaluation, and apply the same operation definition to the Conv TM design. If the measured GOP/s/W ratio is not 2.54x and system power is not 6x lower, the headline claim fails; likewise, if switching from CoTM to Vanilla TM or from 500 to 2000 clauses requires resynthesis, the runtime-reconfiguration claim fails.","supporting_citations":[{"cited_title":"Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training,","cited_arxiv_id":null,"evidence_quote":"The closest prior FPGA Tsetlin Machine accelerator with on-device training; the comparison baseline for DTM's GOP/s/W and power claims."},{"cited_title":"MATADOR: Automated System-on-Chip Tsetlin Machine Design Gen- eration for Edge Applications,","cited_arxiv_id":null,"evidence_quote":"A prior TM accelerator with hard-wired TA actions that cannot be recalibrated without resynthesis; motivates DTM's run-time reconfiguration."},{"cited_title":"Parallel Symbiotic Random Number Generator for Training Tsetlin Machines on FPGA,","cited_arxiv_id":null,"evidence_quote":"Provides the master-slave PRNG cluster design that DTM adapts to LFSRs with re-seeding for training randomness."},{"cited_title":"REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines,","cited_arxiv_id":null,"evidence_quote":"Shows that feedback to clauses diminishes as TMs converge, the observation behind DTM's clause-group skipping optimization."},{"cited_title":"The mnist database of handwritten digit images for machine learning research,","cited_arxiv_id":null,"evidence_quote":"Supplies MNIST, the benchmark dataset used for accuracy, latency, and the Table I comparisons."}],"review_version":1}