{"id":"8146746c-6125-45cd-a052-bda95fa68e06","arxiv_id":"2504.20028","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Zinc sulfide films grown at 400°C on BEOL-compatible substrates via hybrid pulsed laser deposition show weak texture and low leakage current, but the claim of a highly intrinsic material is not yet fully supported.","lead":"This paper reports low-temperature growth of crystalline zinc sulfide films on seven chip-manufacturing-compatible surfaces and shows they are smooth and weakly textured. The work is a step toward a p-type semiconductor that could be stacked on top of finished chips for three-dimensional integrated circuits.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Flat C-V is not uniquely diagnostic of 'highly intrinsic' ZnS: full depletion, blocking contacts, interface states, or series resistance also yield flat C-V, so the central electrical claim is underdetermined without Hall or frequency-dependent C-V.","rationale":"Reader and stress-test converge on the same load-bearing point: the claim that ZnS is highly intrinsic is supported only by a flat C-V, which has multiple competing explanations. The paper does not provide Hall data, frequency-dependent C-V, or a transistor measurement, so the inference is underdetermined. I agree with the reader's conditional verdict. The proposed Hall-effect test would directly discriminate: if carrier concentration is significant, the flat C-V is not evidence of near-zero electrically active defects; if the film is highly resistive, the claim is strengthened but still needs corroborating frequency-dependent C-V. The structural characterization and growth results are not called into question by this concern, so the paper remains a useful demonstration of hPLD-grown textured ZnS on BEOL-compatible substrates. Therefore the existing CONDITIONAL verdict is appropriate and no change is needed.","tokens_in":10017,"tokens_out":5817,"duration_ms":60459,"concrete_test":"Perform a van der Pauw Hall-effect measurement on a 100 nm ZnS film grown by the same hPLD process on a non-conductive sapphire substrate, using thermally evaporated Cr/Au contacts, and extract carrier type, density, and mobility at room temperature. If the measured carrier density is above ~1e14 cm^-3, the flat C-V interpretation as 'highly intrinsic' is invalid; if the film is too resistive to measure, that would at least be consistent with the claim but still should be reported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim that hPLD-grown ZnS is 'highly intrinsic with very low unintentional, electrically active point defects' is supported solely by the flat C-V curve in Fig. 4(a) (Section III.D). A flat C-V in a MOSCAP with a 100 nm semiconductor layer on SiO2 is not uniquely diagnostic of an intrinsic semiconductor. The same flat response arises if the ZnS is fully depleted over the entire voltage range—which occurs even for moderately doped material once the depletion width exceeds the film thickness—if the top contact is blocking, if series resistance dominates, or if interface states pin the surface potential. The authors themselves report a ZnS dielectric constant of 5.6, below the bulk value of 8, and attribute this to 'interface trapping effects' (Section III.D), indicating that non-geometric contributions are already present in the measured capacitance. Without Hall-effect measurements, frequency-dependent C-V, or a transistor transfer characteristic, the flat C-V cannot distinguish a nearly defect-free semiconductor from a fully depleted, defective, or contact-limited film. This is the load-bearing weakness because the 'highly intrinsic' conclusion motivates the proposed p-type doping studies; if the flat C-V arises from one of the alternative mechanisms, the paper's core electrical claim is unsupported, even though the structural growth results may stand.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports growth of zinc sulfide (ZnS) thin films by hybrid pulsed laser deposition (hPLD) at 400°C on a variety of amorphous and polycrystalline BEOL-compatible substrates: SiNx, thermal SiO2, Y2O3, HfO2, sapphire, Pt, and TiN. Structural characterization by θ-2θ XRD shows 'weak out-of-plane texture' (00l reflections) on all surfaces; GIWAXS shows random in-plane orientation on most surfaces but some ordering on Y2O3; XRR and AFM indicate smooth films. Electrical characterization consists of J-V measurements on a ZnS/Pt stack and C-V measurements on ZnS/SiO2 MOSCAPs. The flat C-V curve is interpreted as evidence that ZnS is 'highly intrinsic with very low unintentional, electrically active point defects,' motivating future p-type doping studies.","tokens_in":10221,"tokens_out":2979,"duration_ms":32409,"significance":"If the electrical claim were well supported, the work would be a useful step toward a p-type channel material for BEOL-compatible 3D integration, because it demonstrates 400°C growth of textured, smooth ZnS on multiple substrates and reports a bilayer-capacitor response. The structural results appear solid: the XRD, GIWAXS, XRR, and AFM data are internally consistent, and the hPLD method has been previously published, so the growth portion is reproducible and credible. However, the central electrical conclusion—that flat C-V implies a nearly defect-free, highly intrinsic semiconductor—is not uniquely supported by the presented data, and this conclusion is what motivates the proposed p-type doping program. The paper also provides honest statements of limitations (e.g., 'cautious inference' about interface trapping, need for future FET measurements), which is commendable.","major_comments":[{"comment":"The flat C-V curve is not uniquely diagnostic of a 'highly intrinsic' ZnS film. A flat capacitance that is independent of bias also results if the semiconductor is fully depleted over the entire voltage range (which can occur even for moderately doped films when the maximum depletion width exceeds the film thickness), if the top contact is blocking, if interface states pin the surface potential, or if series resistance dominates the measurement. The authors themselves report ε_ZnS = 5.6, below the bulk value of 8, and attribute this to 'interface trapping effects' (Section III.D), indicating that non-idealities already affect the measured capacitance. Without Hall-effect measurements, frequency-dependent C-V, or a transistor transfer characteristic, the data cannot distinguish a nearly defect-free semiconductor from a fully depleted or contact-limited film. Because the 'highly intrinsic' conclusion is the paper's central electrical claim and the stated motivation for future p-type doping studies, this underdetermination is load-bearing and must be addressed.","section":"III.D, Fig. 4(a)"},{"comment":"The electrical data are presented without error bars, statistics over devices, or measurement details such as the number of devices tested and the spread in extracted dielectric constants. The J-V data are shown for a single ZnS/Pt stack (Fig. S8) and for the MOSCAP (Fig. 4(b)), but no breakdown field, comparison to a control sample, or temperature dependence is given to support the claim that the leakage current is 'low.' Reporting device-to-device variability and at least one independent electrical probe (e.g., Hall effect or capacitance-frequency sweep) would substantially strengthen the interpretation.","section":"III.D, Fig. 4 and Fig. S8"}],"minor_comments":[{"comment":"The caption of Fig. 4 labels part (b) as an 'in-plane I-V measurement,' but the text in Section III.D describes J-V measurements through the film thickness (perpendicular to the plane). The label appears to be a misnomer and should be corrected to 'cross-plane J-V' or 'out-of-plane J-V.'","section":"Fig. 4 caption"},{"comment":"The phrase 'anisotropic metal-insulator-metal structure' is unclear; the structure (ZnS on Pt on heavily doped Si with Cr/Au top contacts) is asymmetric rather than anisotropic. Please clarify the intended meaning.","section":"III.D"},{"comment":"The caption of Fig. 2(a) lists Al2O3 under 'polycrystalline surfaces,' but the text (Section III.A and Fig. 1) describes Al2O3 deposited by ALD as amorphous. This is inconsistent and should be corrected.","section":"Fig. 2 caption"},{"comment":"The abstract states 'out-of-plane texturing across all surfaces,' while the body repeatedly describes the texture as 'weak' (Sections III.A and IV). To avoid overstating the result, use a consistent qualifier such as 'weak out-of-plane texture' in the abstract as well.","section":"III.A, Fig. 1"}],"recommendation":"major_revision","confidential_remarks":"The structural growth results are publishable in principle, but the electrical interpretation in Section III.D is the core claim tied to the paper's motivation. The flat C-V evidence alone is insufficient to establish that ZnS is 'highly intrinsic' or has 'minimal electrically active defects.' The authors should be asked to provide additional measurements (e.g., Hall effect, frequency-dependent C-V, or a simple FET) or to substantially soften the electrical claims and reframe the paper as a growth/texture study with preliminary electrical data. The inconsistencies in figure captions and the mislabeled I-V can be fixed during revision. I see no circularity or fabrication concerns; the concerns are about interpretation and completeness of evidence."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: the growth work is genuinely useful—hPLD gives textured, smooth ZnS on seven BEOL-compatible surfaces at 400°C, and that's new. The XRD, GIWAXS, XRR, and AFM data hang together, and the contrast between random in-plane orientation on most surfaces and the in-plane ordering on Y2O3 is a real observation. If you work on chalcogenide films or BEOL channel materials, this is a data point you want to know about.\n\nThe soft spot is exactly where the reader and the stress-test put it: the electrical section. The conclusion that ZnS is 'highly intrinsic with very low electrically active point defects' rests on a flat C-V curve. That is not a diagnostic of an intrinsic semiconductor. Full depletion, a blocking top contact, series resistance, or interface state pinning all give the same flat response. The authors themselves note interface trapping effects when extracting the dielectric constants (ZnS 5.6 vs bulk 8), which suggests non-geometric contributions are already present. Without Hall effect, frequency-dependent C-V, or a FET transfer curve, the claim is underdetermined. I'd want that conclusion softened to 'consistent with a fully depleted or highly resistive film' rather than 'highly intrinsic.' It is a meaningful distinction because the proposed p-type doping study is motivated by the supposed low defect density.\n\nMinor but worth fixing: Fig 4's caption says cross-plane C-V and in-plane I-V, while the text describes both as cross-plane (the J-V is through the film). There are also thickness mismatches between the growth section and the Fig 2 captions (e.g., ZnS on Pt: 200 nm in text vs 120 nm in caption; SiNx: 58 vs 90 nm). These are small, but they add friction for a reader trying to reproduce the measurements.\n\nOn balance, the structural claims are solid and new; the electrical claims need either more evidence or a much more cautious wording. The paper deserves peer review, because the growth results are a contribution and the electrical overreach is fixable in revision.\n\nRecommendation: send it to review, but if you're the editor, find a referee who will press on the C-V interpretation.","headline":"Solid growth study undermined by an electrical interpretation that reads too much into a flat C-V curve; the structural data are worth a careful referee.","tokens_in":10894,"tokens_out":2184,"would_cite":true,"duration_ms":21494,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper reports that hybrid pulsed laser deposition grows crystalline, out-of-plane textured zinc sulfide films on amorphous and polycrystalline back-end-of-line-compatible substrates at 400 °C, and electrical measurements indicate the…","keywords":["zinc sulfide","hybrid pulsed laser deposition","BEOL-compatible substrates","thin-film texture","MOSCAP characterization","p-type semiconductor","back-end-of-line integration","chalcogenide thin films"],"falsifier":"Measure the same MOSCAPs' capacitance from 1 kHz to 1 MHz and under illumination, or fabricate a field-effect transistor and attempt to gate-modulate the channel; if the flat C-V shows strong frequency dispersion, or if a transistor shows no channel modulation, then the flat curve is a contact or depletion artifact rather than proof of an intrinsic, low-defect film.","tokens_in":9770,"feed_emoji":"🔬","tokens_out":6714,"duration_ms":63767,"temperature":0.7,"pith_summary":"This paper is trying to establish that zinc sulfide (ZnS), a wide-band-gap semiconductor that can be made p-type by copper doping, can be grown as crystalline, textured thin films below 450 °C on the kinds of surfaces found in the back-end of a chip: silicon nitride, silicon dioxide, hafnium oxide, yttrium oxide, platinum, and titanium nitride. The growth method is a variant of pulsed laser deposition that supplies sulfur through an organosulfur precursor, which helps control the vapor-pressure mismatch that usually ruins sulfide films. X-ray diffraction shows out-of-plane texturing on every surface tested, and the films are smooth even on rough amorphous templates. Electrical tests show low leakage current and a flat capacitance-voltage curve that the authors interpret as bilayer-capacitor behavior, meaning the undoped ZnS is essentially insulating with few electrically active defects. If this holds, ZnS becomes a credible starting point for p-type doping studies aimed at back-end-of-line transistors for 3D integration.","feed_headline":"Textured zinc sulfide grows on chip back-end surfaces at 400 °C","feed_subtitle":"A new deposition route yields smooth, low-leakage ZnS films that could become the missing p-type channel for 3D chips.","key_machinery":"The load-bearing mechanism is hybrid pulsed laser deposition (hPLD): a 248 nm KrF laser ablates a dense ZnS target while tert-butyl disulfide vapor is metered into the chamber without a carrier gas, providing a sulfur-rich environment that compensates for sulfur loss at elevated temperature. This is what enables crystalline, textured growth at 400 °C on surfaces with no epitaxial relation to ZnS. Structural characterization relies on powder XRD for out-of-plane texture, GIWAXS for in-plane ordering, and X-ray reflectivity and atomic force microscopy for smoothness; electrical characterization uses J-V and MOSCAP measurements, with the flat capacitance treated as evidence of a nearly intrinsic, defect-poor film.","core_discovery":"The central discovery is that the hybrid PLD process produces wurtzite ZnS with a consistent c-axis (00l) out-of-plane texture on all substrates, including amorphous oxides and nitrides, with no requirement for lattice matching; in-plane grain orientation remains random except on yttrium oxide, where the template's own texture imposes partial ordering. On the electrical side, metal-insulator-metal and MOSCAP structures show leakage near $10^{-5}\\ \\mathrm{A\\,cm^{-2}}$ at $0.40\\ \\mathrm{MV\\,cm^{-1}}$ and a nearly flat C-V curve, which the paper reads as ZnS and SiO2 acting as two capacitors in series, with ZnS behaving as a highly intrinsic semiconductor. The implication is that unintentional doping is low, so any future p-type behavior will come from deliberate dopants rather than from background defects.","pith_inferences":["If the intrinsic interpretation holds, a systematic copper-doping series in the same chamber is the immediate next experiment; a monotonic rise in hole concentration with copper fraction would confirm both the baseline and the dopability.","The absence of Hall and frequency-dependent data leaves room for an alternative reading of the flat C-V, so a dedicated Hall or Mott-Schottky study would settle whether the low-defect claim is quantitative.","Comparing ZnS on textured Y2O3 with ZnS on amorphous SiNx could separate texture effects from grain-boundary conduction, since both are smooth but only the former has in-plane ordering.","The same hPLD sulfur-precursor strategy may extend to other vapor-pressure-mismatched sulfides, making textured low-temperature growth a general route rather than a ZnS-specific result."],"forward_implications":["If hPLD grows textured, smooth ZnS on every surface tested at 400 °C, the recipe can be transferred directly to a back-end stack without changing the dielectrics or metals already present.","If undoped ZnS is as intrinsic as the flat C-V suggests, then copper or nitrogen doping should yield p-type conductivity without being swamped by background donors.","Leakage near $10^{-5}\\ \\mathrm{A\\,cm^{-2}}$ at $0.40\\ \\mathrm{MV\\,cm^{-1}}$ indicates the films can hold the fields needed for a transistor channel without excessive off-state current.","Because in-plane order is only imposed by the yttrium oxide template, films on the other substrates should show grain-boundary-dominated transport, and Y2O3 offers a control surface to test that."],"supporting_citations":[{"why":"Shows room-temperature p-type conductivity in Cu-alloyed ZnS, which motivates ZnS as a BEOL p-type channel candidate.","marker":"[4]"},{"why":"Documents the vapor-pressure mismatch and slow diffusion that make sulfide thin-film growth difficult, motivating the hybrid-PLD sulfur source.","marker":"[16]"},{"why":"Raises the same chalcogenide growth challenges for a related sulfide, justifying the need for a new deposition approach.","marker":"[17]"},{"why":"Introduces the hybrid PLD method with an organosulfur precursor that the paper uses to grow the ZnS films.","marker":"[18]"},{"why":"Earlier 248-nm PLD growth of ZnS films provides a comparison point for texture and growth temperature.","marker":"[32]"},{"why":"Explains the silicon (002) multiple-diffraction peak that appears in the XRD patterns so substrate reflections can be assigned correctly.","marker":"[35]"},{"why":"Provides the steady-state MOSCAP measurement conditions used to obtain the flat C-V curves.","marker":"[36]"},{"why":"Gives the dielectric properties of ZnS films used to interpret the lower-than-bulk dielectric constant.","marker":"[37]"},{"why":"Supplies reference dielectric-constant values and interface-trap reasoning for the MOSCAP analysis.","marker":"[38]"}],"fun_headline_variants":["Textured ZnS grows on amorphous chip surfaces at 400°C","Zinc sulfide: low-leakage p-type candidate for 3D chips","No lattice match needed: ZnS textures on all BEOL surfaces","Crystalline ZnS films on silicon nitride and beyond at low temp","ZnS: the missing p-type channel for BEOL-compatible logic"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The paper's suggestion that ZnS is highly intrinsic rests on interpreting a flat capacitance-voltage curve as the signature of a nearly defect-free insulating layer; if that flatness instead comes from full depletion, blocking contacts, or interface and series-resistance effects, the low-defect conclusion does not follow.","fun_headline_variants_meta":{"raw":{"variants":["Textured ZnS grows on amorphous chip surfaces at 400°C","Zinc sulfide: low-leakage p-type candidate for 3D chips","No lattice match needed: ZnS textures on all BEOL surfaces","Crystalline ZnS films on silicon nitride and beyond at low temp","ZnS: the missing p-type channel for BEOL-compatible logic"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000528,"raw_usage":{"total_tokens":2606,"prompt_tokens":1063,"completion_tokens":1543,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":679,"completion_tokens_details":{"reasoning_tokens":1447}},"tokens_in":679,"tokens_out":1543,"duration_ms":11539,"temperature":1.0,"reasoning_tokens":1447,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T05:36:54.819598+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the same MOSCAPs' capacitance from 1 kHz to 1 MHz and under illumination, or fabricate a field-effect transistor and attempt to gate-modulate the channel; if the flat C-V shows strong frequency dispersion, or if a transistor shows no channel modulation, then the flat curve is a contact or depletion artifact rather than proof of an intrinsic, low-defect film.","supporting_citations":[],"review_version":1}