{"id":"5effe97d-d4ea-4219-80a1-220be6110f6d","arxiv_id":"2504.20680","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A hybrid serial-parallel FPGA architecture for fully connected oscillatory neural networks scales arithmetic logic near-linearly, enabling 506 oscillators on a Zynq-7020, but weight memory and latency still scale quadratically.","lead":"A digital oscillatory neural network design replaces one adder per connection with a time-shared accumulator, cutting the growth of adder logic from quadratic to near-linear on an FPGA. The trade-off is a sharp drop in oscillation speed and a still-quadratic weight memory, so the design fits larger networks only at lower throughput.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Near-linear scaling is shown only for LUTs/FFs; BRAM and DSP are saturated at 506 oscillators and weight storage remains O(N^2), so the total-hardware scaling claim is overstated.","rationale":"The paper is a credible engineering demonstration: serializing the multiply-accumulate operation reduces LUT/FF scaling from roughly quadratic to near-linear, enabling a fully connected digital ONN with 506 oscillators on a Zynq-7020, which is larger than prior digital all-to-all implementations. The reader's verdict of CONDITIONAL correctly balances this achievement against the unresolved scope of the scaling claim. My review agrees with the reader's weakest assumption: the same constraint of serial computation within one phase-update period applies at every N, and the on-chip memory for the O(N^2) weights is already fully consumed at the maximum demonstrated size. The most load-bearing issue is that the central claim 'overcoming quadratic hardware scaling' is only demonstrated for the logic resources (LUTs and FFs), while the total hardware budget still scales quadratically because weight storage cannot be reduced (stated explicitly in Section 2.1). This does not invalidate the engineering result, but it means the title and abstract overstate the generality of the scaling improvement. My proposed test—fitting BRAM utilization or aggregate area across synthesis runs—would settle whether the total-resource scaling is actually near-linear. Since this is exactly the concern the reader already identified and the verdict is already conditional, I do not recommend changing the verdict.","tokens_in":14684,"tokens_out":8229,"duration_ms":92279,"concrete_test":"Re-run the resource scaling analysis for the hybrid architecture at N = 64, 128, 256, and 506 using the paper's own aggregate area measure (mean of LUT, FF, DSP, and BRAM percentage utilizations) and separately fit the scaling exponent for BRAM slices alone. If the BRAM exponent is approximately 2, or if the aggregate area exponent is well above 1.2 and the design fails place-and-route at N = 512 due to BRAM/DSP exhaustion, then the 'near-linear hardware scaling' claim does not hold for total hardware. Alternatively, attempt to synthesize N = 1024 on the same Zynq-7020; failure due to BRAM/DSP before LUT/FF saturation would confirm that the quadratic resources, not the near-linear logic, set the practical limit.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim of 'overcoming quadratic hardware scaling' is supported only for the arithmetic logic (LUTs and FFs), not for the full hardware budget. Section 4.2 explicitly measures scaling only in terms of lookup tables and flip-flops, while Section 2.1 concedes that the number of memory cells cannot be reduced and remains O(N^2). At the maximum demonstrated size of 506 oscillators, Table 4 shows BRAM and DSP slices at 100% utilization, while LUTs are at 78% and FFs at 42%. Thus the binding constraints on scaling are the quadratic weight memory and the DSP count, not the LUT/FF logic whose exponent is fit as 1.2. The serialized design also requires a fast clock at least N times the phase clock; with a 50 MHz fast clock at N=506 the oscillator frequency is already only 6.1 kHz, and the reported frequency scaling of N^-1.35 means larger N would require either unattainable clock rates or impractically slow oscillations. Consequently, the paper demonstrates a valuable area-time trade-off for the arithmetic logic, but the headline claim that the architecture overcomes quadratic hardware scaling is not established for total resources: the quadratic weight storage remains and is the actual limiting factor.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a hybrid architecture for digital oscillatory neural networks (ONNs) in which the coupling arithmetic is partially serialized: rather than using N parallel adders per oscillator, a single multiply-accumulate unit per oscillator is time-multiplexed across all N weights, operating on a faster clock domain. The authors compare this against a previously reported recurrent digital ONN on a Zynq-7020 FPGA, reporting LUT/FF scaling exponents of about 1.2 for the hybrid architecture versus about 2.0–2.4 for the recurrent baseline, and a 10.5× increase in maximum oscillator count (48 to 506) at 5-bit weights and 4-bit phases. They also report pattern-retrieval benchmarks showing similar retrieval accuracy and settling time between the two architectures, and high accuracy on larger patterns up to 22×22. The central claim is that the hybrid architecture overcomes quadratic hardware scaling.","tokens_in":14967,"tokens_out":3136,"duration_ms":31401,"significance":"If properly qualified, this is a useful engineering contribution: it demonstrates the largest fully connected digital ONN implemented on an FPGA to date, and it shows that the dominant logic cost of the coupling network can be reduced from O(N^2) adders to O(N) adders by time-multiplexing, with measured resource usage fitting the claimed near-linear trend (R² above 0.99 for LUTs and FFs). The use of an external learning rule (Diederich-Opper) and standard corruption benchmarks strengthens the functional validation. The strength of the paper is the concrete FPGA synthesis data across network sizes, not just a conceptual proposal. However, the significance is limited by the fact that the near-linear scaling applies only to LUT/FF logic, while on-chip weight storage and DSP usage remain quadratic and are the actual binding constraints at the maximum demonstrated size.","major_comments":[{"comment":"The headline claim of 'overcoming quadratic hardware scaling' is contradicted by the paper's own account: §2.1 states that the number of memory cells for weights cannot be reduced and remains O(N²), and Table 4 shows that at 506 oscillators the hybrid design uses 100% of BRAM and 100% of DSP slices, while LUTs are at 78% and FFs at 42%. Thus the binding resource constraints at the maximum demonstrated size are the quadratic weight memory and the DSP count, not the LUT/FF logic whose exponent is fitted as 1.2. The paper should qualify the claim as near-linear scaling of the coupling arithmetic logic (LUTs/FFs), and should explicitly state that total resource scaling, including on-chip storage, remains quadratic.","section":"§2.1 and Table 4"},{"comment":"The scaling analysis is incomplete because it excludes BRAM and DSP utilization. The methodology states that only LUTs and FFs were recorded because 'these are the two components determining the amount of logic hardware', but BRAM and DSP are also hardware resources and they saturate at the maximum network size. To support the claim of near-linear hardware scaling, the authors should report BRAM and DSP usage per network size, and either fit scaling exponents for those resources or justify their exclusion with a clear argument that they are not part of the architecture's scaling bottleneck. Without this, the paper's conclusion that 'hardware resource usage scales nearly linear' is only demonstrated for a subset of the resources.","section":"§4.2"},{"comment":"The frequency trade-off is not incorporated into the scaling claim. Figure 11 and the text report that the hybrid architecture's oscillation frequency scales as N^(-1.35), which is slightly faster than inversely linear. Because the serialized arithmetic requires at least N fast-clock cycles per phase update, the phase clock must be slowed down by a factor of N; at N=506 with a 50 MHz fast clock the oscillation frequency is already only 6.1 kHz. For larger N, the required fast clock becomes increasingly impractical or the oscillation frequency falls to levels that undermine the utility of the architecture. This is acknowledged in the discussion but is not reflected in the title or the 'near-linear hardware scaling' framing; the paper should present the result as an area-time trade-off rather than as a wholesale overcoming of quadratic scaling.","section":"§5.2 and Figure 11"}],"minor_comments":[{"comment":"The flip-flop data point for the recurrent architecture at 16 oscillators is acknowledged as a possible outlier, but the fit is still reported without a sensitivity analysis. A short robustness note (e.g., refitting without that point) would make the scaling exponent more credible.","section":"§5.2"},{"comment":"The paper states in one paragraph that 'the oscillator dynamics of the hybrid architecture are the same as the recurrent architecture', while the immediately preceding discussion of the 3×3/50% anomaly hypothesizes that 'the additional synchronization required in the hybrid architecture slightly changes the system dynamics'. These statements are in tension and should be reconciled, for example by saying the dynamics are approximately equivalent for practical purposes with a possible small deviation at small sizes and high noise.","section":"§5.3"},{"comment":"The footnotes containing '⁄pilcrow' and '§' are rendered cryptically (e.g., '1008⁄pilcrow'); the table should use standard footnote symbols or superscript numbers that are clearly explained in the caption.","section":"Table 2"},{"comment":"The benchmark section explicitly states that 'exhaustive benchmarking is not required' and that only functionality is verified. This is fine, but the conclusion that the architectures have 'similar dynamics' would be strengthened by reporting the standard deviation or confidence intervals of the retrieval accuracy across the 1000 runs, rather than only the mean.","section":"§4.3"},{"comment":"The 'maximum frequency (100%)≈ 325KHz' annotation in Figure 12 refers only to the hybrid architecture, but the figure caption does not make this explicit; the text should clarify that the frequency axis is relative to the hybrid architecture's own maximum.","section":"§5.2 and Figure 12"}],"recommendation":"major_revision","confidential_remarks":"The paper's strongest result—the near-linear scaling of LUT/FF logic in the hybrid architecture—is well supported by the synthesis data. The main issue is that the title and abstract oversell this as 'overcoming quadratic hardware scaling' when the paper's own Table 4 shows that BRAM and DSP are at 100% utilization at the maximum size and §2.1 concedes weight memory remains O(N²). I recommend the authors re-frame the contribution as a time-multiplexed coupling-arithmetic architecture that reduces the arithmetic-logic scaling, while clearly stating that total resource scaling (including weight storage) remains quadratic. With that qualification, the paper is publishable. If the authors are willing to add BRAM/DSP scaling data and soften the headline, I would be happy to see it in revised form."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Dear [Name],\n\nThis is a solid engineering paper with an overstated headline. The actual result: the authors serialize the weighted-sum computation in a fully connected digital ONN, sharing one multiply-accumulate per oscillator, and fit the LUT/FF growth against network size. On a Zynq-7020 they get 506 oscillators, 10.5x more than the recurrent baseline, with LUT scaling exponent ~1.2 and FF ~1.1, both with R^2 > 0.99. The pattern retrieval benchmarks using the Diederich-Opper rule show broadly similar accuracy and settling times to the recurrent architecture at small sizes. That is a genuine, reproducible capability jump inside this subfield and the first scaling characterization of such a hybrid design. The synthesis data and the FPGA board are real; you could rerun the fits from the numbers in the figures.\n\nWhat gives me pause is the title and abstract. The paper says it \"overcomes quadratic hardware scaling,\" but the analysis in Section 4.2 only counts LUTs and FFs. The weight storage is still O(N^2) in BRAM, and at the demonstrated 506 oscillators the BRAM is at 100% and the DSP slices (used for the MAC) are at 100%. So the architecture trades quadratic logic for quadratic memory plus a linear number of DSP blocks, and the actual limiting resources on the Zynq are the BRAM and DSP, not the LUT/FF logic. The paper's own Section 2.1 concedes memory cells cannot be reduced. So the claim should be scoped to arithmetic logic, not total hardware.\n\nThe other soft spot is the timing cost: serialization requires a fast clock at least N times the phase clock. At 506 oscillators they already run a 50 MHz fast clock and get only 6.1 kHz oscillation; the fitted N^-1.35 scaling means bigger networks either need an unreasonably fast clock or become impractically slow. The benchmark comparison also lacks statistics; the unexplained accuracy difference at 3x3/50% corruption suggests the dynamics are not bit-identical, which is worth understanding rather than hand-waving.\n\nNone of these are fatal if presented as a design trade-off. The core engineering is sound, the measurement method is transparent, and the 506-oscillator demo is a concrete milestone. I'd send it to peer review, but require the authors to correct the scaling claim in the title/abstract, include the BRAM/DSP data in the scaling analysis, and either provide error bars or discuss run-to-run variance more carefully.\n\nBest,","headline":"A real 10.5x scaling demo for ONN arithmetic logic, but the 'quadratic hardware scaling' claim overreaches because weight memory and DSP are still the limiting resources.","tokens_in":15486,"tokens_out":3589,"would_cite":true,"duration_ms":32951,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Serialized couplings make digital oscillator networks scale nearly linearly","keywords":["oscillatory neural networks","digital implementation","FPGA prototyping","hardware scaling","serialization","pattern retrieval","Ising machine","multiply-accumulate"],"falsifier":"Synthesize the hybrid architecture at 1024 oscillators on an FPGA with enough BRAM and DSP slices and measure the LUT/FF counts and the achievable fast-clock frequency. If the resource counts leave the fitted near-1.2 exponent, or if the fast clock cannot run at least $N$ times the phase clock while meeting timing, the near-linear scaling claim fails; similarly, the claim weakens if pattern retrieval accuracy degrades materially when the design is actually run at that size.","tokens_in":14426,"feed_emoji":"🧠","tokens_out":4446,"duration_ms":41872,"temperature":0.7,"pith_summary":"This paper argues that the quadratic growth in coupling hardware that limits fully connected digital oscillatory neural networks can be broken by serializing the weighted-sum computation. It introduces a hybrid architecture that keeps one oscillator per node but replaces the per-connection adder trees with a single time-multiplexed multiply-accumulate unit per oscillator. On a Zynq-7020 FPGA, the same 5-bit weights and 4-bit phases that supported 48 oscillators in the recurrent baseline support 506 oscillators, a 10.5x increase, with LUT and FF usage scaling with exponents around 1.22 and 1.11 instead of roughly 2.1 and 2.4. Pattern retrieval accuracy and settling time match the baseline, so the serialization does not appear to change the network's dynamics.","feed_headline":"Serialized couplings fit 10.5x more oscillators on one FPGA","feed_subtitle":"A hybrid architecture cuts hardware growth from quadratic to near-linear, reaching 506 fully connected oscillators.","key_machinery":"The load-bearing mechanism is time-multiplexed serial accumulation of the weighted sum. For each oscillator, instead of a combinatorial tree of $N-1$ adders, one adder with feedback accumulates the products of the $N$ stored weights with the time-multiplexed oscillator amplitudes over $N$ fast-clock cycles; a counter selects the memory address and the multiplexer, and the final sum is latched in time for the next phase update on the slow clock. The multiply-accumulate maps onto DSP slices and the weight matrix onto block RAM, trading arithmetic logic for memory and a faster clock domain. Its cost is the requirement that the fast clock run at least $N$ times the phase clock, which is the trade that limits the largest demonstrable network.","core_discovery":"The central discovery is that a fully connected digital ONN does not need $N^2$ arithmetic circuits. By storing the $N \\times N$ coupling matrix in block RAM and feeding oscillator amplitudes through a multiplexer into one accumulator per oscillator, the hardware cost of the couplings drops from quadratic to near-linear: measured LUT scaling order 1.2231, FF scaling order 1.1092, versus 2.0770 and 2.3859 for the recurrent architecture. This raises the maximum fully connected network on the test FPGA from 48 to 506 oscillators at the same precision, at the price of an oscillation frequency that falls with order about -1.35 in network size. The paper verifies that the serialized arithmetic reproduces the dynamics of the recurrent design on pattern retrieval tasks at multiple corruption levels.","pith_inferences":["The same accumulator-per-node serialization could be applied to other fully connected recurrent FPGA designs, and the measured exponents suggest that the practical ceiling will move from logic cells to on-chip memory and DSP capacity.","The 100% BRAM and 100% DSP utilization at 506 oscillators implies that the architecture could likely exceed 506 nodes on a larger FPGA or with external memory, but the paper's near-linear scaling claim is only demonstrated up to that size.","A natural testable extension is to run combinatorial optimization benchmarks, such as max-cut or MaxSAT, at the newly reachable all-to-all scale; the paper leaves this to future work.","The frequency penalty could be reduced by processing several oscillators' weighted sums concurrently when spare DSP slices exist, giving a tunable parallelism-versus-serialization tradeoff that the paper does not explore."],"forward_implications":["At 5-bit weights and 4-bit phases, the hybrid architecture runs 506 fully connected oscillators on a Zynq-7020, 10.5x the recurrent baseline's 48, and is the largest fully connected digital ONN reported in the paper.","Hardware usage for the coupling logic scales approximately linearly: LUTs at exponent about 1.22 and flip-flops at about 1.11, versus about 2.08 and 2.39 for the recurrent architecture.","The hybrid architecture matches the recurrent architecture in pattern retrieval accuracy and settling time on small patterns, and retains near-100% accuracy on 10x10 and 22x22 patterns at 10% and 25% corruption.","Scaling comes at the cost of oscillation frequency, which drops with exponent about -1.35 in network size, so applications that need fast oscillation must use fewer oscillators.","Because the network remains all-to-all, problems that need dense embedding, such as graph max-cut, do not require sparse-topology mapping tricks."],"supporting_citations":[{"why":"The recurrent digital ONN architecture this work modifies and benchmarks against; it supplies the oscillator design, the 5-bit/4-bit precision choice, and the baseline scaling data.","marker":"[2–4, 18]"},{"why":"The Diederich-Opper I learning rule used to generate the quantized coupling weight matrices for the pattern retrieval tests.","marker":"[12]"},{"why":"The phase-locked loop coupled-oscillator dynamics equation that the digital square-wave phase update discretizes.","marker":"[14]"},{"why":"The streamed all-to-all SDE accelerator whose connection count anchors the state-of-the-art comparison table that the 256,036 connections are measured against.","marker":"[5]"}],"fun_headline_variants":["Digital ONN hits near-linear scaling: 506 oscillators on one FPGA","Hybrid ONN architecture breaks quadratic coupling barrier","From quadratic to linear: 10.5x more oscillators on FPGA","506 fully connected oscillators via serialized coupling","Near-linear scaling unlocks larger digital ONNs"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The serialized design must finish all $N$ weighted additions inside one phase-update period, which requires a fast clock at least $N$ times the phase clock and all $N^2$ weights resident in on-chip memory; the paper demonstrates this only up to 506 oscillators, where BRAM and DSP slices are already at 100% utilization.","fun_headline_variants_meta":{"raw":{"variants":["Digital ONN hits near-linear scaling: 506 oscillators on one FPGA","Hybrid ONN architecture breaks quadratic coupling barrier","From quadratic to linear: 10.5x more oscillators on FPGA","506 fully connected oscillators via serialized coupling","Near-linear scaling unlocks larger digital ONNs"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000565,"raw_usage":{"total_tokens":2688,"prompt_tokens":962,"completion_tokens":1726,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":578,"completion_tokens_details":{"reasoning_tokens":1644}},"tokens_in":578,"tokens_out":1726,"duration_ms":10663,"temperature":1.0,"reasoning_tokens":1644,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T05:22:47.934385+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Synthesize the hybrid architecture at 1024 oscillators on an FPGA with enough BRAM and DSP slices and measure the LUT/FF counts and the achievable fast-clock frequency. If the resource counts leave the fitted near-1.2 exponent, or if the fast clock cannot run at least $N$ times the phase clock while meeting timing, the near-linear scaling claim fails; similarly, the claim weakens if pattern retrieval accuracy degrades materially when the design is actually run at that size.","supporting_citations":[],"review_version":1}