{"id":"80fe2020-20b6-48f5-b4b8-e8775717a570","arxiv_id":"2505.00066","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A hybrid surface code with erasure qubits placed in central rows and columns achieves better logical error rates per transmon than all-standard or all-erasure designs for certain near-term transmon budgets.","lead":"This paper studies quantum error correcting surface codes where some, but not all, qubits are 'erasure qubits' that announce when they fail. It shows that a carefully chosen hybrid layout can beat both all-normal and all-erasure designs for a fixed number of superconducting components at near-term sizes.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Hybrid transmon-budget advantage is conditioned on perfect erasure checks and fully heralded erasure errors; realistic check errors and unheralded Pauli errors are acknowledged but unmodeled and could shrink or erase the advantage.","rationale":"I read the paper as a well-structured architecture study whose central quantitative claim is about the transmon-budget trade-off in a specific idealized noise model. The abstract and Section V-B assert a concrete advantage for hybrid-erasure layouts at fixed transmon budgets. For that advantage to hold in practice, erasure qubits must actually provide clean, reliable 'no-erasure' information. The paper's own Section IV.A and Section IV.D state that erasure checks are assumed perfect and that all erasure-qubit errors are heralded, and Section VII lists imperfect erasure checks as future work. The reader's weakest assumption identifies exactly this idealization, and my reading agrees. Within the stated model, the argument is coherent: the decoder's edge-deletion and reweighting scheme is a legitimate way to use heralded information, the effective-distance formula in Equation 2 is consistent with the repetition-code toy model in Section III-B, and the circuit-level simulations validate the placement heuristic for small distances. I did not find an internal inconsistency in the derivation, and I do not think the central claim is false within the stated assumptions. The concern is external validity: realistic check errors and unheralded Pauli errors could materially change the numerical comparisons in Figures 9 and 10. This is addressable by simulation, so a conditional verdict is appropriate. I see no reason to escalate to a stronger rejection, nor to fully accept without qualification. The reader's conditional verdict, with the request for check-error modeling and error bars, remains the right call.","tokens_in":19206,"tokens_out":8029,"duration_ms":90534,"concrete_test":"Rerun the circuit-level simulations underlying Figure 9 for d = 3, 5, 7 and p = 0.003, 0.01 with a noisy erasure-check model: set both false-positive and false-negative probabilities to q = 0.01 and q = 0.1, values consistent with the range of dual-rail check fidelities reported in refs. [22] and [46], and add unheralded Pauli errors on erasure qubits at rate r = 0.1p. Replace the decoder's edge deletion for unflagged qubits with a weight-update that retains a small but nonzero error probability. If the transmon-budget regions where hybrid beats all-erasure and all-standard layouts shrink by more than the scatter in the original data, then the central claim requires a qualifier stating that the advantage depends on near-perfect erasure checks and fully heralded errors.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim, stated in the abstract and quantified in Section V-B (Figures 9 and 10), is that hybrid-erasure layouts achieve lower logical error rates than homogeneous all-standard or all-erasure layouts for a fixed transmon budget. This claim rests on two noise-model idealizations introduced in Section IV.A: erasure checks are perfect, with no false positives or false negatives, and every error on an erasure qubit is a heralded erasure event followed by replacement with a maximally mixed state. The decoder in Section IV.B exploits this by deleting decoding-graph edges for unflagged erasure qubits and reweighting edges for flagged ones, effectively treating an absent erasure flag as a guarantee that no error occurred on that qubit. If checks are imperfect, or if unheralded Pauli errors exist on erasure qubits, then an unflagged qubit no longer certifies cleanliness, so the edge-deletion procedure is incorrect and the 'extra information' that drives the hybrid benefit is corrupted. The paper explicitly acknowledges these limitations in Section IV.D and Section VII and cites related work on imperfect erasure checks, but it does not model them. Because the headline claim is specifically about a fixed transmon budget and near-term-relevant parameters, the sensitivity of the transmon-budget comparison to realistic erasure-check fidelity is the most load-bearing uncertainty. Within the stated idealized model the simulations and analysis are plausible, but the unqualified statement of the central claim overstates robustness; this is an external-validity concern rather than an internal inconsistency.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper proposes a hybrid-erasure surface code architecture in which a strategically chosen subset of data qubits are implemented as dual-rail erasure qubits while the remaining qubits are standard transmons. The authors derive a code-capacity effective-distance bound (Eq. 2) based on the number of full rows and columns of erasure qubits that any lattice-traversing error path must cross, propose a center-first placement heuristic, and validate the heuristic through circuit-level simulations using Stim and PyMatching. They then compare logical error rates as a function of transmon budget for hybrid, all-standard, and all-erasure architectures (Figures 9 and 10), concluding that hybrid layouts can outperform both homogeneous layouts for certain intermediate transmon budgets, particularly at near-term system sizes. The paper is explicitly exploratory and includes a limitations section (Section IV.D) that acknowledges the main idealizations.","tokens_in":19402,"tokens_out":7780,"duration_ms":82863,"significance":"The hybrid-interpolation idea is timely and practically motivated. The paper has several genuine strengths: Eq. (2) is an explicit closed-form bound with no fitted constants; the placement heuristic is derived from an error-path counting argument and is then checked against independent circuit-level simulations; the simulation methodology uses widely available open-source tools (Stim and PyMatching), making the results reproducible; and the authors are transparent about the assumptions behind their noise model. If the stated idealized noise model is accepted, the central transmon-budget conclusion is credible for small to intermediate code distances. The main caveat is that the advantage rests on perfect erasure checks and fully heralded erasure errors, both acknowledged but not modeled, so the quantitative scope of the headline claim remains conditional.","major_comments":[{"comment":"The decoder's treatment of erasure flags is load-bearing for the headline claim. In Section IV.B, edges are removed from the decoding graph when no erasure flag is observed, which is equivalent to treating an unflagged erasure qubit as certified error-free. This is justified only under the Section IV.A assumption that erasure checks are perfect, with no false positives or false negatives, and under the Section IV.B assumption that every error on an erasure qubit is a heralded erasure followed by a maximally mixed replacement. Section IV.D acknowledges that real checks are imperfect and that unheralded Pauli errors exist, but these are not modeled. A false negative or an unheralded Pauli error would corrupt the 'no-erasure' information and make the edge-deletion step incorrect, potentially shrinking or eliminating the transmon-budget advantage claimed in Section V.B. I request either a sensitivity analysis with nonzero erasure-check error rates and unheralded Pauli fractions, or a clearly stated set of conditions under which the advantage persists. The abstract and conclusion should also carry this qualifier.","section":"Section IV.A/IV.B/IV.D"},{"comment":"The transmon-budget comparisons are computed at a single parameter point: the noise ratios in Table I and the three-transmon cost per erasure qubit. Section IV.D concedes that the results are sensitive to these ratios and that reducing the cost or error-rate ratio would contract the regions where hybrid architectures outperform the homogeneous alternatives. Because the central claim is specifically about 'certain transmon budgets', the paper should provide a quantitative sensitivity scan over the erasure-to-standard error-rate ratio and over the erasure-qubit cost (for example, the two-transmon cavity-readout implementation mentioned in Section IV.D). Without such a scan, the reader cannot tell whether the observed hybrid advantage is robust or an artifact of the chosen parameter point.","section":"Table I, Section IV.D, Section V.B"}],"minor_comments":[{"comment":"The epsilon term in Eq. (2) is not defined consistently: Section III.A writes 'epsilon_d approximately -d/log p < 1', while Section III.D defines 'epsilon = -d/log_2 p'. The notation should be unified and the sign/convergence statement clarified.","section":"Section III.A/III.D"},{"comment":"The sentence 'Indeed, when epsilon_k < 1...' appears to contain a typo: the subscript should likely be 'd' rather than 'k'.","section":"Section III.A"},{"comment":"The passage 'In Stim, the erasure flag is' ends mid-sentence; the description of how the erasure flag is implemented in Stim should be completed.","section":"Section IV.B"},{"comment":"The sentence 'Figure ?? shows the extracted surface code thresholds...' has an unresolved figure reference; presumably the right panel of Figure 8 is intended.","section":"Section V.A"},{"comment":"The sentence 'Again, we can that hybrid-erasure schemes allow...' is missing a verb, likely 'see'.","section":"Section V.B"},{"comment":"The text refers to '(Top, Figure 9)' and '(Bottom, Figure 9)' when describing the panels of Figure 10; the figure references appear to be incorrect.","section":"Section V.C"},{"comment":"The word 'prove' in the summary of results is stronger than the leading-order error-path argument that follows in Sections III.C and III.D. Consider rephrasing to 'derive' or 'argue' to match the level of rigor actually supplied.","section":"Section III.A"}],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: the hybrid-erasure allocation problem is the real contribution here; prior erasure-qubit work was all-or-nothing. The paper asks where a limited number of dual-rail erasure qubits should go in a transmon surface code, proposes a center-first row-and-column heuristic, derives a path-counting effective-distance bound (Eq. 2), and tests it with Stim/PyMatching circuit-level simulations. That is a genuine new angle, and the heuristic is well-motivated: central rows and columns maximize the number of lattice-traversing paths intercepted, and the bound is self-contained with no fitted constants.\n\nWhat the paper does well: it is transparent about its model. Section IV.D lists the perfect erasure-check assumption, the all-heralded-error assumption, and the sensitivity to the fixed noise ratios in Table I. Section VI-C explicitly compares the capacity model to circuit-level results and notes where they deviate. The simulation methodology is standard, and the placement validation (consecutive vs. alternate columns, orientation, centrality) is thorough. One caveat: Eq. 2 is presented as a proof, but the derivation is really a union-bound approximation; the paper itself later calls it an approximation, so treat it as a capacity-level estimate rather than a hard guarantee.\n\nWhere I would push back: the soft spots are real, and they are load-bearing for the headline transmon-budget comparison. The decoder deletes edges for unflagged erasure qubits, so an absent flag is treated as a certificate of cleanliness. If erasure checks have false positives or negatives, as they do in hardware, that certificate is corrupted and the hybrid advantage could shrink or disappear. The paper acknowledges this but does not model it, even though the related literature on imperfect checks is cited. Similarly, unheralded Pauli errors on erasure qubits are acknowledged but unmodeled. The simulation plots lack error bars, which makes it hard to judge whether the reported hybrid-over-full-erasure improvements at fixed transmon counts are statistically meaningful. And no code or data is shipped, which is a real limitation for a simulation-driven architecture paper. The large-system extrapolations reuse the same capacity model they are validating, which is a mild circularity, though the bound-and-shaded-region presentation keeps it honest.\n\nNone of this sinks the paper. Within the stated noise model, the central result is internally consistent and the authors are unusually explicit about what they left out. The risk is external validity, not internal contradiction: the quantitative transmon-budget advantage is likely a best-case estimate, and the paper reads as such. If I were editing, I would send it to peer review and ask for an imperfect-check sensitivity analysis, error bars (or a statement about shot counts), and a code/data release. It is the kind of paper that will be most useful to QEC architecture researchers working on near-term superconducting hardware, and it deserves a serious referee.","headline":"A useful, honest first pass at hybrid erasure placement for surface codes; the transmon-budget advantage is plausible but hinges on perfect erasure checks, so read it as a best-case architecture study.","tokens_in":20008,"tokens_out":3908,"would_cite":true,"duration_ms":41107,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["03.67.Pp"],"model":"deepseek-v4-flash","headline":"A hybrid surface code with strategically placed erasure qubits reaches lower logical error rates than all-standard or all-erasure designs at the same transmon budget.","keywords":["quantum error correction","erasure qubits","surface code","dual-rail transmon","hybrid erasure architecture","effective distance","logical error rate","qubit placement"],"falsifier":"Run the same circuit-level sweep with finite erasure-check false-positive and false-negative rates, for example 1% and 5%, and check whether any transmon budget still favors the hybrid layout over both all-standard and all-erasure chips; if the hybrid curve never falls below both homogeneous curves at fixed transmon count, the central claim is refuted.","tokens_in":18944,"feed_emoji":"⚛️","tokens_out":7181,"duration_ms":75219,"temperature":0.7,"pith_summary":"The paper tries to establish that you do not need every qubit to be an erasure qubit to capture most of the benefit. It proposes a hybrid surface code in which a selected subset of data qubits are dual-rail erasure qubits, each costing three transmons, while the rest remain standard. With erasure qubits placed in full central rows and columns, effective distance and threshold improve steadily as the erasure fraction grows, and for certain fixed transmon budgets the hybrid layout beats both an all-standard and an all-erasure chip. This matters because fabrication yield and refrigerator cooling limit the number of transmons available, so spending transmons where they buy the most logical performance is a practical architectural choice.","feed_headline":"Partial erasure beats full erasure in surface codes","feed_subtitle":"Centrally placed dual-rail qubits cut logical error rates at fixed transmon budgets, especially for near-term-sized patches.","key_machinery":"The load-bearing object is the hybrid-erasure architecture $A(d,f_e,P)$: a distance-$d$ surface-code patch with erasure fraction $f_e$ placed on data-qubit subset $P$. The argument decomposes logical errors into lattice-traversing paths, connected chains of errors crossing the patch, and shows that once $k$ full rows and columns are filled with erasure qubits, every such path must cross at least $k$ erasure qubits. This reduces the effective-distance analysis to a repetition-code-like chain with $k$ clean barriers and yields the bound in Eq. 2. In circuit-level decoding, the machinery is the erasure flag: when an erasure check fires, the correlated error set's decoding-graph edges are reweighted, and when it does not fire, those edges are removed from the graph, so the decoder has strictly more information than the syndrome alone provides.","core_discovery":"The paper's central claim is that a distance-$d$ surface-code patch with a chosen subset of data qubits as dual-rail erasure qubits—optimally arranged in full rows and columns radiating from the center—achieves effective distance at least $\\lfloor(d(2-\\sqrt{1-f_e})+1)/2\\rfloor-\\epsilon_d$ for erasure fraction $f_e$, interpolating between the standard surface code and the all-erasure surface code. Code-capacity analysis and circuit-level simulations for distances 3, 5, and 7 show effective distance and threshold rising with erasure fraction, and for fixed transmon budgets near 70–100 and 150–190 transmons the hybrid chip reaches lower logical error rates than either homogeneous extreme. The mechanism is that erasure qubits supply the decoder with certified information about where errors did and did not occur, converting a blind error-guessing problem into a Minesweeper-like deduction.","pith_inferences":["Beyond the paper: because filled rows and columns of erasure qubits block logical error paths, the same placement heuristic should give tunable asymmetric protection under biased noise, offering a cheaper alternative to nonsquare or XZZX surface codes.","Beyond the paper: if imperfect erasure checks are included, the optimal erasure fraction should drop and the transmon-budget window should narrow; sweeping false-positive and false-negative rates would map exactly where the hybrid design still wins.","Beyond the paper: the placement heuristic could be repurposed for defect tolerance, reserving erasure positions on known-bad or high-error transmon locations rather than allocating them before fabrication data is known.","Beyond the paper: the circuit-level checkerboard correlation pattern suggests that CNOT scheduling, not just placement, controls which error channel benefits; rotating the stabilizer schedule could make the hybrid gain channel-specific and testable in simulation."],"forward_implications":["Effective distance and threshold rise monotonically with erasure fraction, interpolating between the standard surface code and the all-erasure surface code.","Placement is decisive: central rows and columns outperform random placement at intermediate erasure fractions, with the largest gains on qubits that appear in the most lattice-traversing paths.","For fixed transmon budgets around 70–100 and 150–190 transmons, a hybrid chip can reach lower logical error rates than either an all-standard or an all-erasure chip at the same cost.","The hybrid advantage shrinks as system size grows, so the payoff is largest for near-term small-distance patches and for concatenated-code settings that rely on small surface-code patches."],"supporting_citations":[{"why":"Supplies the dual-rail transmon erasure-qubit implementation and the three-transmon cost model that drives the budget comparison.","marker":"[15]"},{"why":"Establishes the high-threshold erasure-qubit surface-code baseline that the hybrid architecture interpolates toward.","marker":"[13]"},{"why":"Provides threshold results for topological codes with erasure or loss, grounding the all-erasure endpoint.","marker":"[37]"},{"why":"Supplies the maximum-likelihood decoding framework and repetition-code logical-error analysis used in the toy model.","marker":"[44]"},{"why":"Provides the lattice-path counting sequence used to quantify how often each qubit appears in logical error paths.","marker":"[45]"},{"why":"Implements the stabilizer-circuit simulations that produce the circuit-level logical error rate data.","marker":"[47]"},{"why":"Provides the minimum-weight perfect matching decoder whose decoding graph is reweighted or pruned by erasure flags.","marker":"[48]"},{"why":"Documents the impact of imperfect erasure checks, which is the paper's acknowledged limitation and a benchmark for future work.","marker":"[46]"},{"why":"Studies erasure-check scheduling and optimized error-correction protocols with erasure qubits.","marker":"[39]"}],"fun_headline_variants":["Hybrid erasure beats full for surface code error correction","Minesweeper-inspired qubit layout cuts logical errors","Strategic erasure qubits improve surface code performance","Partial erasure: optimal for transmon budgets","Central erasure rows boost quantum error correction"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument depends on erasure checks never being wrong and on every erasure-qubit error being announced; if real checks miss detections or falsely flag, the decoder's special knowledge is corrupted, and the claimed transmon-budget advantage could shrink or disappear.","fun_headline_variants_meta":{"raw":{"variants":["Hybrid erasure beats full for surface code error correction","Minesweeper-inspired qubit layout cuts logical errors","Strategic erasure qubits improve surface code performance","Partial erasure: optimal for transmon budgets","Central erasure rows boost quantum error correction"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000247,"raw_usage":{"total_tokens":1551,"prompt_tokens":960,"completion_tokens":591,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":576,"completion_tokens_details":{"reasoning_tokens":527}},"tokens_in":576,"tokens_out":591,"duration_ms":6275,"temperature":1.0,"reasoning_tokens":527,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T04:52:32.605934+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same circuit-level sweep with finite erasure-check false-positive and false-negative rates, for example 1% and 5%, and check whether any transmon budget still favors the hybrid layout over both all-standard and all-erasure chips; if the hybrid curve never falls below both homogeneous curves at fixed transmon count, the central claim is refuted.","supporting_citations":[{"cited_title":"Erasure Qubits: Overcoming the T 1 Limit in Superconducting Circuits,","cited_arxiv_id":null,"evidence_quote":"Supplies the dual-rail transmon erasure-qubit implementation and the three-transmon cost model that drives the budget comparison."},{"cited_title":"Thresholds for Topological Codes in the Presence of Loss,","cited_arxiv_id":null,"evidence_quote":"Provides threshold results for topological codes with erasure or loss, grounding the all-erasure endpoint."},{"cited_title":"Topological quantum memory,","cited_arxiv_id":null,"evidence_quote":"Supplies the maximum-likelihood decoding framework and repetition-code logical-error analysis used in the toy model."},{"cited_title":"The On-Line Encyclopedia of Integer Sequences,","cited_arxiv_id":null,"evidence_quote":"Provides the lattice-path counting sequence used to quantify how often each qubit appears in logical error paths."},{"cited_title":"Stim: a fast stabilizer circuit simulator,","cited_arxiv_id":null,"evidence_quote":"Implements the stabilizer-circuit simulations that produce the circuit-level logical error rate data."}],"review_version":1}