{"id":"e78bca99-21e8-4b6a-b762-b6ae62a81c10","arxiv_id":"2505.01316","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":8,"one_line_summary":"S-SYNC unifies shuttling and SWAP operations into a single 'generic swap' on a static graph, and a greedy heuristic co-optimizes them to cut shuttling by 3.69x and raise success rate by 1.73x on average in simulation.","lead":"This paper presents S-SYNC, a compiler for trapped-ion quantum computers that plans qubit movements and swap gates together. It reports up to 3.69x fewer shuttling moves and 1.73x higher application success rates in simulations, which matters because QCCD chips are a leading path to larger quantum computers.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Eq. (4) fidelity model is internally inconsistent with stated Γ=1 and microsecond times, so the reported 1.73x success-rate improvement is unsupported as written.","rationale":"Paper's core algorithmic idea — representing qubits and empty slots as nodes in a static graph and treating SWAPs and shuttles as generic swaps — is coherent, and the shuttle/SWAP reductions are plausible from the figures. However, the success-rate evaluation, which is half of the headline result (1.73x), is built on Eq. (4). With Γ=1 and τ in microseconds, that equation yields negative fidelities for any operation longer than 1 μs, and most listed operations are 5–80 μs or more. The reported success rates in Fig. 10 are all between 0 and 1, so the simulation must have used something other than the literal equation, e.g., an exponential fidelity, a scaled Γ, or normalized times. This is an internal inconsistency, not merely a question of whether the linear noise model is realistic. The reader's weakest_assumption correctly identifies the fidelity model as load-bearing but does not catch that the model as specified is numerically impossible. This makes the success-rate claim unverifiable and supports the CONDITIONAL verdict, pending a corrected fidelity model and ideally released code.","tokens_in":22894,"tokens_out":6979,"duration_ms":66119,"concrete_test":"Recompute the success rate for BV_64 on the S-4 topology from the reported schedule using Eq. (4) literally, with Γ=1, Table 1 times, and τ_FM(N) = max(13.33N−54,100) μs. If the per-gate fidelity is negative or the product is not in (0,1], the published success rates require a different fidelity model. Request the exact formula and parameter values used to generate Fig. 10 from the authors.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 4.1 defines per-gate fidelity as F = 1 − Γτ − A(2n̄+1) (Eq. 4), sets Γ = 1, and lists operation times in microseconds: split/merge 80 μs, junction 40+20n μs, FM gate τ_FM(N) = max(13.33N−54,100) μs. With Γ=1, a single split contributes Γτ = 80, so the fidelity of any gate preceded by a split is ≤ −79. The product over a circuit would be negative or zero in most cases, yet Fig. 10 reports success rates in (0,1] for all benchmarks (e.g., BV_64 ≈ 0.8–1.0). Thus the stated model, together with the stated parameters and units, cannot produce the reported success rates. The success-rate improvement (1.73x average) and the topology/capacity guidance in Figs. 10–12 therefore rest on an unstated fidelity model or parameter normalization that is not given in the paper. This is a correctness risk in the central quantitative claim, independent of whether the linear model is a good approximation to real QCCD noise.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces S-SYNC, a compiler for QCCD trapped-ion devices that represents the device as a static weighted graph containing both qubit nodes and empty space nodes. It defines a unified 'generic swap' operation covering SWAP gates, intra-trap reordering, and shuttling, and schedules circuits with a greedy heuristic using a distance-based cost function plus penalties for blocked traps and repeated moves. The authors evaluate S-SYNC on benchmarks of 24-66 qubits against the Murali et al. and Dai et al. compilers across several QCCD topologies, reporting a 3.69x average reduction in shuttle count and a 1.73x average improvement in success rate. They also analyze the effect of topology, trap capacity, gate implementation choices, initial mappings, and hyperparameters, and compare compilation time and optimality against idealized scenarios.","tokens_in":23091,"tokens_out":11166,"duration_ms":112455,"significance":"If the results hold, S-SYNC contributes a useful abstraction for QCCD compilation: treating space nodes as first-class graph vertices solves the previously noted problem that the QCCD topology changes after each shuttle, and the generic-swap formulation cleanly unifies SWAP and shuttling costs. The shuttle-count and SWAP-count reductions in Figs. 8-9 are plausible and would be valuable even without the fidelity model. However, the headline success-rate improvement of 1.73x and the topology and capacity guidance in Figs. 10-12 rest entirely on Eq. (4), which is not specified consistently enough to reproduce the reported numbers. The paper does not release code and contains no machine-checked proofs, so the quantitative claims currently depend on an unverified and partially described noise model. The central scheduling mechanism itself is described completely enough to be reimplemented, and the sensitivity analysis for the heuristic weights is a positive feature.","major_comments":[{"comment":"The success-rate model is not internally consistent as written. The text sets Γ = 1 while Table 1 lists split/merge times of 80 μs, junction times of 40+20n μs, and FM gate times of hundreds of microseconds. If τ in Eq. (4) is in microseconds, a single split contributes Γτ = 80, so the per-gate fidelity is at most 1 - 80 - A(2n̄+1) ≤ -79, and the product over the circuit would be zero or negative. This contradicts the positive success rates in Fig. 10 and makes the logarithmic QFT_64 panel impossible. If τ is intended to be in seconds, or if Γ has nontrivial units, that normalization is never stated. Since the 1.73x success-rate claim and Figs. 10-12 all depend on Eq. (4), the reported success-rate results are unsupported as written.","section":"Section 4.1, Eq. (4)"},{"comment":"The terms in Eq. (4) are not quantitatively defined. The text states that A ∝ N/ln(N) but gives no proportionality constant, and it does not specify how split, merge, and shuttle operations update n̄ through k1 and k2 or how n̄ is tracked across a circuit. Consequently, the success-rate simulator cannot be reconstructed from the manuscript alone. The authors should provide the complete model, including the value of A and the exact update rule for n̄, or release the simulator code, and then rerun Figs. 10-12.","section":"Section 4.1, Eq. (4)"},{"comment":"The threshold parameter in the static-topology rules is never assigned a value. Rules 1-4 all distinguish operations by whether W(u,v) is below or above the threshold, and the resulting shuttle and SWAP counts in Figs. 8-9 depend on this distinction. Section 4.2 gives inner weight 0.001, shuttle segment weight 1, and junction multipliers, but no threshold value. The reported counts are therefore not reproducible, and the threshold should be stated and preferably included in the sensitivity analysis.","section":"Section 3.1 and Section 4.2"}],"minor_comments":[{"comment":"The decay rate is set to δ = 0.0001 in Section 4.2 but to δ = 0.001 in Section 5.5; the correct value used for the main results should be stated consistently.","section":"Section 4.2 vs Section 5.5"},{"comment":"The text says that m = 2 is 'sufficient to achieve near-optimal results in most cases, as shown in Fig. 16,' but Fig. 16 compares S-SYNC against idealized perfect-shuttle and perfect-SWAP scenarios and does not sweep m. Please either add an m-sweep figure or correct the cross-reference.","section":"Section 4.2, Fig. 16"},{"comment":"The intra-trap mapping score l(q_i) = -αE(q_i) + βI(q_i) uses parameters α and β, but no values are given in the experimental section. The STA-mapping curves in Fig. 12 cannot be reproduced without these values.","section":"Section 3.4, Eq. (3)"},{"comment":"References [48] and [49] are the same Murali et al. ISCA 2020 paper; the duplicate should be removed and the citation in Observation 3 should be fixed.","section":"References [48] and [49]"},{"comment":"The y-axis for QFT_64 is logarithmic while the other panels are linear; this should be stated explicitly in the caption.","section":"Fig. 10 caption"},{"comment":"The phrase 'significantly extend execution time' should be 'significantly extending execution time' or 'significantly extend execution times'.","section":"Abstract"},{"comment":"The headline 3.69x average shuttle reduction is not directly derivable from the per-benchmark percentages reported in Section 5.1; a summary table with per-benchmark counts and the averaging procedure would allow the reader to verify the number.","section":"Abstract and Section 5.1"}],"recommendation":"major_revision","confidential_remarks":"The core scheduling abstraction is sound and the shuttle/SWAP reductions may well survive, but the paper's headline success-rate claims rest on a fidelity model that is not specified consistently and, as written, cannot produce the reported positive success rates. In addition, the threshold parameter and several hyperparameters are undocumented. I would ask for the full noise model and all parameter values, ideally with the simulator released, before accepting the quantitative claims."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Punchline: the static-topology formulation with space nodes is the real idea here, and it's worth stealing even if the headline numbers need a closer look.\n\nWhat's genuinely new: representing both qubits and empty slots as nodes on a fixed graph, so shuttle operations become node swaps. That sidesteps the dynamic-topology problem that makes superconducting-style compilers awkward for QCCD, and it lets you co-optimize SWAP gates and shuttles under one cost function. The greedy heuristic is clearly described, and the shuttle-count reductions against Murali et al. and Dai et al. (3.69x average) are plausible as an algorithmic outcome. I'm not suspicious of those.\n\nWhere it gets soft: the success-rate claim. Eq. (4)'s fidelity model is borrowed from Murali, which is fine in principle, but the paper sets Γ=1 and gives operation times in microseconds. With that, a single split already contributes Γτ=80, so any gate after it gets fidelity below -79, and the product over a circuit is nonsense. Yet Fig. 10 reports success rates in (0,1], so either the parameters or the model as written can't be what actually produced the numbers. That's a load-bearing problem for the 1.73x improvement in the abstract. The shuttle/SWAP reductions don't depend on that model, so those likely stand. Minor issues: no code or data, α and β in Eq. (3) are never specified, and the decay rate δ is given as 0.0001 in one place and 0.001 in another. These are fixable.\n\nMy sense: this deserves a serious referee. The modeling idea is good, and the shuttle/SWAP reductions are useful. The referee should require a corrected noise-model specification and either code or enough parameters to reproduce the success rates. If that can't be done, the success-rate numbers should come out of the abstract. Otherwise it's a solid engineering paper for compiler and trapped-ion architecture people.","headline":"S-SYNC's space-node trick is a real contribution, but the success-rate numbers don't survive contact with the paper's own fidelity model.","tokens_in":23689,"tokens_out":4255,"would_cite":true,"duration_ms":41229,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["03.67.Lx"],"model":"deepseek-v4-flash","headline":"S-SYNC claims that co-optimizing shuttling and SWAPs as generic swaps on a static weighted QCCD graph cuts shuttle counts by 3.69x and raises average success rate by 1.73x.","keywords":["S-SYNC","quantum charge-coupled device","trapped-ion quantum computing","qubit mapping","shuttling scheduling","SWAP optimization","QCCD topology","success rate"],"falsifier":"Measure success rates of S-SYNC-scheduled circuits on a real QCCD device (or on a simulator whose noise model is fitted to direct heating measurements) and compare against the linear-model predictions. If the success-rate advantage over the baselines shrinks or reverses once heating is measured rather than assumed proportional to operation time and motional quanta, the central success-rate claim is falsified. A sharper experiment: repeatedly shuttle ions through the same junction and record gate fidelity as a function of prior shuttle count; superlinear degradation would violate the model's additive per-operation cost assumption.","tokens_in":22629,"feed_emoji":"⚛️","tokens_out":10255,"duration_ms":99632,"temperature":0.7,"pith_summary":"The paper tries to establish that a compiler for quantum-charge-coupled-device (QCCD) trapped-ion computers should schedule ion shuttling and SWAP gates together, not separately, because the two operations are physically coupled: moving an ion chain almost always forces reordering, and reordering costs SWAPs. Its proposal, S-SYNC, rewrites the QCCD device as a weighted static graph that includes empty 'space nodes', so every physical operation--splitting, merging, moving ions between traps, swapping qubits--becomes one unified node interchange that the paper calls a generic swap. On this graph the scheduler searches heuristically for low-cost generic swaps until all two-qubit gates are executable, and this co-optimization is reported to reduce the number of shuttles by 3.69x on average and improve application success rate by 1.73x on average across QFT, adder, BV, QAOA, and alternating-layer-ansatz benchmarks on linear, grid, and fully connected QCCD topologies. A reader should care because shuttling is the dominant error and time cost in scaling trapped-ion devices; if this reduction transfers to hardware, near-term QCCD devices can run larger algorithms, and the static-topology formulation lets a large toolbox of qubit-routing heuristics be reused for trapped-ion hardware.","feed_headline":"Treating shuttles and SWAPs as one move cuts ion shuttling 3.69x","feed_subtitle":"Static-graph 'generic swap' scheduling also lifts average application success rate by 1.73x versus prior compilers.","key_machinery":"The load-bearing object is S-SYNC's static weighted graph with space nodes, together with the generic swap it defines. A space node is simply a free slot in a trap that can hold one ion; the graph has an edge between any two nodes whose contents can be interchanged, with weights such as $w_1 = 0.001$ for an intra-trap move and $w_2, w_3, w_4$ scaling with distance and junction crossings. Because every QCCD operation--splitting, merging, shuttling between traps, and SWAP-based reordering--is represented as one generic swap (interchange of two nodes), the topology graph stays fixed through the whole schedule, which removes the dynamic-topology problem that prevented standard routing algorithms from being applied. The scheduler's heuristic $H(\\mathit{swap})$ evaluates each candidate generic swap by the shortest weighted path needed to bring the two qubits of a frontier gate together, plus a penalty for traps that contain no free space, and a decay term that discourages repeatedly moving the same qubits; the lowest-scoring move is applied and the search repeats until the circuit's dependency graph is exhausted.","core_discovery":"The central claim is that the QCCD scheduling problem can be made static: represent every occupied or empty trap slot as a node of a weighted connectivity graph, with edge weights expressing whether swapping two nodes costs a cheap intra-trap SWAP, a costly shuttle, or a junction crossing. A shuttle physically exchanges a qubit with an empty space, a SWAP exchanges two qubits, and repositioning space within a trap is also a node interchange, so all operations share one form. The paper names this unified operation a generic swap. On top of this representation S-SYNC builds a DAG-aware greedy scheduler: whenever no ready gate can be executed, it scores every candidate generic swap with $H(\\mathit{swap}) = \\min_g \\{ \\mathit{decay}(g) \\cdot \\mathit{score}(g) \\} + w(\\mathit{swap})$, where score combines the weighted path between the two qubits of the most urgent gate and a penalty for traps with no free space, then applies the lowest-scoring move. The paper argues this co-optimization, rather than minimizing shuttles or SWAPs in isolation, is what yields the reported 3.69x shuttle reduction and 1.73x success-rate improvement over the prior compiler baselines, and it uses the same machinery to draw architectural conclusions: grid-type topologies generally beat linear ones, and peak success rates occur at roughly 10-15 qubits per trap.","pith_inferences":["The generic-swap abstraction suggests QCCD scheduling can be recast as token swapping on a graph where empty vertices are mobile, which would let exact and near-exact routing methods from the circuit-mapping literature be tested against S-SYNC's greedy search; the paper does not explore this connection.","Because the success-rate model assumes heating adds a fixed number of motional quanta per split/merge/shuttle, a direct measurement of how gate fidelity degrades with cumulative shuttling through junctions would tell whether the 1.73x improvement is optimistic, pessimistic, or roughly right under real QCCD noise.","The same static-graph formulation could extend to mixed-species or memory-zone QCCD designs where some ions are immobile, by adding constraints that lock certain nodes from interchange; this is a natural next step not treated in the paper.","The paper's benchmark evidence suggests that the best compiler choices depend on gate implementation (AM2 for short-range gates, FM/PM for long-range), so hardware vendors reporting gate times and heating rates could let S-SYNC-style compilers tune their weights automatically; such auto-tuning is not in the paper."],"forward_implications":["Prior superconducting-style qubit-routing and SWAP-insertion heuristics become applicable to QCCD, because the static graph with space nodes keeps the connectivity fixed throughout scheduling.","The reported reductions mean near-term QCCD applications spend fewer operations on movement, directly cutting the main source of heating-induced error and execution-time overhead in trapped-ion systems.","The topology study implies device designers can expect grid- or ring-style QCCD layouts to outperform linear layouts for most applications, and that trap capacities around 10-15 ions are the sweet spot for success rate.","Initial mapping choices trade shuttles against execution time: gathering mapping minimizes shuttles but can reduce success rate under frequency-modulated gates, since longer ion chains make those gates slower.","S-SYNC comes close to the idealized 'perfect SWAP' bound but retains a gap to 'perfect shuttle', so further gains are available specifically in shuttle scheduling rather than in SWAP reduction."],"supporting_citations":[{"why":"Supplies the baseline compiler, the benchmark suite, the noise-model constants ($\\Gamma=1$, $k_1=0.1$, $k_2=0.01$), and the simulator against which S-SYNC's improvements are measured.","marker":"[48]"},{"why":"Supplies the second baseline compiler with advanced shuttle strategies for parallel QCCD architectures that S-SYNC is compared against.","marker":"[15]"},{"why":"The open-source QCCD simulator and benchmark source code the paper directly uses for its evaluations.","marker":"[61]"},{"why":"The original QCCD architecture proposal that defines the split, move, and merge operations the static-graph formulation encodes.","marker":"[30]"},{"why":"The modular trapped-ion expansion protocol that motivates the QCCD operational model used throughout the paper.","marker":"[81]"},{"why":"Supplies the frequency-modulated gate time formula $\\tau_{FM}(N)=\\max(13.33N-54,100)$, which drives the trade-off between gathering qubits and extending execution time.","marker":"[36]"},{"why":"Provides the junction transport time constants used in the Table 1 weights for shuttles that cross junctions.","marker":"[5]"},{"why":"Supplies the split, merge, and move timing values used in the execution-time model that feeds the fidelity calculation.","marker":"[21]"},{"why":"Supplies the STA initial-mapping method that S-SYNC compares against its gathering and even-divided mappings.","marker":"[56]"},{"why":"The hardware roadmap whose device shapes and capacities define the linear, grid, and fully connected topologies tested in the evaluation.","marker":"[62]"}],"fun_headline_variants":["Co-optimizing shuttles and swaps cuts ion shuttling 3.69x","S-SYNC: one operation for shuttles and swaps, 3.69x fewer shuttles","Unified shuttle-swap scheduling lifts QCCD success rate 1.73x","Co-optimized ion shuttle and swap scheduling boosts success 1.73x","Generic swap co-optimization reduces shuttling 3.69x and improves success"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The paper's central success-rate improvement rests on a linear fidelity model, $F = 1 - \\Gamma\\tau - A(2\\bar{n}+1)$, with heating constants $k_1=0.1$ and $k_2=0.01$ taken from a prior trapped-ion study; if real QCCD noise grows nonlinearly with chain size or depends on the history of previous shuttles, the 1.73x success-rate claim and the topology/capacity guidance would not survive contact with hardware, even if the shuttle-count reductions themselves are real.","fun_headline_variants_meta":{"raw":{"variants":["Co-optimizing shuttles and swaps cuts ion shuttling 3.69x","S-SYNC: one operation for shuttles and swaps, 3.69x fewer shuttles","Unified shuttle-swap scheduling lifts QCCD success rate 1.73x","Co-optimized ion shuttle and swap scheduling boosts success 1.73x","Generic swap co-optimization reduces shuttling 3.69x and improves success"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00086,"raw_usage":{"total_tokens":3797,"prompt_tokens":1076,"completion_tokens":2721,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":692,"completion_tokens_details":{"reasoning_tokens":2602}},"tokens_in":692,"tokens_out":2721,"duration_ms":19541,"temperature":1.0,"reasoning_tokens":2602,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T04:20:59.037811+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure success rates of S-SYNC-scheduled circuits on a real QCCD device (or on a simulator whose noise model is fitted to direct heating measurements) and compare against the linear-model predictions. If the success-rate advantage over the baselines shrinks or reverses once heating is measured rather than assumed proportional to operation time and motional quanta, the central success-rate claim is falsified. A sharper experiment: repeatedly shuttle ions through the same junction and record gate fidelity as a function of prior shuttle count; superlinear degradation would violate the model's additive per-operation cost assumption.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The open-source QCCD simulator and benchmark source code the paper directly uses for its evaluations."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The original QCCD architecture proposal that defines the split, move, and merge operations the static-graph formulation encodes."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The modular trapped-ion expansion protocol that motivates the QCCD operational model used throughout the paper."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the frequency-modulated gate time formula $\\tau_{FM}(N)=\\max(13.33N-54,100)$, which drives the trade-off between gathering qubits and extending execution time."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The hardware roadmap whose device shapes and capacities define the linear, grid, and fully connected topologies tested in the evaluation."}],"review_version":1}