{"id":"72a994e7-4ef7-4e63-a657-3254de5b7223","arxiv_id":"2505.02181","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A time-domain popcount built from programmable delay lines and arbiters is demonstrated on FPGA, giving asynchronous Tsetlin Machine inference reported latency, power, and resource savings over adder-based designs.","lead":"This paper replaces digital adder-based vote counting in Tsetlin Machine classifiers with chains of delay lines whose propagation time encodes the vote count, then uses an arbiter to find the winner. The authors demonstrate the idea on an FPGA in an asynchronous design, reporting up to 38% lower latency, 43.1% lower dynamic power, and 15% lower resource use versus synchronous adder-based TMs.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Spearman monotonicity in Fig. 6 does not rule out position-dependent PDL delays; equal-Hamming-weight vectors may still race differently.","rationale":"The reader's weakest assumption already points at manual placement/routing uniformity and residual skew; this stress-test sharpens it into a concrete pattern-invariance requirement. The central claim has two parts: (1) PDL delay maps Hamming weight monotonically, and (2) the asynchronous TM realizes the claimed latency, power, and resource gains. The concern targets part (1), since if part (1) fails for some inputs the architecture is functionally wrong even on a single board. A Spearman rank correlation close to -1 over one measurement per Hamming weight does not rule out large within-weight spread; if the inputs were generated in canonical order, the measurement mainly validates the tuned delay chain's repeatability rather than popcount behavior. Because each delay element is a physical LUT with manually routed high/low nets, position-dependent skew is expected, and the design flow is an attempt to control it rather than evidence that it is fully controlled. The per-dataset tuning to lossless accuracy is a functional test on one board and on specific data, not a demonstration that the PDL is a pattern-independent counter. The proposed concrete test is inexpensive and would settle whether the central mapping claim holds. Since the reader's verdict is already CONDITIONAL and this concern is a specific, testable instance of the flagged weakest assumption, no verdict adjustment is needed.","tokens_in":12454,"tokens_out":6377,"duration_ms":88082,"concrete_test":"Implement a 100-element PDL with the MNIST-tuned low/high delays (~371/632 ps) using the proposed placement, pin-assignment, and routing flow. For every Hamming weight w, measure propagation delay over many random input vectors of that weight (e.g., 1000 random permutations per w) using the Section III-B.4 characterization method. Verify that the maximum delay for weight w is strictly less than the minimum delay for weight w-1 for all w; any overlap between adjacent weight distributions demonstrates that delay is pattern-dependent and the time-domain popcount does not reliably compute Hamming weight.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim depends on total PDL delay being a function of Hamming weight, not of which bits are set. Section III-B.4 (Fig. 6) validates this only via a Spearman correlation between delay and Hamming weight; it does not report how the weight-varying input vectors were generated, and it does not report the within-weight delay spread. If the measurements used a canonical ordering of ones (e.g., filling bits from one end), position-dependent routing skew would be invisible. Since the PDL is a serial chain of LUT-based delay elements, even with the manual placement/pin/routing flow each element's high-low delay difference can vary with position, so two inputs with the same Hamming weight could produce different total delays and hence different arbiter outcomes. The actual TM deployment uses a delay difference of roughly 233 ps (Table I), whereas Fig. 6 characterizes 60 ps and 600 ps; no monotonicity data are shown at the deployed difference. The trial-and-error tuning to 'lossless accuracy' in Section IV-B is performed per dataset on one board and does not test pattern invariance. This is load-bearing because without pattern-independent delay the circuit is not a popcount, regardless of PVT or board-to-board variation.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper proposes implementing the popcount and argmax operations of Tsetlin Machine (TM) inference in the time domain on FPGA. Each class's clause outputs select low- or high-latency paths through a programmable delay line (PDL), and an arbiter compares arrival times to select the class with the highest Hamming weight. The authors describe a placement, pin-assignment, and routing flow intended to make PDL delay elements uniform, measure the delay-versus-Hamming-weight response on a Xilinx Zynq FPGA, and integrate the popcount into a MOUSETRAP-based asynchronous TM. They report up to 38% lower inference latency, up to 43.1% lower dynamic power, and up to 15% lower resource utilization compared with synchronous adder-based TM implementations.","tokens_in":12595,"tokens_out":5158,"duration_ms":71911,"significance":"The paper addresses a real bottleneck: popcount and argmax dominate TM inference latency and resources. The central mechanism, converting Hamming weight to a monotonic delay, is physically plausible, and Fig. 6 provides direct on-FPGA measurements with Spearman rank correlations very close to -1. The reproducible Tcl-based design flow for placement, pin assignment, and routing is a concrete practical contribution, as is the asynchronous TM integration. However, the headline numbers rest on several assumptions that are not yet fully validated: delay must depend only on Hamming weight, not on which bits are set; the per-dataset tuned delay difference must transfer across inputs and boards; and the asynchronous average latency must be compared fairly against synchronous worst-case latency. If these points are addressed, the result would be a useful addition to low-complexity ML hardware and asynchronous FPGA design.","major_comments":[{"comment":"The monotonicity evidence does not establish that total PDL delay is a function of Hamming weight alone. The manuscript reports Spearman's rho but does not describe how the weight-varying input vectors were generated, nor does it report the spread of delays at fixed Hamming weight. Because the PDL is a serial chain of LUT-based delay elements, position-dependent routing skew or per-element delay variation can make two inputs with the same Hamming weight produce different total delays and hence different arbiter outcomes. Please provide per-Hamming-weight delay distributions (for example, box plots over many random bit assignments) and, ideally, demonstrate that all same-weight vectors produce identical arbiter decisions.","section":"Section III-B.4, Fig. 6"},{"comment":"The high-latency net delay is tuned per dataset by trial and error to the smallest value that gives 'lossless accuracy' (641.9 ps, 593 ps, 603.3 ps, and 632.1 ps in Table I). This makes the accuracy-preservation claim a calibration result rather than an independent prediction. Please define explicitly what 'lossless' is measured against (for example, exact software TM arithmetic), provide a sensitivity analysis around the tuned delay difference, and test at least one additional board or varied voltage/temperature conditions, or state the operating envelope within which the monotonicity and accuracy claims hold.","section":"Section IV-B, Table I"},{"comment":"The latency comparison is asymmetric: the asynchronous design's latency is reported as the average over 100 samples, while the synchronous designs are evaluated using the minimal clock period, i.e., the worst-case critical path. Figure 10 shows that the time-domain worst-case latency is substantially larger than the average, so the 'up to 38% lower latency' claim is not a worst-case improvement. Please report the asynchronous worst-case latency (or, alternatively, the average throughput of the synchronous designs) to provide a like-for-like comparison.","section":"Section IV-C.1, Figs. 9(a) and 10"},{"comment":"The dynamic power comparison is also asymmetric: the synchronous designs' dynamic power is taken from Vivado implementation reports and includes clock-tree switching, while the asynchronous design has no clock. This makes the reported power reduction partly a consequence of the chosen comparison baseline. Please separate the clock-tree contribution from the logic power, or provide on-chip power measurements, before claiming a 43.1% dynamic-power reduction.","section":"Section IV-C.3, Figs. 9(c) and 12"}],"minor_comments":[{"comment":"The text states that the high-latency net delay is adjusted during routing to 'minimize the delay difference' relative to the low-latency net, but then says the goal is to ensure 'adequate granularity and resolution'; please clarify whether the objective is to minimize the difference or to set it to a specific target value.","section":"Section III-A.2"},{"comment":"The accuracy values in Table I are reported without showing the baseline accuracy of the same TM models computed with exact arithmetic; please state the reference used to define 'lossless accuracy'.","section":"Section IV-B, Table I"},{"comment":"Adding error bars or confidence intervals for the measured delays at each Hamming weight would strengthen the figure; the Spearman rho values are statistically meaningful with 150 points, but the current plot does not show the spread of equal-weight measurements.","section":"Fig. 6"},{"comment":"The signal transition graph is described informally; labeling the transitions and states in Fig. 8 explicitly would improve reproducibility for readers who want to reimplement the asynchronous controller.","section":"Section IV-A, Fig. 8"},{"comment":"The resource comparison treats LUTs and FFs as equally weighted; since their area and routing impact differ on modern FPGAs, reporting them separately or using a weighted metric would make the 15% resource-saving claim easier to interpret.","section":"Section IV-C.2, Fig. 9(b)"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the scope of asynchronous circuits and FPGA implementation, but the empirical validation is currently thin: the key measurements come from a single board, a single temperature, and per-dataset tuned delays. For a journal version, the authors should be encouraged to add cross-board or PVT variation data, and to present the latency and power comparisons with matched worst-case or average-case metrics. The comparison with ASYNC'21 is based only on equivalent LUT counts, not a full implementation, which should be stated more prominently in the text."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is the first physical FPGA implementation of the PDL-as-popcount idea for Tsetlin Machines, and it mostly delivers what it claims, but the paper's central validation has a gap the authors don't address. The design flow—manual placement, pin assignment to A5/A6, delay-constrained routing—is concrete and transferable. The measured Spearman rho near -1 for 60ps and 600ps delay differences is real evidence that the delay drops monotonically with Hamming weight. The asynchronous TM case study is thoughtful, and the resource and power numbers are interesting.\n\nThe gap is that monotonicity is not the same as being a popcount. For a popcount, total delay must depend on the number of ones, not on which bits are set. The paper never reports the within-weight delay spread, and never describes how the Hamming-weight-varying input vectors were generated. If they filled ones from one end, position-dependent routing skew would be hidden. The deployed delay difference is roughly 233ps (Table I), but Fig. 6 only shows 60ps and 600ps. The trial-and-error tuning to 'lossless accuracy' is a functional check, but it is per dataset on one board and does not test pattern invariance. This is load-bearing: without weight-only behavior the circuit is just an arbiter that happens to work on the test inputs, not a popcount.\n\nThe other soft spots are more minor. The async latency is an average over 100 samples while the synchronous baseline is the worst-case clock period; that is an apples-to-oranges comparison, though it is at least disclosed. 'Lossless accuracy' is claimed but not tabulated, so I cannot tell whether any samples were misclassified. And the delay difference is tuned by trial and error, which is a free parameter that eats into the generality of the headline numbers. None of these are fatal, and the paper genuinely advances [16] from an idea to a working measurement. The question is whether the authors have proven that the time-domain popcount is actually a popcount.\n\nWho is this for: hardware engineers working on Tsetlin machines, binarized NNs, or time-domain circuits. They will get a useful, reproducible design flow and a fair baseline comparison. It deserves peer review, but a serious referee should ask for within-weight spread data at the deployed delay difference, a description of the test vectors, and a tabulated accuracy check before the 'popcount' claim is taken at face value.","headline":"First physical FPGA evidence for PDL-based time-domain popcount, but the weight-only claim needs within-weight spread data before the 'popcount' label holds.","tokens_in":13205,"tokens_out":2815,"would_cite":true,"duration_ms":37502,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper establishes that a time-domain popcount built from programmable delay lines and arbiters can replace adder-based vote counting in a Tsetlin Machine, reporting up to 38% lower latency, 43.1% lower dynamic power, and 15% lower…","keywords":["time-domain popcount","programmable delay line","Tsetlin Machine","asynchronous logic","FPGA implementation","argmax","Hamming weight","low-complexity machine learning"],"falsifier":"Take a second FPGA of the same part, place the same PDL design, and measure propagation delay against Hamming weight over a range of supply voltages and temperatures; if the delay-weight curve stops being monotonic—rank correlation coefficient moving far from $-1$—or if a fixed classifier's accuracy drops below the trained baseline on the same inputs, the paper's central claim is refuted.","tokens_in":12182,"feed_emoji":"⏱️","tokens_out":6942,"duration_ms":77077,"temperature":0.7,"pith_summary":"This paper tries to establish that population count and class comparison—the bottleneck of Tsetlin Machine inference—can be moved from digital adder trees into the time domain, where a count becomes a delay and the largest count is simply the signal that arrives first. It reports that programmable delay lines implemented in FPGA lookup tables give a monotonic, near-linear mapping from Hamming weight to propagation delay, and that arbiters can perform the argmax by racing the delayed signals. If true, the result matters because it removes the clocked worst-case path from the voting step and makes inference latency depend on the actual inputs, not on the slowest possible input. The paper demonstrates this in an asynchronous Tsetlin Machine, claiming up to 38% lower latency, 43.1% lower dynamic power, and up to 15% resource savings against adder-based synchronous designs while keeping classification accuracy lossless.","feed_headline":"Time-domain popcount trims ML inference latency by up to 38%","feed_subtitle":"An asynchronous Tsetlin Machine counts votes with delay lines, also cutting dynamic power by 43.1 percent.","key_machinery":"The programmable delay line (PDL) is the load-bearing object: a cascade of LUT-based delay elements in which each element offers a high-latency net and a low-latency net, selected by one input bit, so that a 0/1 for a positive clause or the reversed polarity for a negative clause adds one unit of delay. The total delay of the chain is inversely proportional to the Hamming weight of the input code, turning popcount into a time measurement. The second mechanism is the arbiter—a NAND SR latch placed symmetrically between two PDLs—that decides which transition arrived first, performing the comparison; completion detection and a two-phase handshake make the result naturally self-timed. The supporting design flow (identical geometric placement, pin assignment to the fastest physical pins, delay-range routing) is what makes the monotonic delay-to-weight mapping actually hold on commercial FPGAs.","core_discovery":"The central discovery is that a programmable delay line (PDL) of cascaded LUT delay elements can act as a popcounter: each input bit of the code selects, through a multiplexer, either a short or a long routing delay, so the total propagation delay falls as the number of ones rises. With symmetric placement of the PDLs, deliberate physical pin assignment to the fastest LUT inputs, and delay-constrained routing, the measured delay decreases monotonically with input Hamming weight, with rank correlation coefficient of $-0.9897$ for a 60 ps delay difference and $-0.9981$ for a 600 ps difference. An arbiter built from cross-coupled NAND gates then reports which of two PDLs finished first, implementing the argmax in essentially constant time regardless of the number of classes. Integrated in a single-rail, two-phase asynchronous TM pipeline, this replaces adder-tree popcount and digital comparators, and the paper reports that the time-domain version reduces latency, dynamic power, and resource use while preserving the trained model's classification accuracy.","pith_inferences":["My inference: if monotonicity holds across temperature and supply-voltage corners, the time-domain vote could be paired with a small training or adaptation loop, since per-sample latency already reflects input difficulty and could be traded against energy.","My inference: the manual trial-and-error tuning of the delay difference suggests an automated calibration routine—for example, sweeping the delay constraint on-chip and checking a known-weight vector—could make the design portable across boards without redesign.","My inference: because the argmax compares arrival times in parallel, the same mechanism could accelerate any winner-take-all over bit-vectors, including k-winner or top-k selection, by cascading arbiter levels."],"forward_implications":["For multi-class tasks, comparison latency grows linearly with class count in adder-based designs but stays nearly constant here, so the advantage widens as classes are added.","Popcount and comparison no longer sit on the worst-case clock path; average-case latency over real inputs can replace the critical-path bound, especially for larger clause counts.","Dynamic power becomes far less sensitive to input switching activity, simplifying power management for battery-operated ML devices.","The same PDL-plus-arbiter structure can be reused in other bit-wise classifiers, with the paper outlining a natural extension to binarized neural networks.","Resource savings persist as the model scales: the time-domain design consistently shows the smallest increase in LUT-plus-FF count when clauses or classes grow."],"supporting_citations":[{"why":"Supplies the basic LUT-based programmable delay line construction from arbiter PUF work that this design adapts to popcount.","marker":"[12]"},{"why":"Provides practitioner's placement and routing guidelines for symmetric PDLs on FPGAs that the design flow follows.","marker":"[15]"},{"why":"Prior proposal of PDL-based TM popcount with asynchronous arbitration, lacking physical implementation; this paper adds the FPGA design flow that makes it work.","marker":"[16]"},{"why":"Documents LUT physical pin delay differences (for example, A6 and A5 being fastest), used to assign low- and high-latency net pins.","marker":"[17]"},{"why":"Supplies the delay characterization method used to measure PDL propagation delay versus input Hamming weight.","marker":"[19]"},{"why":"Provides the MOUSETRAP single-rail two-phase asynchronous pipeline template used for the TM datapath and controller.","marker":"[8]"},{"why":"Serves as the FPT'18 adder-based popcount baseline, reconstructed in a TM architecture and beaten on latency, power, and resources.","marker":"[6]"},{"why":"Provides the ASYNC'21 dual-rail asynchronous TM baseline used for the resource-utilization comparison.","marker":"[24]"}],"fun_headline_variants":["Delay lines replace adders in Tsetlin Machine vote counting","Time-domain popcount cuts TM latency and power on FPGA","Asynchronous Tsetlin Machine uses delay lines for popcount","FPGA delay-based popcount: 38% less latency, 43% less power","Popcount via delay lines reduces Tsetlin Machine cost and time"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central claim stands or falls on whether manual placement, pin assignment, and routing can keep every delay element's short and long paths uniform enough that total PDL delay stays monotonic in Hamming weight across boards, voltage, and temperature.","fun_headline_variants_meta":{"raw":{"variants":["Delay lines replace adders in Tsetlin Machine vote counting","Time-domain popcount cuts TM latency and power on FPGA","Asynchronous Tsetlin Machine uses delay lines for popcount","FPGA delay-based popcount: 38% less latency, 43% less power","Popcount via delay lines reduces Tsetlin Machine cost and time"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00122,"raw_usage":{"total_tokens":5061,"prompt_tokens":1029,"completion_tokens":4032,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":645,"completion_tokens_details":{"reasoning_tokens":3940}},"tokens_in":645,"tokens_out":4032,"duration_ms":28941,"temperature":1.0,"reasoning_tokens":3940,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-16T00:59:14.094625+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a second FPGA of the same part, place the same PDL design, and measure propagation delay against Hamming weight over a range of supply voltages and temperatures; if the delay-weight curve stops being monotonic—rank correlation coefficient moving far from $-1$—or if a fixed classifier's accuracy drops below the trained baseline on the same inputs, the paper's central claim is refuted.","supporting_citations":[{"cited_title":"FPGA PUF using programmable delay lines,","cited_arxiv_id":null,"evidence_quote":"Supplies the basic LUT-based programmable delay line construction from arbiter PUF work that this design adapts to popcount."},{"cited_title":"Towards ideal arbiter PUF design on Xilinx FPGA: A practitioner’s perspective,","cited_arxiv_id":null,"evidence_quote":"Provides practitioner's placement and routing guidelines for symmetric PDLs on FPGAs that the design flow follows."},{"cited_title":"An asynchronous winner-takes-all arbitration architecture for Tsetlin machine acceleration,","cited_arxiv_id":null,"evidence_quote":"Prior proposal of PDL-based TM popcount with asynchronous arbitration, lacking physical implementation; this paper adds the FPGA design flow that makes it work."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Documents LUT physical pin delay differences (for example, A6 and A5 being fastest), used to assign low- and high-latency net pins."},{"cited_title":"Rapid FPGA characterization using clock synthesis and signal sparsity,","cited_arxiv_id":null,"evidence_quote":"Supplies the delay characterization method used to measure PDL propagation delay versus input Hamming weight."},{"cited_title":"MOUSETRAP: High-speed transition-signaling asyn- chronous pipelines,","cited_arxiv_id":null,"evidence_quote":"Provides the MOUSETRAP single-rail two-phase asynchronous pipeline template used for the TM datapath and controller."},{"cited_title":"FPGA architecture enhancements for efficient BNN implementation,","cited_arxiv_id":null,"evidence_quote":"Serves as the FPT'18 adder-based popcount baseline, reconstructed in a TM architecture and beaten on latency, power, and resources."},{"cited_title":"Self-timed reinforcement learning using tsetlin machine,","cited_arxiv_id":null,"evidence_quote":"Provides the ASYNC'21 dual-rail asynchronous TM baseline used for the resource-utilization comparison."}],"review_version":1}