{"id":"7b7c01fd-4580-45fa-9ab2-d80a7fd833da","arxiv_id":"2505.04069","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"An asynchronous SFQ up-down counter using Josephson Trapping Lines and alpha-cells is shown by simulation to operate over a [-4, +4] state range at 4 GHz.","lead":"This paper presents a clockless up-down counter built from superconducting single-flux-quantum circuits, using a new storage cell called a Josephson Trapping Line to hold pulses without a clock. A generalist might read it because reliable, energy-efficient counting is a basic building block for cryogenic computers, quantum control, and neuromorphic chips.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Read operation rests on an unverified Dec-before-Inc timing race; at the ±4 boundaries and at larger ranges the claimed correct behavior is not established.","rationale":"The reader's weakest assumption (the Dec-before-Inc race) is the same point I would stress. The paper's main evidence is a set of nominal JSIM waveforms, which are legitimate component-level and system-level demonstrations, but they do not bound the timing margin. SFQ junctions switch on picosecond scales, and the difference between the intended decrease-then-increase order and the destructive Inc-first order can be a small fraction of the 4 GHz period. The paper never quantifies this Δt window, and the scalability claim transfers the same unquantified race to longer chains of JTrLs and α-SPLs. I therefore keep the conditional verdict: the architecture is plausible, the simulations show nominal functionality, but the central claim of robust bidirectional operation is not yet established. Secondary issues—absence of a full netlist, lack of process-corner or thermal-noise analysis, and the read-at-zero caveat—reinforce the conditionality but are not the single load-bearing point. The concrete skew sweep would settle whether the timing race actually lands; if the allowed window is wide, the central claim is strengthened, and if it is narrow or negative, the design needs correction before acceptance.","tokens_in":8541,"tokens_out":9743,"duration_ms":108681,"concrete_test":"Run a skew sweep in JSIM on the complete Fig. 13 counter. Insert a controllable delay between the Modified Inc and Modified Dec pulses, define Δt = t_Inc − t_Dec, and for each initial state +1..+4 and -1..-4 vary Δt from -20 ps to +20 ps in 2 ps steps at a 4 GHz input rate. Record the output pulse count and the final stored state. If any Δt < 0 (Inc earlier) at state +4 or -4 changes the final state or output count, the asserted 'Dec earlier' margin is too small; quantify the allowed Δt window. Then repeat the same sweep after adding one more JTrL pair (range [-5,+5]) and check whether the allowed window changes; if it shrinks by more than a few ps, the scalability claim is not supported by the current simulation.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The load-bearing point is the timing assumption in §II-B1: 'Due to the symmetrical structure of the state circuit, Dec reaches the cell earlier than Inc.' The read operation is implemented by launching Modified Inc and Modified Dec pulses into the state circuit, and the intended decrease-then-increase sequence only works if Dec arrives first. This ordering is asserted, not derived from delay calculations, verified by SPICE margin sweeps, or supported by a timing analysis. It matters concretely: in state +4 the Inc path is already full, so if Inc arrives first it cannot be trapped and may be directed to the sink, corrupting both the read output and the stored state; the analogous failure exists at -4. The paper itself flags the zero-state version of this race: 'the outcome depends on which pulse triggers a junction first at the intermediate point of the data path.' Furthermore, the same unquantified race underlies the claimed scalability, since adding JTrLs and α-SPLs changes path delays and balance, yet only a single nominal configuration is simulated. Thus the central claim of robust 4 GHz bidirectional functionality is conditional on an unquantified skew margin.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes an asynchronous (clockless) up-down counter for single-flux quantum (SFQ) logic, using Josephson Trapping Lines (JTrLs) for persistent pulse storage and α-cells with splitters (α-SPL) for bidirectional, multi-fanout pulse propagation. The design includes a state circuit with four JTrLs for positive and four for negative states (range [-4,+4]) and a control unit composed of a state reader and a state updater. The state reader implements read by simultaneously applying Inc and Dec pulses, while the state updater handles output generation for Inc-in-negative and Dec-in-positive states. The correctness claims are supported by JSIM circuit simulations of the JTrL, α-SPL, state circuit, state reader, state updater, and the full counter at a nominal 4 GHz operating frequency. The authors further claim that the architecture scales to larger ranges by adding more JTrLs and α-SPLs.","tokens_in":8814,"tokens_out":4855,"duration_ms":48449,"significance":"If the reported functionality is robust, the counter offers a useful clockless building block for superconducting digital systems, avoiding clock distribution overhead and enabling persistent state storage. The paper's strengths are that it provides direct JSIM simulations of the integrated state circuit and control unit, that the trapping mechanism is experimentally grounded in the JTrL cell, and that the simulation does not rely on parameter fitting to match an external target. The architectural integration of α-SPL cells to achieve bidirectional propagation is also noteworthy. However, the validation is limited to nominal parameter values; no bias margins, process-variation analysis, or temperature sensitivity studies are reported, and the read operation relies on an unquantified timing skew. The scalability claim is currently supported only by a single 3-bit demonstration. These limitations prevent the current evidence from fully supporting the paper's 'robust' and 'scalable' claims, though the core idea remains plausible and worth revising.","major_comments":[{"comment":"The read operation is built on an unquantified timing assumption. The manuscript states 'Due to the symmetrical structure of the state circuit, Dec reaches the cell earlier than Inc,' but provides no delay calculation, SPICE-measured delay, or margin sweep for this skew. The ordering is load-bearing: in state +4, if the Inc pulse arrives before the Dec pulse, the Inc pulse cannot be trapped and may be directed to the sink, corrupting the read output and the stored state; an analogous failure exists at -4. Please provide a quantitative timing analysis and bias/process margin sweeps for the read path, or explicitly restrict the claimed operating conditions.","section":"II-B1"},{"comment":"The central claim of robustness is not supported by the reported simulations. All waveforms in Figs. 8-13 are nominal-parameter runs; the paper reports no bias margins, no Monte Carlo or process-variation analysis, and no sensitivity study of JTrL and α-SPL parameters. Bias margins are a standard validation requirement for SFQ circuits. Without them, the abstract's phrase 'robust bidirectional functionality' overstates what has been demonstrated; please add margin sweeps or temper the wording to 'functionality at nominal parameter values.'","section":"III"},{"comment":"The scalability claim that additional JTrLs and α-SPLs extend the counter range without increasing complexity is not substantiated by simulation. Only the 3-bit [-4,+4] configuration is demonstrated. Since the state-reader timing race depends on path delays that change as JTrLs are added, the extension to larger ranges requires either a simulation at a larger width (e.g., 4-bit) or a timing/load analysis showing that the Dec-before-Inc ordering is preserved. Please provide one such demonstration or restate the scalability claim as a design proposal rather than a validated property.","section":"IV"},{"comment":"The state updater is simulated only for the negative-state/Inc case (Fig. 12); the claimed symmetric behavior for Dec in positive states is not shown. Moreover, no exhaustive state-transition table or formal verification is provided for the full 9-state counter under all input combinations (Inc, Dec, Read). Given the abstract's statement that the control unit 'guarantees correct output behavior across all valid state transitions,' please either provide complete functional coverage results or replace the word 'guarantees' with a weaker claim consistent with the demonstrated evidence.","section":"II-B2"}],"minor_comments":[{"comment":"The read-at-zero restriction is a functional limitation: the text states 'The read signal should not be applied when the state is zero.' This should be disclosed in the abstract, since the design otherwise claims general read support.","section":"II-B1"},{"comment":"The caption of Fig. 4 says 'half of the JTLs and intermediate delay elements have been removed from the diagrams'; the text should specify which elements are omitted and how they are accounted for in simulation, otherwise the reader cannot reproduce the circuit.","section":"II-A"},{"comment":"The α-SPL behavior is described verbally ('A pulse from Input 1 generates output pulses at Output 1 and 3'), but the circuit-level parameters (bias currents, junction critical currents, inductances) for the α-SPL and for the state reader/updater cells are not reported, making the simulations difficult to reproduce. Please include a full parameter table.","section":"II-A"},{"comment":"The description of the JTrL simulation in Fig. 8 is contradictory: the text says 'the first Input 2 pulse is observed at Output 2' and later 'The Input 2 pulse at 275 ps does not produce an output.' Please clarify which pulses are trapped and which propagate, and whether these refer to the same or different Input 2 pulses.","section":"III"},{"comment":"There are typographical issues in the reference list, e.g., 'Sympsoium' in reference [2]; the JSIM citation [13] also appears to refer to a specific readout application rather than the JSIM simulator itself, so the reference should be corrected or expanded.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The paper would benefit from a standard SFQ validation flow, including bias margins and at least one larger counter configuration. The read-at-zero limitation is more than a minor caveat; it should be clearly stated in the abstract. The authors' prior work on α-cells and the Soma cell is cited, but the novelty of this integration should be positioned more clearly against existing SFQ counter designs."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First thing to know: this is a new circuit, not a repackaged one. The Josephson Trapping Line (a JTL with an enlarged SQUID loop that stores a circulating current) plus the α-SPL for bidirectional fanout add up to an asynchronous, clockless SFQ up-down counter. The paper simulates the integrated state circuit and control unit together, so the central claim is not curve-fit to an external target. That is real work.\n\nWhat it does well: the JTrL storage mechanism is plausible, and the simulations in Figs. 8–13 show the designed behavior for a [-4,+4] range at 4 GHz. The authors also flag the zero-state read ambiguity themselves, which is honest and correct: at zero, Inc and Dec meet with nothing stored, so the outcome is delay-dependent. The citation pattern is fine; the α-cell and JJ-Soma references are the authors’ own prior work, but they are used appropriately.\n\nThe soft spots are real and load-bearing. The read mechanism relies on Dec arriving before Inc when both are applied. The paper says this follows from symmetry. That is asserted, not derived or swept. If the order reverses at the ±4 boundaries, the read can corrupt the stored state. The same unquantified race is exactly what will change when you add more JTrLs and α-SPLs, so the “scalable” claim is currently a 3-bit extrapolation, not a demonstrated property. There are also no bias margins, Monte Carlo runs, or process-variation sweeps. “Robust” in the abstract is overstated; the evidence is nominal simulation only. Minor point: reference [13] does not appear to cite the JSIM simulator itself, which is worth checking.\n\nWho it is for: people working on SFQ state machines, cryogenic control for qubits, or neuromorphic SFQ will want to read this. It’s a building block, not a full system, and it is not ready to tape out.\n\nMy recommendation: the paper deserves serious peer review. A good referee will ask for margin analysis and an explicit timing budget for the read race, and ideally a demonstration at a larger range (even 5 bits would help). I would not desk-reject it.","headline":"A genuinely new asynchronous SFQ counter cell with credible nominal simulations, but the read mechanism rests on an unquantified timing race and 'robust' outruns the evidence.","tokens_in":9310,"tokens_out":3127,"would_cite":false,"duration_ms":30146,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims that a clockless SFQ up-down counter built from Josephson trapping lines and alpha-SPL cells correctly increments, decrements, and reads over a [-4, +4] state range at 4 GHz in circuit-level simulation.","keywords":["single flux quantum","SFQ logic","asynchronous counter","up-down counter","Josephson trapping line","persistent current storage","superconducting electronics","cryogenic digital logic"],"falsifier":"Apply simultaneous Inc and Dec while the count is +1 or -1 and sweep their relative arrival times, or run Monte Carlo variation of junction and inductor parameters; if any allowed skew makes Dec arrive after Inc, or makes the read produce the wrong count, the central functional claim fails.","tokens_in":8399,"feed_emoji":"🔢","tokens_out":5331,"duration_ms":53428,"temperature":0.7,"pith_summary":"This paper proposes an asynchronous, clockless up-down counter for single-flux-quantum (SFQ) superconducting logic. The central claim is that the counter, built from Josephson Trapping Lines and alpha-SPL cells, correctly executes increment, decrement, and read operations over the state range -4 to +4, including transitions that a plain state circuit cannot express on its own. The design matters because it removes the clocked storage elements normally used to hold counts and replaces them with persistent circulating currents that need no clock to remain stored. If the claim holds, superconducting digital systems gain a compact, scalable, event-driven counting primitive for qubit control, spiking neural networks, and cryogenic sensor readout.","feed_headline":"Clockless superconducting counter counts at 4 GHz","feed_subtitle":"A Josephson trapping line holds each count as persistent current, so up, down, and read need no clock signal.","key_machinery":"The load-bearing object is the Josephson Trapping Line (JTrL): a Josephson transmission line in which one SQUID loop has enlarged inductance so an incoming SFQ pulse settles into a persistent circulating current instead of propagating onward. That trapped current is the stored bit; a later pulse on the same side passes through unhindered, while a pulse from the opposite side annihilates the stored current and clears the cell. Around this cell, the paper assembles alpha-SPL lines (a splitter plus two alpha-cells) that route SFQ pulses bidirectionally with fan-out, an upper JTrL bank for negative states and a lower bank for positive states, and a control unit whose state reader performs a read by applying Inc and Dec simultaneously and whose state updater emits modified Inc and Dec signals when the bare state circuit would stay silent.","core_discovery":"The paper's discovery is a storage and counting mechanism: a Josephson Trapping Line (JTrL) is a Josephson transmission line whose storage SQUID loop has enlarged inductance, so the first SFQ pulse entering from the trapping side is captured as a persistent circulating current while subsequent pulses pass through, and a pulse entering from the opposite side annihilates that stored current and clears the cell. Wired together with alpha-SPL cells that propagate pulses bidirectionally and provide fan-out, banks of JTrLs form a state circuit whose trapped-pulse count is the counter value. The paper reports SPICE-level simulation of the complete architecture across the full [-4, +4] range at an operating frequency of 4 GHz, with a control unit supplying the increment, decrement, and read behavior the raw state circuit cannot produce by itself.","pith_inferences":["An implication left implicit is that the read-while-zero restriction forces surrounding control logic to track whether the counter is at zero separately, since applying a read at zero is explicitly described as unpredictable.","A testable extension would be a Monte Carlo sweep of junction critical currents and inductances: the Dec-before-Inc ordering that the read depends on is justified only by symmetry and has no stated timing margin.","If the JTrL's trapped current remains stable over long idle periods, the same cell could serve as a building block for nonvolatile SFQ memory or asynchronous state machines beyond counters.","At larger counter ranges the path through more alpha-SPLs and JTrLs may desynchronize the simultaneous Inc and Dec read pulses, so the scalability claim becomes a timing question rather than a wiring question."],"forward_implications":["An SFQ counter can hold its state without any clock tree, removing clock distribution area and power from superconducting digital layouts.","The counter range can be widened by appending more JTrLs and alpha-SPL cells, so the design offers a modular path to larger counters.","The persistent trapped current gives a storage element that can keep a count between operations without refreshing, effectively nonvolatile within cryogenic operation.","The read operation produces no output at state zero and is declared unpredictable there, so surrounding control logic must know that zero is not a readable state.","Because the full counter was verified only in circuit simulation at 4 GHz, the concrete claim to check in hardware is correct bidirectional behavior across the full state range."],"supporting_citations":[{"why":"Establishes the RSFQ logic/memory family and the clocked storage baseline that this design replaces.","marker":"[7]"},{"why":"Supplies the energy-efficient SFQ technology context and clocking conventions the counter avoids.","marker":"[9]"},{"why":"Presents a prior 8-bit SFQ up-down counter for flux digitization, the bidirectional counting problem this work extends.","marker":"[10]"},{"why":"Shows a high-speed SFQ up/down counter for stochastic neural computation, a direct prior bidirectional counter.","marker":"[11]"},{"why":"Introduces binary up-down counters in AQFP logic, the alternative superconducting technology compared.","marker":"[12]"},{"why":"Provides the simulation environment in which all component and full-counter waveforms were produced.","marker":"[13]"},{"why":"Defines the JJ-Soma threshold cell reused in the state updater to detect state amplitude greater than one.","marker":"[14]"}],"fun_headline_variants":["Clockless superconducting up-down counter runs at 4 GHz","No-clock counter stores state as persistent current","Trapped pulses count up and down at 4 GHz","Josephson trapping lines make clockless counters"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that during a read, the Dec pulse always reaches the storage cell before the Inc pulse; the paper supports this only by saying the structure is symmetric, without quantifying a timing margin or simulating parameter variations.","fun_headline_variants_meta":{"raw":{"variants":["Clockless superconducting up-down counter runs at 4 GHz","No-clock counter stores state as persistent current","Trapped pulses count up and down at 4 GHz","Josephson trapping lines make clockless counters"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000182,"raw_usage":{"total_tokens":1282,"prompt_tokens":888,"completion_tokens":394,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":504,"completion_tokens_details":{"reasoning_tokens":333}},"tokens_in":504,"tokens_out":394,"duration_ms":4562,"temperature":1.0,"reasoning_tokens":333,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T23:38:32.096885+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Apply simultaneous Inc and Dec while the count is +1 or -1 and sweep their relative arrival times, or run Monte Carlo variation of junction and inductor parameters; if any allowed skew makes Dec arrive after Inc, or makes the read produce the wrong count, the central functional claim fails.","supporting_citations":[{"cited_title":"RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,","cited_arxiv_id":null,"evidence_quote":"Establishes the RSFQ logic/memory family and the clocked storage baseline that this design replaces."},{"cited_title":"Energy-Efficient Single Flux Quantum Technology,","cited_arxiv_id":null,"evidence_quote":"Supplies the energy-efficient SFQ technology context and clocking conventions the counter avoids."},{"cited_title":"Design of Digital DROS With SFQ Up/Down Counter for Wide Dynamic Operation Range,","cited_arxiv_id":null,"evidence_quote":"Presents a prior 8-bit SFQ up-down counter for flux digitization, the bidirectional counting problem this work extends."},{"cited_title":"Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural ComputationUs- ing Stochastic Logic,","cited_arxiv_id":null,"evidence_quote":"Shows a high-speed SFQ up/down counter for stochastic neural computation, a direct prior bidirectional counter."},{"cited_title":"Binary Counters Using Adi- abatic Quantum-Flux-Parametron Logic,","cited_arxiv_id":null,"evidence_quote":"Introduces binary up-down counters in AQFP logic, the alternative superconducting technology compared."},{"cited_title":"Current Resolution of a Single-Flux-Quantum Readout Circuit Based on Current- to-Time Conversion Toward a Flux Qubit System,","cited_arxiv_id":null,"evidence_quote":"Provides the simulation environment in which all component and full-counter waveforms were produced."},{"cited_title":"JJ-Soma: Toward a spiking neuromorphic processor architecture,","cited_arxiv_id":null,"evidence_quote":"Defines the JJ-Soma threshold cell reused in the state updater to detect state amplitude greater than one."}],"review_version":1}