{"id":"6b074799-abb3-4fd8-9342-cc0b03fa4f1e","arxiv_id":"2505.04337","paper_version":3,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"CMOS-compatible, 200 mm wafer fabrication of 24-qubit chips with flip-chip bonding via KOH-etched Si-island microbumps yields functional qubits with T1 up to 15 µs.","lead":"This paper shows superconducting qubits built on large silicon wafers using industry-standard chip manufacturing, then connected to a second chip with tiny solder-free bumps. The work suggests quantum processors could be mass-produced in existing semiconductor factories, with early qubits running for about 15 microseconds.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 'negligible added loss' claim is unsupported and in tension with the residual 20 Ω DC resistance: a series 20 Ω element alone gives ~1.6 dB insertion loss.","rationale":"The reader's weakest assumption matches the point I would stress: the low-loss claim for the microbump rests on a qualitative comparison rather than a quantitative reference, and the DC measurement already signals that the bump stack is not fully superconducting. This concern is load-bearing because the microbump's RF transparency is the distinguishing technical contribution; if the residual 20 Ω were truly in series, the abstract's 'negligible attenuation' would be false. However, the paper is a proof-of-concept and provides independent evidence that the assembled devices actually work: 29/31 qubits show spectroscopy signatures, T1 reaches 15 µs, and S21 appears low on the plotted scale. These observations make the residual resistance likely a localized interface effect rather than a fatal design flaw, but they do not by themselves quantify the bump loss. The issue is addressable with a reference device, so I would keep the verdict at CONDITIONAL rather than accept or reject. The required repair is modest: show a direct S21 comparison with and without bumps, or provide a model converting the DC residual into an RF-loss bound and verify that bound experimentally.","tokens_in":9124,"tokens_out":6468,"duration_ms":69052,"concrete_test":"Measure S21 of a second feedline on the same qubit wafer before flip-chip bonding, or of a carrier-chip through that bypasses the bumps, using the same cryogenic SOLT calibration; then measure S21 of the flip-chip assembly and report the difference across 4-8 GHz. The 'no additional insertion loss' claim survives only if the added loss is below about 0.1 dB. As a cross-check, convert the measured low-temperature residual resistance into an expected series-loss bound via S21,dB = 20log10(2Z0/(2Z0+R)); if the assembly's S21 is compatible with R ≈ 20 Ω, the bump path is not negligible, and if it is not compatible, identify the shunting mechanism that removes the resistance from the RF path.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central novelty is that the Si-island microbump is both superconducting and low-loss at RF. The paper's support is Sec. V.A/Fig. 4b, a calibrated S21 whose trace is visually 'comparable to standard planar CPW signal lines,' with no reference trace, no loss-per-length fit, and no error budget. This is directly undercut by the paper's own Fig. 4a and conclusion, which acknowledge 'no full superconductivity of the bumps' and a residual ~20 Ω at 10 mK, attributed to TiN or interface oxides in the signal path. If that resistance is in series in the 50 Ω line, the expected insertion loss is 20log10(2Z0/(2Z0+R)) ≈ -1.6 dB, not a negligible effect. It is possible the TiN layer is shunted at RF by the superconducting In/Al overlaps, or that the 20 Ω lies outside the RF current path, but the paper does not demonstrate this; the qualitative S21 comparison cannot distinguish a small bump loss from a ~1-2 dB series loss. Because the 'negligible attenuation' statement is an explicit abstract claim, this is the load-bearing point that needs a quantitative check before the flip-chip interconnect claim can be accepted.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports a proof-of-concept development of superconducting transmon qubits fabricated on 200 mm wafers using CMOS-line equipment with subtractive patterning of Al/AlOx/Al Josephson junctions, and 3D-integrated to a carrier chip via flip-chip bonding using metallized KOH-etched Si-island microbumps. DC measurements of the bump/feedline path show superconducting transitions of Nb, In, and Al but a residual ~20 Ω at 10 mK; calibrated S21 measurements are claimed to show transmission comparable to planar CPW with negligible added loss. In qubit characterization across six feedlines on four assemblies, 29/31 qubit-resonator pairs showed one- and two-tone spectroscopy signatures, with T1 up to 15 μs and T2* up to 17 μs.","tokens_in":9339,"tokens_out":5761,"duration_ms":57816,"significance":"If the quantitative claims were fully supported, the work would be of practical significance: it demonstrates that industry-style 200 mm wafer processing and flip-chip integration can produce functional transmon qubits in a first run, with a path toward large-area grounding and signal routing without airbridges. The strengths are the direct measurements of a complete integrated device, the explicit reporting of yield statistics (31/36 resonators, 29/31 qubits), and the transparent statement that full superconductivity of the bump path was not achieved. The paper is a process/technology demonstration rather than a coherence-optimization study; T1 ~15 μs is modest compared to state-of-the-art planar qubits but reasonable for a first integrated run. The central claims are direct measurements; there is no fitted derivation, and the reliance on companion papers for design details does not create circularity.","major_comments":[{"comment":"The abstract claim that 'the microbump connection in the signal chain is not introducing additional insertion loss' is not quantitatively established. The DC measurement in Fig. 4a shows a residual resistance of about 20 Ω at 10 mK, and Sec. VI concedes that full superconductivity of the bump path was not reached. If this residual resistance were in series in the 50 Ω feedline, it alone would produce roughly 20log10(2Z0/(2Z0+R)) ≈ -1.6 dB of insertion loss, which is not negligible at the level claimed. The S21 trace in Fig. 4b is compared only qualitatively to \"standard planar CPW signal lines,\" with no reference trace on the same chip, no loss-per-length or equivalent-circuit fit, and no stated error or reproducibility. Because the low-loss RF interconnect is the principal novelty of the bump technology, this point must be supported by a quantitative check, e.g., a direct comparison with a reference planar CPW line of the same length on the same carrier, or a model using the measured residual resistance and surface impedance that reproduces the S21.","section":"Sec. V.A, Fig. 4; Sec. VI"},{"comment":"The 'high yield' claim is based on measurements of six feedlines on four assemblies that were chosen for wire-bonding and mounting. The paper does not state the selection criterion, the total number of bonded devices produced, or how many devices failed before measurement. Without that information, the reported 29/31 qubit yield cannot be interpreted as a process yield or representative yield; it may reflect a favorable subset. Please report the selection procedure and, if possible, statistics over a larger set of devices, or weaken the claim to 'in the measured devices.'","section":"Sec. V.B and Abstract"}],"minor_comments":[{"comment":"The first sentence contains a typo: \"multiple advantages ... the make it\" should read \"that make it.\"","section":"Sec. I"},{"comment":"The shaded region in Fig. 4b is described as \"the relevant frequency range of 4–8 GHz\" in the text, but the figure caption does not define it, and the expected baseline insertion loss for a planar CPW line of the same length is not given; please add this information to make the comparison concrete.","section":"Sec. V.A, Fig. 4b"},{"comment":"The description of the TiN/In lift-off processing is somewhat ambiguous: the text says the resist is exposed again by i-line stepper lithography and then states that the lift-off resist is exposed to ion bombardment; please clarify whether the same resist layer is used and how the surface preparation avoids degrading the lift-off profile.","section":"Sec. III.A"},{"comment":"The phrase \"time-domain spectroscopy\" is non-standard for pulsed T1 and T2* measurements; consider using \"time-domain measurements\" or \"pulsed qubit characterization.\"","section":"Sec. V.B"},{"comment":"Essential design and process details are delegated to companion papers [13] and [16]; since the main claims should be assessable from the present manuscript, please include the key circuit parameters (qubit frequencies, anharmonicities, and feedline/resonator geometry) in the main text or supplement.","section":"Refs. [13] and [16]"}],"recommendation":"major_revision","confidential_remarks":"The manuscript relies substantially on companion papers [13] and [16] for chip design and process details; the editors may wish to confirm that these references are publicly available. The title's 'CMOS-Compatible' claim should be interpreted carefully, because the Nb and In processing is done outside the CMOS line; this is not a basis for rejection but should be clarified in revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Dear Colleague,\n\nThis is a credible engineering proof-of-concept, and the main thing to know is that the Si-island microbump process is genuinely new, but the paper's headline claim that the bump adds negligible RF loss is not actually demonstrated and may be in tension with its own DC data.\n\nWhat is new: they show a full 200 mm CMOS-compatible process for both qubit and carrier wafers, with KOH-etched Si islands metallized with Nb/In on the carrier and TiN/In pads on the qubit chip. That specific microbump geometry and the foundry-style subtractive JJ etch are real contributions. They also demonstrate flip-chip bonding at 200 mm scale, RF transfer through the bumps, and qubit operation: 29 of 31 possible qubits showed spectroscopy signatures, with T1 up to 15 µs and T2* about 17 µs. For a first processing run that is meaningful.\n\nThe soft spot, and it is load-bearing, is the loss claim. Figure 4a shows a residual ~20 Ω DC resistance at 10 mK, and the conclusion concedes that full superconductivity of the bumps was not observed. If that resistance is in series with the 50 Ω line, it alone gives about 1.6 dB insertion loss, which is not 'negligible.' The S21 measurement in Fig. 4b is compared qualitatively to 'standard planar CPW' with no reference trace, no noise floor, and no error budget. So the mechanism that would make the 20 Ω harmless (e.g., shunting by superconducting overlaps, or the resistance being outside the RF current path) is plausible but not shown.\n\nThere are two smaller issues. Coherence numbers are single maxima, not statistics, so the 'up to 15 µs' should not be read as representative. And parts of the circuit design and modelling are deferred to the authors' own companion papers, which is fine for a technology letter but weakens self-containedness. The citation pattern otherwise looks appropriate, building on Rosenberg, Yost, Foxen, and the 300 mm CMOS work from imec.\n\nNone of this invalidates the core demonstration. The paper is honest about the open interface problem, and the fabrication story is credible. What it needs before the loss claim is accepted is a quantitative comparison: a reference CPW line measured in the same setup, or an estimate of the expected loss from the residual resistance.\n\nFor a reader working on flip-chip or CMOS-based qubit integration, this is worth a careful read and a serious referee. I would send it to review with a request for that quantitative loss analysis rather than desk-rejecting.\n\nRegards","headline":"A credible 200 mm CMOS-compatible flip-chip qubit process with a genuinely new Si-island microbump technology, but the 'negligible loss' claim is not quantitatively supported and may conflict with the residual 20 Ω DC resistance.","tokens_in":9992,"tokens_out":2466,"would_cite":true,"duration_ms":23751,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Working superconducting qubits made with CMOS-compatible, 200 mm wafer processing and connected by a new Si-island microbump that transfers control signals with negligible added loss.","keywords":["superconducting qubits","flip-chip bonding","3D integration","CMOS-compatible fabrication","microbumps","wafer-scale processing","transmon","coherence time"],"falsifier":"In the same cooldown and with the same calibration, measure the S21 of a flip-chip feedline and a co-fabricated planar CPW through-line of identical length; if the flip-chip path drops by more than a few tenths of a dB relative to the planar reference, the claim of negligible added loss fails. A time-domain reflectometry trace that shows a discrete reflection at the bump would also falsify it.","tokens_in":8920,"feed_emoji":"⚛️","tokens_out":5304,"duration_ms":51047,"temperature":0.7,"pith_summary":"This paper demonstrates that superconducting qubits can be fabricated entirely in a CMOS-compatible, 200 mm wafer process using subtractive etching, then 3D-integrated by flipping the chip onto a carrier and connecting them with tiny metallized silicon-island bumps. The authors report that the bump connection is superconducting in its metal stacks, that radio-frequency signals pass through it with no measurable extra loss, and that 29 out of 31 tested qubit/resonator pairs showed working qubit signatures with energy relaxation times up to 15 microseconds. If this holds, it opens a route to making quantum processors on the same large-wafer infrastructure that produces conventional computer chips, while also providing the chip-to-chip wiring that larger, modular quantum processors will need.","feed_headline":"Flip-chip qubits on 200 mm CMOS wafers reach 15 µs lifetimes","feed_subtitle":"A Si-island microbump carries control signals between chips with negligible added loss, enabling scalable multi-chip quantum processors.","key_machinery":"The central object is the Si-island microbump: a KOH-etched silicon pillar on the carrier chip, metallized with a Nb/In stack, that bonds to a TiN/In pad on the qubit chip. The silicon island sets a precise, reproducible chip-to-chip spacing while providing both a dense grid of grounding connections and the two RF signal connections at the ends of each feedline. The second load-bearing element is the all-subtractive Josephson junction process, which replaces double-angle evaporation and lift-off with two optical lithography layers and dry etching, making the qubit fabrication compatible with CMOS contamination rules and 200 mm tooling.","core_discovery":"The paper claims that a proof-of-concept device hosting 24 fixed-frequency transmons on a 12.3 mm qubit chip, flip-chip bonded to a 14.3 mm carrier chip, works as a functional 3D-integrated superconducting quantum processor. The qubit chip and carrier are fabricated on separate 200 mm wafers using industry-style, subtractive processing (including an all-dry-etched aluminum Josephson junction instead of shadow-mask lift-off), and the connection between chips is made by an array of Si-island microbumps with Nb/In on the carrier side and TiN/In pads on the qubit side. Measurements show the bumps become superconducting with transitions near the expected critical temperatures, RF transmission through the bump-connected feedline is comparable to standard planar coplanar waveguide lines, and of 31 measurable resonator/qubit pairs, 29 produce clear qubit signatures, with T1 up to 15 µs and T2* up to 17 µs.","pith_inferences":["A quantitative S21 comparison against a calibrated on-chip reference line would settle whether the unquantified 'negligible attenuation' claim holds; the paper's current evidence is suggestive but not metrological.","If the roughly 20 Ω residual DC resistance arises from a thin normal-metallic TiN layer, its effect could be frequency- or power-dependent and may show up in resonator quality factors at higher drive powers, which the present measurements do not resolve.","The Si-island gap-control technique could transfer to other multi-chip platforms, such as spin-qubit or photonic modules, that need accurate and reproducible die-to-die spacing.","A direct test of the claim that the bumps eliminate the need for airbridges would be to compare coherence on the same chip layout with and without additional wirebond or airbridge grounding."],"forward_implications":["Qubit production can move onto the same 200 mm lithography, etch, and deposition tools used for conventional CMOS chips, improving wafer-scale uniformity and repeatability.","The microbump interconnect can replace airbridges for uniform grounding and can route control signals across chip boundaries, enabling signal crossings in complex QPU layouts.","With 151 qubit chips per wafer and 119 carrier chips per wafer, the process is directly compatible with modular, chiplet-style quantum processors in which several qubit dies are bonded to one carrier.","The reported coherence times come from the very first processing run, so subsequent runs should improve as the microbump metallurgy and interfaces are optimized."],"supporting_citations":[{"why":"Shows that CMOS-line manufacturing of superconducting qubits on 300 mm wafers is possible, establishing the baseline this work extends to 3D integration.","marker":"[8]"},{"why":"Reports manufacturable superconducting qubits with relaxation times exceeding 0.1 ms, defining the performance target for industry-style fabrication.","marker":"[9]"},{"why":"Prior demonstration of 3D integrated superconducting qubits that motivates the flip-chip architecture used here.","marker":"[10]"},{"why":"Companion paper describing the circuit design and modelling of this multifloating-qubit flip-chip platform with TLS-loss mitigation.","marker":"[13]"},{"why":"Companion work reporting the planar CMOS-compatible qubit processing and room-temperature characterization that underlies the fabrication.","marker":"[16]"},{"why":"Demonstrates low-loss interconnects for modular superconducting processors, the alternative approach this microbump technology competes with.","marker":"[19]"}],"fun_headline_variants":["Flip-chip qubits on 200 mm CMOS wafers hit 15 µs T1","Wafer-scale 3D qubits: 29/31 measurable pairs, T1 up to 15 µs","Superconducting Si-island bumps link chips, qubits endure 15 µs","All-dry-etched qubits flip-chip bonded, CMOS flow, T1=15 µs"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim that the microbump adds negligible RF loss rests on a qualitative comparison of the measured transmission to standard planar lines, while DC measurements show about 20 ohms of residual resistance in the bump path at base temperature; if that residual resistance causes appreciable insertion loss at the 4-8 GHz operating band, the central claim about the interconnect weakens.","fun_headline_variants_meta":{"raw":{"variants":["Flip-chip qubits on 200 mm CMOS wafers hit 15 µs T1","Wafer-scale 3D qubits: 29/31 measurable pairs, T1 up to 15 µs","Superconducting Si-island bumps link chips, qubits endure 15 µs","All-dry-etched qubits flip-chip bonded, CMOS flow, T1=15 µs"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000727,"raw_usage":{"total_tokens":3224,"prompt_tokens":877,"completion_tokens":2347,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":493,"completion_tokens_details":{"reasoning_tokens":2244}},"tokens_in":493,"tokens_out":2347,"duration_ms":15610,"temperature":1.0,"reasoning_tokens":2244,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T23:31:03.620074+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"In the same cooldown and with the same calibration, measure the S21 of a flip-chip feedline and a co-fabricated planar CPW through-line of identical length; if the flip-chip path drops by more than a few tenths of a dB relative to the planar reference, the claim of negligible added loss fails. A time-domain reflectometry trace that shows a discrete reflection at the bump would also falsify it.","supporting_citations":[{"cited_title":"Van Damme, S","cited_arxiv_id":null,"evidence_quote":"Shows that CMOS-line manufacturing of superconducting qubits on 300 mm wafers is possible, establishing the baseline this work extends to 3D integration."},{"cited_title":"Verjauw, R","cited_arxiv_id":null,"evidence_quote":"Reports manufacturable superconducting qubits with relaxation times exceeding 0.1 ms, defining the performance target for industry-style fabrication."},{"cited_title":"Rosenberg, D","cited_arxiv_id":null,"evidence_quote":"Prior demonstration of 3D integrated superconducting qubits that motivates the flip-chip architecture used here."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Companion paper describing the circuit design and modelling of this multifloating-qubit flip-chip platform with TLS-loss mitigation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Companion work reporting the planar CMOS-compatible qubit processing and room-temperature characterization that underlies the fabrication."}],"review_version":1}