{"id":"5d368132-8b28-45bb-818a-443778d9bc64","arxiv_id":"2505.07490","paper_version":3,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Ternary neural networks on RRAM crossbars are more resilient to wire parasitics and low-resolution ADCs than binary networks, at a 40% energy efficiency cost.","lead":"This paper builds simulation tools for RRAM-based compute-in-memory accelerators, modeling how wire resistance and ADC precision affect accuracy and energy. It finds ternary neural networks tolerate these imperfections better than binary ones, but use about 40% more energy per operation.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 40% TNN energy-efficiency penalty is not derivable from the printed energy model: Eq. 9 cancels the two-cycle overhead it is said to cause.","rationale":"The reader's weakest assumption was the missing SPICE validation of Algorithm 1. That is a legitimate reproducibility concern, but the more load-bearing issue is internal: the energy model equation cannot produce the paper's key quantitative result without an unstated change in the MAC-count convention. The parasitics claim (TNNs more resilient) is qualitatively robust to model details and is supported by a plausible sparsity mechanism, so it is not the main risk. The ADC calibration result is also a separate contribution that does not depend heavily on the contested energy equation. However, the 40% energy-efficiency figure is one of the three headline findings and is directly attributed to the two-cycle overhead. Eq. 9 cancels that overhead, so the paper's own derivation contradicts its stated explanation. This is not a disagreement with consensus; it is an internal consistency check that fails as written. The concern is concrete and testable: rerunning the energy calculation with a transparent definition of O_t and x_t, and without dividing out the two-cycle factor inappropriately, would settle whether the 40% result holds. I therefore keep the verdict conditional rather than rejecting outright, because a corrected formula may restore the qualitative conclusion. The reader's conditional verdict stands, but for a different and sharper reason than the one identified.","tokens_in":9124,"tokens_out":11497,"duration_ms":119818,"concrete_test":"Recompute the TNN energy efficiency from Eq. 8 using the physically correct MAC count: for each full MVM, MACs = N_t M_t, and E_TNN = 2*(N_t x_t^+ E_RD + M_t E_ADC + N_t M_t x_t^+ g_t V_R^2 T_R) with x_t^+ equal to the per-cycle active-input fraction (about 1/3 for balanced ternary). Compare the resulting TNN/BNN energy ratio to the 40% penalty in Fig. 5. Also recompute with the printed Eq. 9, setting O_TNN = 2 and O_BNN = 1, to verify whether the cancellation removes the penalty entirely. If the corrected ratio is not approximately 0.6, the stated energy model does not generate the headline result.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The quantitative core of the central claim is the 40% energy-efficiency penalty for TNNs (Section IV-F, Fig. 5), but the energy model as written does not produce this result. Eq. 8 gives tile energy E_t = O_t (N_t x_t E_RD + M_t E_ADC + N_t M_t x_t g_t V_R^2 T_R), and Eq. 9 divides by O_t N_t M_t to obtain E_MAC = x_t E_RD/M_t + E_ADC/N_t + x_t g_t V_R^2 T_R. The factor O_t cancels. If O_t is the number of MVM cycles (1 for B-I/B-II, 2 for T-I/T-II, Table I), then the two-cycle overhead invoked in Section IV-F is divided out of the energy per MAC, and with per-cycle x_t around 1/3 for TNN versus 1/2 for BNN, Eq. 9 predicts TNN is more efficient on row-driver and cell terms and equal on ADC, not 40% less efficient. If instead O_t is the number of full MVM operations and x_t is averaged over both TNN cycles, Eq. 9 still omits the second ADC conversion: a T-I MVM performs 2*M_t ADC conversions per full dot product, but only M_t E_ADC appears. Reproducing the claimed 40% penalty requires either a denominator of N_t M_t rather than O_t N_t M_t, or an explicit factor 2 in the numerator for TNN. Neither is present. Since the 40% headline is computed directly from this model, the central quantitative claim is currently an artifact of an ambiguous or misstated equation rather than a demonstrated result.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents simulation models for evaluating RRAM-based compute-in-memory (CIM) accelerators running binary and ternary CNN workloads. The authors propose a vectorized algorithm (Algorithm 1) for computing crossbar output currents under resistive wire parasitics, claiming a maximum error below 0.15% against SPICE. They also propose an ADC calibration method with a layer-wise scale parameter and a statistics-based energy model. Using these components, they compare binary neural networks (BNNs) and ternary neural networks (TNNs) on LeNet-5 and VGG-7, concluding that TNNs are more resilient to wire parasitics, require lower ADC resolution (4 bits with calibration), but suffer a 40% reduction in energy efficiency. The paper is an extended simulation study with no hardware measurements.","tokens_in":9422,"tokens_out":5933,"duration_ms":56006,"significance":"If the energy-efficiency and resilience comparisons are correct, the paper provides useful design guidance for RRAM-based CIM accelerators, particularly the finding that operand sparsity in TNNs helps tolerate wire parasitics and coarse ADC quantization. The vectorized parasitics solver and the ADC calibration scheme are practical contributions that could be reused by other groups. The quantitative headline, however, is currently compromised by an inconsistency in the printed energy model: the two-cycle overhead for TNNs cancels out of Eq. (9), so the reported 40% energy-efficiency penalty is not derivable from the equations as written. The paper also omits the SPICE verification details behind the 0.15% error claim and reports no error bars or seeds. These issues are fixable with additional text and a corrected derivation, so the central methodology remains defensible.","major_comments":[{"comment":"The printed energy model cannot produce the claimed 40% energy-efficiency penalty for TNNs. Equation (8) defines E_t = O_t (N_t x_t E_RD + M_t E_ADC + N_t M_t x_t g_t V_R^2 T_R), and Eq. (9) divides by O_t N_t M_t to obtain E_MAC = x_t E_RD/M_t + E_ADC/N_t + x_t g_t V_R^2 T_R. The factor O_t cancels, so the number of MVM cycles per operation does not enter the per-MAC energy. If O_t counts full MVM operations, then T-I/T-II require two cycles per operation and Eq. (8) must have a factor of two in all three bracketed terms; if O_t counts cycles, then the total number of MACs for a ternary tile is O_t N_t M_t/2 and the denominator in Eq. (9) overcounts by a factor of two. Under either reading, the sentence in Section IV-F that the two dot-product cycles 'decrease overall energy efficiency' is not derivable from the model as printed. The 40% headline therefore needs a corrected cycle-counting equation and a recomputation before it can be accepted.","section":"Section III-C, Eqs. (8)-(9) and Section IV-F"},{"comment":"The claim that Algorithm 1 computes output currents with a maximum error of 0.15% compared to SPICE is unsupported in the manuscript. There is no netlist description, no specification of the tested crossbar sizes, parasitic resistance ranges, or conductance values, and no list of comparison points. Since the parasitics-resilience comparison in Fig. 3 rests on the correctness of this circuit model, the authors should either add an appendix with the SPICE setup and the error-vs-configuration data or provide the verification scripts. This is a reproducibility gap, not necessarily an error, but it is load-bearing for the wire-parasitics claims.","section":"Section III-A"},{"comment":"All quantitative comparisons are single point estimates: 200 images are used for profiling, 100 for accuracy evaluation, and no random seeds or confidence intervals are reported for either the accuracy curves or the energy-efficiency numbers. Because the ADC-calibration scale s_l is fit to the profiling histograms, the reported 4-bit result and the TNN-vs-BNN gaps could vary with the calibration set; reporting variance over seeds or bootstraps would strengthen the three central claims.","section":"Section IV-C/D/E/F"}],"minor_comments":[{"comment":"The sentence 'a high number of active colums Nt is important to amortise the elevated energy cost of ADC conversions' should read 'active rows N_t'; the ADC energy term E_ADC/N_t is amortized by the number of rows per column, not columns, and the word 'colums' is misspelled.","section":"Section III-C, after Eq. (9)"},{"comment":"The text says 'the iteration loop (lines 5-7)' but the loop in Algorithm 1 spans lines 4-6; please correct the line reference.","section":"Section III-A, Algorithm 1"},{"comment":"Fig. 5 reports energy efficiency for B-I and T-I only, while Figs. 3 and 4 include all four encoding schemes; a sentence explaining the omission of B-II and T-II from the energy comparison would help.","section":"Section IV-F, Fig. 5"},{"comment":"The profiling uses 200 images and the accuracy evaluation uses 100 images; please clarify whether these are disjoint image sets and whether the same test images are reused across experiments.","section":"Section IV-C and IV-D"}],"recommendation":"major_revision","confidential_remarks":"The energy-model issue is fixable with a corrected denominator or an explicit factor for the two-cycle ternary operations, but the authors must recompute the energy-efficiency comparison after that correction; the 40% penalty could become smaller, larger, or reverse depending on the correct counting. I would not reject outright because the parasitics solver and ADC calibration methodology are useful and the resilience claim does not depend on the energy model. The lack of SPICE details and error bars should be addressed in revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is a working paper with a real contribution - the vectorized parasitic solver and the calibration method do what they claim, and the finding that TNNs tolerate parasitics and low ADC resolution better than BNNs is plausible and well-supported by the accuracy experiments. The problem is the headline energy number. Eq. 8 defines tile energy as O_t times a per-cycle term. Eq. 9 divides by O_t N_t M_t to get per-MAC energy. If O_t is the number of cycles (1 for BNN, 2 for TNN), it cancels, so the two-cycle overhead the text credits for the TNN penalty is divided out. If O_t is meant to be the number of full MVM operations, then the per-cycle term has to be multiplied by the cycle count, and the T-I case still omits the second ADC conversion. Either way, the printed equations do not produce a 40% penalty. You need an explicit denominator of N_t M_t or a factor 2 in the numerator for ternary mappings. The stress-test note got this right, and it is a load-bearing flaw for Section IV-F and the abstract.\n\nWhat is genuinely new and good: the vectorized conductance-reduction solver (Algorithm 1) is a clever alternative to CrossSim, and the layer-wise ADC scale calibration (Eq. 6-7) convincingly shows 4-bit ADCs suffice with negligible accuracy loss across the two networks. The parasitics resilience comparison (Fig. 3) is the strongest part: the qualitative trend survives the model details, and the mechanism - operand sparsity - is independently observable, not an artifact. The authors also did the honest thing by using external energy parameters for the ADC and row drivers.\n\nSoft spots beyond the energy model: the SPICE validation behind the 0.15% error claim is not shown (no netlist, no comparison points), there is no released code or data, no error bars or seeds for the accuracy or energy numbers, and the workload set is two networks. The 'active columns' typo in the discussion of Eq. 9 is minor but confusing. None of these would worry me much if the energy model were fixed.\n\nBottom line: the framework and the parasitics/ADC results are worth a serious referee. The energy-efficiency headline needs to be reworked or heavily qualified. If that is done, the paper would be a solid systems contribution. If it is not, the abstract overclaims.","headline":"Useful simulation framework and a genuinely interesting TNN-vs-BNN robustness result, but the central 40% energy-efficiency penalty is not derivable from the printed energy model.","tokens_in":10025,"tokens_out":4047,"would_cite":false,"duration_ms":36089,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Ternary neural networks tolerate wire resistance and low ADC resolution on RRAM crossbars better than binary ones, but use about 40% more energy per MAC.","keywords":["compute-in-memory","RRAM crossbar","wire parasitics","ADC resolution","binary neural networks","ternary neural networks","calibration","energy efficiency"],"falsifier":"Reproduce the SPICE validation of Algorithm 1 with a complete 1T1R netlist using the same LRS/HRS values and wire-resistance sweep; if the output-current error exceeds 0.15% or the accuracy-vs-$R_p$ curves shift enough to change the TNN-vs-BNN ordering, the central claim is unsupported.","tokens_in":8886,"feed_emoji":"🧠","tokens_out":7765,"duration_ms":65440,"temperature":0.7,"pith_summary":"Ternary neural networks, whose weights and activations take values in {-1,0,1}, are more tolerant than binary networks to the two main scalability limits of RRAM-based compute-in-memory accelerators: resistive wire parasitics inside the crossbar and coarse analog-to-digital conversion. To support this claim, the paper builds a fast vectorised solver for crossbar output currents, a layer-wise ADC calibration rule, and a statistics-based energy model, then compares binary and ternary versions of two CNN workloads across five memristive technologies. The intended upshot is a practical design trade: ternary networks pay about 40% more energy per MAC, but they can use larger crossbars and 4-bit ADCs without losing baseline accuracy. If these models are right, accelerator designers should weigh input sparsity, not just weight precision, when choosing a quantization scheme.","feed_headline":"Ternary nets beat binary on RRAM wire and ADC limits","feed_subtitle":"Sparse ternary inputs tolerate parasitic resistance and 4-bit ADCs, but cost 40% more energy per MAC.","key_machinery":"The load-bearing mechanism is Algorithm 1, a vectorised iterative conductance-reduction solver for 1T1R crossbars with resistive wires. It treats each column as a chain of parallel/series conductance combinations with the parasitic wire conductance $g_{wire}=1/R_p$, updating each column's effective conductance by $g_{per col} \\leftarrow (g_{per col}+g_{row})\\,g_{wire}/(g_{per col}+g_{row}+g_{wire})$ for every active row, then reading the output current as $g_{per col} V_{read}$. Because the iteration runs for all columns simultaneously using SIMD operations, it is fast enough for design-space sweeps and is the basis for the parasitics resilience comparison. The other two pieces are the ADC calibration rule of Eq. (6) (choose the layer scale so the $\\mu \\pm 3\\sigma$ output range maps to the ADC's full scale) and the additive energy model of Eq. (9) that sums row-driver, ADC, and cell energies per MAC.","core_discovery":"The central claim is that operand sparsity—the zeros in ternary inputs—is the deciding factor in how gracefully a workload degrades on an RRAM crossbar. In simulations, the ternary versions of LeNet-5 and VGG-7 maintain baseline top-1 accuracy at higher parasitic wire resistances than their binary counterparts across the considered memristive technologies and crossbar sizes. The same sparsity compresses the ADC output histograms, so a layer-wise calibration rule that sets the ADC step from the observed output distribution lets both workloads run at 4-bit ADC resolution with minimal accuracy loss, where 6-8 bits are needed without calibration. The cost is energy: because ternary encodings require two dot-product cycles per operation, their energy efficiency is on average 40% lower than the binary versions under the same 4-bit ADC and crossbar size.","pith_inferences":["Because the efficiency gap is computed at equal ADC resolution, a design that exploits the TNN's lower ADC requirement (say, 3-bit instead of 4-bit) could narrow or reverse the 40% energy penalty.","The $\\mu \\pm 3\\sigma$ calibration rule is inherently tied to the calibration data; out-of-distribution inputs would push ADC outputs beyond the chosen range, so robust deployment would need per-dataset recalibration or a wider margin.","The same iterative conductance reduction might extend to multi-level cells and analog inputs if the conductance matrix entries are replaced by per-cell values, making the solver a building block for mixed-precision CIM simulation."],"forward_implications":["Designers can use the fast parasitics solver as a stand-in for SPICE when sweeping crossbar size and wire resistance during early accelerator exploration.","If the calibration result generalizes, 4-bit ADCs—much cheaper and less power-hungry than 6- or 8-bit parts—would suffice for binary and ternary CNN inference on RRAM crossbars.","The 40% energy penalty quantifies the real cost of ternary weights: for energy-constrained devices, binary networks remain the better default unless accuracy or parasitic tolerance forces the ternary choice.","The column-utilisation curves make explicit that energy efficiency saturates as crossbars grow, so there is an optimal crossbar size beyond which larger arrays buy nothing."],"supporting_citations":[{"why":"Supplies the 1T1R parasitic-resistance modelling approach that Algorithm 1 adapts, and the claim that this topology is resilient to wire parasitics.","marker":"[19]"},{"why":"Provides the earlier passive-crossbar parasitic model with O(NM) time that motivates the need for a 1T1R-specific fast solver.","marker":"[3]"},{"why":"Defines the ternary weight-network training methodology and the baseline accuracies that the paper's workloads are compared against.","marker":"[11]"},{"why":"Lists the input encoding schemes (B-I, B-II, T-I, T-II) whose cycle counts and sparsity drive the accuracy and energy results.","marker":"[13]"},{"why":"Supplies the per-cell crossbar energy model that the paper's additive tile-energy formula extends with row-driver and ADC terms.","marker":"[5]"},{"why":"Provides the analytical ADC energy values used for the peripheral energy term in the MAC energy estimate.","marker":"[1]"},{"why":"Supplies the row-driver energy reference used in the same estimate.","marker":"[15]"},{"why":"Supplies the open-source training toolchain used to produce the binary and ternary network weights.","marker":"[7]"}],"fun_headline_variants":["Ternary CNNs outlast binary on RRAM wire and ADC limits","Ternary nets beat binary on RRAM robustness but cost 40% energy","Sparse ternary inputs tame RRAM parasitics and ADC needs","Ternary CNNs: more robust on RRAM, but 40% less energy efficient"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The whole comparison rests on Algorithm 1's iterative conductance reduction being a faithful model of 1T1R crossbar behaviour with resistive wires; the paper states a SPICE error below 0.15% without showing the netlist, comparison points, or validation methodology, so if that circuit model is wrong, the parasitics-resilience ranking loses its foundation.","fun_headline_variants_meta":{"raw":{"variants":["Ternary CNNs outlast binary on RRAM wire and ADC limits","Ternary nets beat binary on RRAM robustness but cost 40% energy","Sparse ternary inputs tame RRAM parasitics and ADC needs","Ternary CNNs: more robust on RRAM, but 40% less energy efficient"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000468,"raw_usage":{"total_tokens":2334,"prompt_tokens":948,"completion_tokens":1386,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":564,"completion_tokens_details":{"reasoning_tokens":1307}},"tokens_in":564,"tokens_out":1386,"duration_ms":9410,"temperature":1.0,"reasoning_tokens":1307,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T22:15:01.509127+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Reproduce the SPICE validation of Algorithm 1 with a complete 1T1R netlist using the same LRS/HRS values and wire-resistance sweep; if the output-current error exceeds 0.15% or the accuracy-vs-$R_p$ curves shift enough to change the TNN-vs-BNN ordering, the central claim is unsupported.","supporting_citations":[{"cited_title":"Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration,","cited_arxiv_id":null,"evidence_quote":"Supplies the 1T1R parasitic-resistance modelling approach that Algorithm 1 adapts, and the claim that this topology is resilient to wire parasitics."},{"cited_title":"Parasitic-aware modeling and neural network training scheme for energy-efficient processing-in- memory with resistive crossbar array,","cited_arxiv_id":null,"evidence_quote":"Provides the earlier passive-crossbar parasitic model with O(NM) time that motivates the need for a 1T1R-specific fast solver."},{"cited_title":"Ternary weight networks,","cited_arxiv_id":null,"evidence_quote":"Defines the ternary weight-network training methodology and the baseline accuracies that the paper's workloads are compared against."},{"cited_title":"Analysis of vmm computation strategies to implement bnn applications on rram arrays,","cited_arxiv_id":null,"evidence_quote":"Lists the input encoding schemes (B-I, B-II, T-I, T-II) whose cycle counts and sparsity drive the accuracy and energy results."},{"cited_title":"A calibratable model for fast energy estimation of MVM operations on RRAM crossbars,","cited_arxiv_id":null,"evidence_quote":"Supplies the per-cell crossbar energy model that the paper's additive tile-energy formula extends with row-driver and ADC terms."},{"cited_title":"Modeling analog-digital-converter energy and area for compute-in-memory accel- erator design,","cited_arxiv_id":null,"evidence_quote":"Provides the analytical ADC energy values used for the peripheral energy term in the MAC energy estimate."},{"cited_title":"DNN+NeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,","cited_arxiv_id":null,"evidence_quote":"Supplies the row-driver energy reference used in the same estimate."},{"cited_title":"Larq: An Open-Source Library for Training Binarized Neural Networks,","cited_arxiv_id":null,"evidence_quote":"Supplies the open-source training toolchain used to produce the binary and ternary network weights."}],"review_version":1}