{"id":"6e989f13-4cbc-43d9-ad51-d42c0849b47b","arxiv_id":"2505.07514","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":6,"one_line_summary":"A two-stage time-stretching TDC built from discrete parts measures pulse widths with 60 to 100 ps resolution using a 100 MHz counter, with conversion time below 300 ns.","lead":"This paper builds a prototype time-to-digital converter that stretches short electrical pulses to measure their arrival time with roughly 60 to 100 picosecond precision using only a 100 MHz clock. It is a low-cost test bench for a future chip design aimed at particle detectors that need very low power per channel.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Reported 60–100 ps resolution depends on bench-measured calibration LUTs and a constant edge-correction factor whose stability is uncharacterized; no independent time reference is used.","rationale":"The reader's verdict CONDITIONAL with the weakest assumption being calibration stability is sound. My stress-test confirms that the 60–100 ps resolution claim rests on LUTs and a constant correction factor whose temperature/supply/aging stability is unmeasured. I additionally note that the calibration reference and the truth reference are the same oscilloscope, and that the agreement with Eq. (4.2) is not an independent confirmation because it uses the same measurements. However, these are addressable concerns: the TDC may well be a viable proof-of-concept, and the final measurement does compare the full FPGA-counter chain against the scope, so the resolution is not purely internal. A temperature and train/test-separation rerun would either support or falsify the transferability of the quoted numbers. For a prototyping paper, CONDITIONAL is the right verdict; my analysis does not move it.","tokens_in":9048,"tokens_out":18985,"duration_ms":184124,"concrete_test":"Re-run the complete calibration and the Figure 13 resolution measurement at 20 °C and 40 °C in a temperature-controlled chamber, with calibration and test data acquired in strictly separate, interleaved runs (no reuse of the same recorded pulses). Compare the resulting LUTs, the residual sigma, and the mean bias. If the residual sigma remains <100 ps and the LUTs shift by less than the calibration uncertainty, the stability concern is resolved; otherwise the reported 60–100 ps figures are not a reliable system-level specification.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim — that the two-stage time-stretching TDC achieves 60–100 ps resolution — is load-bearing on the validity of the calibration LUTs and the constant edge-detection correction factor described in Sections 3–5. The LUTs are generated by measuring each stretching unit's input and output widths with a 3 GHz oscilloscope (Section 5), and Figure 13's 'true' widths are measured with that same oscilloscope. No temperature, supply-voltage, or aging stability data are given, and no split between calibration and test data is documented. If the stretching nonlinearity (Figure 6 right) or the edge-detection offset drifts even by a few tens of picoseconds between calibration and evaluation, the 63 ps residual in Figure 13 would not transfer to a deployed system. Moreover, the agreement between Eq. (4.2) (67 ps) and Figure 13 (63 ps) is not independent, because Eq. (4.2) uses the same scope-based jitter measurements that define the resolution. The architecture may still be viable, but the evidence for the headline resolution is a single-session, scope-relative result.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript describes a proof-of-concept two-stage time-stretching TDC built from discrete components. An input pulse is first stretched by a factor S0, digitized with a 100 MHz counter, and the two sub-clock-cycle residual edges are stretched again by S1 and S2 and digitized, yielding an effective LSB of about T/S^2 ≈ 100 ps. The prototype is characterized with a 3 GHz oscilloscope, including per-stage stretching linearity, jitter, and FPGA edge-detection jitter. The authors report a measured time resolution of 63 ps at 10 ns input width and 60–100 ps across 10–20 ns, with a predicted combined jitter of 67 ps from Eq. (4.2). The paper also presents a toy Monte Carlo study of calibration TDC requirements for a future ASIC implementation.","tokens_in":9263,"tokens_out":6754,"duration_ms":60079,"significance":"If the reported resolution and dead time are robust, the two-stage time-stretching architecture is a credible route toward low-power TDCs for pixel detectors, because it reduces the effective LSB with a slow counter and avoids the dead-time penalty of a single large stretching factor. The paper's strengths are the explicit decomposition of the error budget in Eq. (4.1), the calibration LUT approach with a demonstration that a coarse 2 ns calibration step is sufficient, and the toy MC study of calibration TDC precision. The work is transparent about the prototype's limitations, including nonlinearity and the fact that power consumption is not optimized. The main weakness is that the resolution claim is currently benchmarked against the same oscilloscope used for calibration, with no stability or independent-reference data.","major_comments":[{"comment":"The headline resolution of 63 ps at 10 ns input width is measured by comparing the TDC reconstruction against 'true' widths obtained with the same 3 GHz oscilloscope that was used to generate the calibration look-up tables for S0, S1, and S2. This makes the result circular in the sense that no independent time reference is used, and any drift of the stretching nonlinearity or of the edge-detection correction between calibration and evaluation would be invisible. Please provide an out-of-sample validation, for example a calibrated time interval from a different source or a cross-measurement with a second TDC channel, and a repeatability/stability test with repeated calibrations over time and temperature, to support the claim that the 60–100 ps resolution is a property of the design rather than of one bench session.","section":"§5 and Fig. 13"},{"comment":"The text states that the fixed delay between edge-detection outputs and actual signal edges, and the constant offset between detected and true clock-edge distances, are 'compensated through a constant correction factor applied to the edge-detection outputs.' No numerical value, its uncertainty, or evidence of constancy across the operational range is provided. Since this correction enters directly into the reconstructed width in Eq. (2.4) and contributes to the resolution budget in Eq. (4.1), the omission leaves an unquantified systematic. Please report the measured correction factor with its statistical uncertainty and show that it is stable across the 10–20 ns input range and over the measurement campaign.","section":"§4, edge-detection compensation paragraph"},{"comment":"The combined resolution estimate of 67 ps in Eq. (4.2) uses jitter values (Figures 7, 11, 12) that are themselves measured with the same oscilloscope that provides the 'true' widths in Figure 13. Consequently, the agreement between 67 ps and the measured 63 ps is a consistency check, not an independent validation of the error budget. I ask the authors to state this explicitly or to derive at least one jitter contribution from an independent model, for example comparator noise or current-source noise, rather than from the same measurement chain.","section":"§4, Eq. (4.2)"},{"comment":"The statistical basis for the reported σ values is thin: the histograms in Figures 7, 10, and 13 appear to contain at most a few hundred entries, and no uncertainties on the fitted σ are quoted. Given that the central claim is sub-100 ps resolution, the σ values should be reported with statistical errors from the fit or from a bootstrap, and the number of events should be stated. This is necessary to distinguish the 60–100 ps range from a statistical fluctuation around, say, 80 ps.","section":"§4, Fig. 13 and related histograms"},{"comment":"The abstract and Section 6 state that the conversion time for a 10 ns input width is below 300 ns, but this appears to be a derived quantity based on nominal stretching factors rather than a measured result. Since dead time is a key requirement for the intended high-rate applications, a direct double-pulse measurement showing the minimum interval between two accepted conversions would strengthen the paper. If such a measurement exists, it should be reported explicitly.","section":"§4 and §6, dead-time claim"}],"minor_comments":[{"comment":"The claim of 'under 100 ps' resolution should be qualified to the operational range of 10–20 ns, since Figure 13 (right) shows σ exceeding 100 ps for input widths above about 20 ns.","section":"Abstract and §4"},{"comment":"There is a typo: 'An fast driver' should be 'A fast driver', and 'made withLT3092' is missing a space.","section":"§2, p. 3"},{"comment":"The legend in Figure 14 repeats the same label twice ('σ by look up table from ~0.5 ns step size'); one copy should be removed or corrected.","section":"Fig. 14 legend"},{"comment":"After giving the nominal stretching factor of 11, the text should explicitly note that the measured factors deviate from this value and that this is why interpolation-based look-up tables are needed.","section":"§2, after Eq. (2.3)"},{"comment":"The mean of the distribution in Figure 13 (left) is −0.0261 ns; a brief comment on the source of this small bias would help the reader interpret the data.","section":"§4, Fig. 13 left"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is within JINST scope and the work is honest about its limitations. The main concern is metrological: the calibration and the evaluation share the same reference oscilloscope, so the headline resolution is not yet an independent result. I would encourage the editor to request the stability and validation measurements described in the major comments; with those, the paper would be suitable for acceptance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Dear Colleague,\n\nThe two-stage time-stretching TDC architecture is genuinely neat: stretch the input by S0, count clock cycles, then stretch the two residual edge tails by S1 and S2, giving a total factor ~S0*S1 with dead time ~(S0+S1)*T instead of S0*S1*T. For a total factor of 100, that brings dead time from ~1 µs down to ~300 ns. The LSB formula T/S^2 is right, and the resolution budget in Eq. (4.2) adds up. The basic idea is sound and the prototype demonstrates it.\n\nThe measured 60–100 ps resolution is plausible. The scope waveforms show the expected charge/discharge behavior, the jitter histograms are clean, and the final 63 ps at 10 ns matches the component-level estimates. Using interpolation LUTs to handle the nonlinear current-source behavior is pragmatic and clearly described.\n\nThe soft spots are mostly around referencing and independence. The paper never cites the existing time-stretching TDC literature, so the novelty claim is under-argued. More importantly, the calibration LUTs and the final verification both use the same 3 GHz oscilloscope as the time reference. That makes the reported resolution a single-instrument result, and it also means Eq. (4.2) and Figure 13 are not independent checks of each other. A measurement against an independent time reference, or at least a characterization of the scope's own jitter contribution, would make the numbers much stronger. The constant edge-detection correction factor is introduced without a stability study; temperature and supply voltage are not scanned. The statistics are also thin—many histograms have only a few hundred events.\n\nNone of these are fatal for a proof-of-concept, and the paper says as much. The toy Monte Carlo for the calibration TDC quantization is a nice extra. For the HEP instrumentation community, this is a useful, honest data point for a low-power TDC path toward 4D pixels and neutrino readout.\n\nSend it to peer review. It deserves a serious referee. I'd bring it to the next reading group and would cite it if I were writing about TDC architectures.","headline":"A clean prototype of a two-stage time-stretching TDC with believable but scope-relative 60–100 ps resolution; worth peer review.","tokens_in":9801,"tokens_out":3152,"would_cite":true,"duration_ms":29277,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Two-stage time-stretching TDC built from discrete parts reaches 63 ps resolution using a 100 MHz clock.","keywords":["time-to-digital converter","time stretching","two-stage TDC","discrete components","FPGA","calibration","timing detectors"],"falsifier":"Re-measure the 10 ns input pulse after changing the board temperature by about 10 °C or shifting the LT3092 supply voltage by a few percent without re-running the calibration; if the reconstructed width no longer matches the oscilloscope reference to within the claimed 60–100 ps, the bench-calibration assumption fails.","tokens_in":8826,"feed_emoji":"⏱️","tokens_out":7516,"duration_ms":66719,"temperature":0.7,"pith_summary":"This paper establishes that a two-stage time-stretching time-to-digital converter (TDC) is a practical route to sub-100 ps timing without a fast clock or a high-speed ADC. The prototype, built from capacitors, transistors, comparators, and a low-cost FPGA, measures 10–20 ns input widths with 60–100 ps resolution at a 100 MHz clock rate, and its dead time stays below 300 ns for a 10 ns range. If the result holds, the architecture offers a low-power, low-cost readout for particle-physics timing detectors and a starting point for an ASIC aimed at future 4D pixel detectors.","feed_headline":"Two-stage time stretching gives 63 ps timing with a 100 MHz clock","feed_subtitle":"A low-cost FPGA prototype keeps 60–100 ps resolution and under 300 ns dead time.","key_machinery":"The load-bearing element is the time-stretching unit: a capacitor is discharged quickly while the input pulse is high and recharged slowly afterward, so the output pulse width is the input width times about $1 + I_2/I_1 \\approx 11$. The TDC stretches the input pulse by a first-stage factor $S_0 \\approx 10$, counts whole clock cycles $N_0$ at 100 MHz, then uses edge-detection circuits to capture the two sub-clock residuals and stretches each by another factor near 10 before counting $N_1$ and $N_2$. Reconstruction follows the formula $(N_0 T + N_1 T/S_1 + T - N_2 T/S_2)/S_0$ with $T=10$ ns, giving an effective LSB near $T/S^2 \\approx 100$ ps. The two-stage arrangement keeps dead time near $T_0 S_0 + T_1 S_1$ instead of $T_0 S_0 S_1$.","core_discovery":"The paper claims that a two-stage time-stretching TDC built from discrete components can reach sub-100 ps resolution using only a 100 MHz counter. The measured resolution is 63 ps for 10 ns input pulses and 60–100 ps over the 10–20 ns operating range, matching the predicted 67 ps obtained by combining the counter LSB, first-stage jitter, second-stage jitter, and FPGA edge-detection jitter. The total conversion dead time is below 300 ns for a 10 ns input range, about five times lower than a single-stage design with the same total stretching factor. The resolution bottleneck is the first-stage time-stretching jitter, not the counter quantization.","pith_inferences":["The one-time bench calibration with an oscilloscope is an unstated environmental assumption; temperature, supply-voltage, or aging drift would shift the stretching curves and degrade the reported 60–100 ps figures unless recalibration is added.","The reported 63 ps is measured against a 3 GHz oscilloscope reference, so part of the quoted jitter belongs to the reference; the TDC's intrinsic resolution may be somewhat better than the stated numbers.","The power argument is not demonstrated by this discrete prototype, which uses currents in the 10–100 mA range; the μW-per-channel claim depends on a CMOS implementation that inherits the same calibration and jitter properties."],"forward_implications":["A 100 MHz clock is enough for sub-100 ps timing; the stretching stages, not clock speed, set the resolution.","Two-stage stretching cuts dead time by roughly the first-stage factor compared with a single-stage design, making hit rates of about 100 kHz feasible.","The first-stage time-stretching jitter, not counter quantization, is the current resolution limit, so reducing that jitter in an integrated design should improve resolution toward the sub-50 ps target.","Calibration look-up tables with about 2 ns step spacing give resolution comparable to dense calibration, so a simple on-chip calibration counter may suffice for a multi-channel ASIC.","The prototype already meets the timing needs of neutrino-detector photoelectron readout, where 100 ps precision suffices."],"supporting_citations":[{"why":"Supplies the hadron-collider timing-detector context and the tens-of-picoseconds timing requirement the TDC targets.","marker":"[1]"},{"why":"Supplies the high-granularity timing detector context and the delay-line TDC power budget the design seeks to beat.","marker":"[2]"},{"why":"Provides the high-power, high-cost waveform-sampling baseline for neutrino timing that the TDC offers as an alternative.","marker":"[4]"},{"why":"Represents the milliwatt-per-channel delay-line TDC ASIC whose power level motivates the microwatt-per-channel goal.","marker":"[5]"},{"why":"Gives a low-power delay-line TDC comparison point for resolution and power in the timing layer application.","marker":"[7]"},{"why":"Supplies the hit-rate and dead-time constraints used to justify the two-stage architecture.","marker":"[8]"}],"fun_headline_variants":["Two-stage TDC: 63 ps resolution from a 100 MHz clock","Sub-100 ps TDC using two-stage time stretching, 100 MHz counter","Discrete-component TDC hits 63 ps with two-stage stretching","Two-stage stretch cuts TDC dead time to 300 ns, keeps 63 ps","Low-cost FPGA TDC: 63 ps timing with two-stage architecture"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the calibration look-up tables and constant edge-detection corrections, measured once on the bench, remain valid during the reported measurements and in real use, with no stability data for temperature, supply voltage, or aging.","fun_headline_variants_meta":{"raw":{"variants":["Two-stage TDC: 63 ps resolution from a 100 MHz clock","Sub-100 ps TDC using two-stage time stretching, 100 MHz counter","Discrete-component TDC hits 63 ps with two-stage stretching","Two-stage stretch cuts TDC dead time to 300 ns, keeps 63 ps","Low-cost FPGA TDC: 63 ps timing with two-stage architecture"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000296,"raw_usage":{"total_tokens":1683,"prompt_tokens":876,"completion_tokens":807,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":492,"completion_tokens_details":{"reasoning_tokens":706}},"tokens_in":492,"tokens_out":807,"duration_ms":7583,"temperature":1.0,"reasoning_tokens":706,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T22:14:44.684731+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-measure the 10 ns input pulse after changing the board temperature by about 10 °C or shifting the LT3092 supply voltage by a few percent without re-running the calibration; if the reconstructed width no longer matches the oscilloscope reference to within the claimed 60–100 ps, the bench-calibration assumption fails.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Represents the milliwatt-per-channel delay-line TDC ASIC whose power level motivates the microwatt-per-channel goal."},{"cited_title":"ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade","cited_arxiv_id":"2404.14207","evidence_quote":"Gives a low-power delay-line TDC comparison point for resolution and power in the timing layer application."}],"review_version":1}