{"id":"5c699e6f-b72d-434e-a192-65aca012e859","arxiv_id":"2505.08424","paper_version":3,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A 200 mm CMOS-compatible subtractive process produced transmon qubits with median T1 near 100 microseconds and individual qubits exceeding 200 microseconds, the best reported for wafer-level subtractive fabrication.","lead":"An industrial CMOS-style fabrication line made superconducting qubits on 200 mm wafers with 99.7% junction yield and qubits that stay coherent for over 200 microseconds. This suggests that mass manufacturing methods can reach the coherence levels needed for practical quantum computers.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Cryogenic T1 statistics are based on room-temperature-selected chips with unreported sample sizes, so wafer-scale representativeness is not yet established.","rationale":"The reader's weakest-assumption analysis identified the same load-bearing concern: cryogenic chips were deliberately selected using room-temperature data, and the number of qubits per split group is not reported. My independent review confirms that this is the most consequential gap. The yield statistic (99.7% over 10072 junctions) and frequency prediction (1.6% over 40 qubits) are credible and support the process-control claims. The coherence claims, however, are conditional on an unreported sampling procedure. The paper explicitly acknowledges the selection step in Section II and even markets room-temperature preselection as an advantage, but the abstract and conclusion phrase the T1 results as statistical properties of the fabrication approach. A concrete, feasible check is to measure an unselected random sample from split B; this would settle whether the median and worst-qubit values are representative. No internal inconsistency or evidence of data fabrication was found, so the appropriate verdict remains CONDITIONAL rather than REJECT or ACCEPT. Since my concern matches the reader's, the reader's verdict does not need to change.","tokens_in":7570,"tokens_out":4057,"duration_ms":45615,"concrete_test":"Obtain from the authors the exact number of qubits in split groups A and B and the room-temperature Rn values of every cryogenically measured chip. Then measure T1 with the same protocol on a random sample of 10-20 chips from split B across the full wafer diameter, including chips outside the ±10% Rn target. If the median T1 of this unselected sample is still approximately 100 us and the worst qubit remains above 20 us, the selection concern is resolved. If the median drops or the worst qubit approaches zero, the abstract should be revised to state that the quoted coherence figures apply to selected devices, not to the wafer population.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that this is a credible wafer-scale path requires the cryogenic T1 distribution to represent the fabrication run. Section II states that 'specific chips are picked from the wafers' based on wafer-level electrical characterization, and Section III B reports T1 for chips 'picked from several wafers of the processing run and across the full wafer diameter,' but it never states how many chips or qubits are in split groups A and B, nor the selection rule. If chips were chosen partly for junction resistance near the 7.1 kOhm target, the T1 sample is conditioned on Rn; junction and oxide quality can correlate with Rn, so the median of ~100 us and the 'worst qubit exceeds 20 us' statement for split B need not extend to the general wafer population. The authors' assertion that 'all data generated up to the drafting of the article is shown' addresses omission within the selected set, not the selection of the set itself. The yield and frequency-prediction results are strong and independent, but the coherence statistics, as reported, cannot separate wafer-scale capability from chip preselection.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper reports an industry-grade fabrication run of superconducting transmon qubits on 200 mm wafers using CMOS-compatible subtractive Al/AlOx/Al processing. Room-temperature wafer-prober measurements over 10072 Josephson junctions yield a pass rate of 99.7% (30 fails), and Eq. (1) using measured normal-state resistance predicts qubit frequencies with an average deviation of 1.6% on 40 cryogenically characterized qubits. Cryogenic measurements compare two process splits: split A with a median T1 of about 40 us and split B with a median T1 of about 100 us, with individual qubits reaching T1 values around 200 us, T2echo values above 200 us, a 16-hour stability measurement on a hero qubit whose mean T1 is (196 +/- 16) us over about 1000 cycles, and one chip on which all four qubits exceed 100 us. The paper concludes that the CMOS-compatible wafer-scale process is a credible path to scalable superconducting QPUs.","tokens_in":7734,"tokens_out":8558,"duration_ms":84222,"significance":"If the cryogenic results are representative, this is a meaningful milestone: the junction yield and frequency-targeting data are concrete, large-scale, and machine-checked, and the long-term stability and on-chip uniformity are useful. The room-temperature yield statistics over 10072 junctions on eight wafers are a particular strength; the paper also explicitly states that no measured data were omitted and uses no fitted free parameters in the T1 or yield analysis. The main caveat is that the cryogenic chips were deliberately selected, and the paper does not yet establish that the reported T1 distribution represents the full wafer population. With the selection details supplied, the paper would be a solid contribution.","major_comments":[{"comment":"Section II states that 'specific chips are picked from the wafers' after wafer-level electrical characterization, and Section III B reports T1 data for chips 'picked from several wafers of the processing run and across the full wafer diameter,' but the selection rule, the number of chips, and the number of qubits in split groups A and B are not reported. Because the T1 distribution is therefore conditioned on a deliberate room-temperature selection (potentially favoring chips near the R_n = 7.1 kOhm target), the median T1 of ~100 us and the 'worst qubit exceeds 20 us' claim for split B cannot yet be taken as wafer-scale statistics. This is load-bearing for the paper's central claim that the process reliably yields high-quality qubits across full wafers. Please state the exact selection criterion, list how many chips and qubits were measured per split and per wafer, and report whether any measured chip or qubit was excluded after selection.","section":"Section II, 'Dicing and Bonding'; Section III B"},{"comment":"The boxplots are the statistical basis for comparing split groups, yet no sample sizes, confidence intervals, or per-split summary tables are provided. The statement 'all data generated up to the drafting of the article is shown, nothing is omitted' addresses omission from the already-selected measurement set, not the selection of that set; it does not rule out selection bias. If the selected sets are small (for example, only a few chips per split), the median, minimum, and maximum T1 values need to be accompanied by n and by a discussion of what the room-temperature preselection implies for the interpretation.","section":"Section III B, Figure 2a"},{"comment":"The title claims qubits 'Exceeding Energy Relaxation Times of 200 us,' but the abstract only reports devices 'approaching 200 us' and the body states that 'several qubits reached a T1 up to 200 us' while the only detailed long-term T1 value is a mean of (196 +/- 16) us from the histogram in Fig. 2b. The introduction does claim 'maximum exceeding 200 us for both T1 and T2echo,' which is not supported by a reported numerical maximum for T1. Please clarify whether any qubit's average or maximum T1 exceeds 200 us, report that value, and adjust the title and abstract accordingly if the data only support 'approaching' or 'up to' 200 us.","section":"Title; Abstract; Section I; Section III B"},{"comment":"The reported 1.6% frequency-prediction accuracy is computed on 40 qubits from 'selected chips,' but the text does not state how those chips were selected or how the 40 qubits were distributed across chips and wafers. The calculation also uses the design capacitance Cq = 86 fF and Tc = 0.71 K from previous work, so the 1.6% includes device-to-device capacitance deviations and is not a pure measure of fabrication targeting. Please report the selection of these chips and the per-qubit residuals; otherwise the accuracy figure cannot be independently assessed.","section":"Section III A, Eq. (1), Fig. 1b"}],"minor_comments":[{"comment":"Typos should be corrected: 'W afer' in Section II headings, 'proofed' in Section III A, 'Simlar' in Section III B, 'Boltzman' in Section III A, and 'a energy relaxation time' in Section IV should read 'Wafer', 'proved', 'Similar', 'Boltzmann', and 'an energy relaxation time'.","section":"Throughout"},{"comment":"The caption reads 'showing a qubit's Josephson junction as fail'; it should read 'as a fail'.","section":"Figure 1a caption"},{"comment":"The phrase 'median T1 of up to 100 us' is ambiguous about whether 100 us is a median or an upper bound. It should be rephrased to 'median T1 of 100 us' for split B, with the corresponding sample size stated.","section":"Abstract; Section III B"},{"comment":"The footnote is a welcome caveat about long-term TLS effects, but the main text should also explicitly state that the 16-hour stability measurement is for a single hero device and is not evidence of similar stability across the full split group.","section":"Section III B, footnote 4"}],"recommendation":"major_revision","confidential_remarks":"The chip-selection issue is decisive for the coherence claims; the room-temperature yield evidence is strong and publishable on its own. If the authors can supply the missing counts and selection criteria, and adjust the title/abstract to match the actual T1 data, I would support publication. Otherwise the wafer-scale framing is overstated."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: the wafer-scale room-temperature numbers are the paper's real contribution; the cryogenic T1 statistics are real but cannot carry the wafer-scale representativeness claim as reported. The paper deserves a serious referee.\n\nWhat is actually new: a single processing run on eight 200 mm wafers with 99.7% yield over 10072 junctions and 1.6% average frequency prediction error over 40 qubits. Those are concrete, hard numbers, and they strengthen the case that subtractive CMOS-compatible processing can produce junctions with high uniformity. The T1 split-B median of roughly 100 us and max >200 us is notable for this processing route, and the 16-hour stability data on one hero device is a useful data point. I do not read this as a new technique; it is the same process as their Ref [4] with an optimized run and better statistics. That is a legitimate extension, and the paper says so.\n\nWhere I agree with the stress-test: the coherence statistics are conditioned on room-temperature preselection. Section II says chips are 'picked' based on wafer-level electrical characterization, and the paper never reports how many chips or qubits are in splits A and B. The sentence that all data up to drafting are shown addresses omission within the selected set, not selection of the set. So 'wafer-scale T1 performance' should not be inferred from these numbers. The yield and frequency results are wafer-wide and stand on their own.\n\nWhat I would add: this does not sink the paper. The preselection is transparent at the level of the text, the frequency-targeting application is precisely a room-temperature selection capability, and the T1 numbers are still indicative of process quality even if not representative of every wafer. The bigger reporting flaw is missing N and selection rule. The 'best reported' phrase is also not checked against Ref [5], the 300 mm work, so a referee should ask for a quantitative comparison.\n\nFor whom: quantum hardware people tracking industrial fabrication, and anyone assessing CMOS routes to scalable transmon processors. The paper should go to peer review. A serious referee should push for sample sizes, selection criteria, and a head-to-head with prior 300 mm CMOS coherence numbers.","headline":"A solid, incremental fabrication result with strong room-temperature yield statistics and a credible but preselected cryogenic T1 sample; send to referees.","tokens_in":8368,"tokens_out":1772,"would_cite":true,"duration_ms":18837,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["85.25.Cp","03.67.Lx"],"model":"deepseek-v4-flash","headline":"A CMOS-compatible, wafer-scale subtractive process produced transmon qubits with median T1 near 100 µs and best values above 200 µs, alongside a 99.7% junction yield.","keywords":["superconducting qubits","transmon","Josephson junctions","CMOS-compatible fabrication","200 mm wafer processing","energy relaxation time","frequency targeting","subtractive processing"],"falsifier":"Cool down a random sample of chips from all eight wafers without using room-temperature resistance as a selection filter, and count the qubits with $T_1$ below 20 $\\mu$s together with the sample median; if the median falls well below 100 $\\mu$s or many qubits fall below 20 $\\mu$s, the wafer-wide performance claim would not survive.","tokens_in":7342,"feed_emoji":"⚛️","tokens_out":8099,"duration_ms":67226,"temperature":0.7,"pith_summary":"This paper reports that an industry-grade, subtractive fabrication process on 200 mm wafers—patterning aluminum layers by optical lithography and dry etching, as in CMOS production—can produce transmon qubits with a room-temperature Josephson junction yield of 99.7% across more than 10,000 junctions and cryogenic energy relaxation times with a median near 100 $\\mu$s and maxima exceeding 200 $\\mu$s. The authors argue that this combination of yield, frequency predictability, and coherence puts wafer-scale subtractive manufacturing on a credible path toward scalable quantum processing units. The cryogenic statistics come from chips deliberately selected after room-temperature probing, so the wafer-wide performance claim rests on how representative that selection is.","feed_headline":"CMOS-style wafer process yields 200-µs superconducting qubits","feed_subtitle":"A 200 mm subtractive flow reports 99.7% junction yield and median T1 near 100 µs.","key_machinery":"The load-bearing object is the Josephson junction formed by two patterned aluminum layers with an in-situ grown aluminum-oxide tunnel barrier, fabricated by subtractive processing. The room-temperature normal-state resistance $R_n$ of each junction is the central predictor: measured automatically at the wafer level, it separates shorts from opens to give the 99.7% yield, and through the Ambegaokar-Baratoff relation it determines the qubit frequency, enabling chip preselection before cooldown.","core_discovery":"On the paper's own terms, the central discovery is that a subtractive Al/AlOx/Al junction process—bottom and top electrodes patterned by optical lithography and dry etching, with the tunnel barrier formed in situ—can deliver both high reproducibility and long coherence. In the best split group, the median $T_1$ is about 100 $\\mu$s, the minimum measured $T_1$ is about 20 $\\mu$s, and individual qubits reach $T_1$ and $T_2^{\\text{echo}}$ above 200 $\\mu$s; a 16-hour stability study on one device keeps $T_1$ above roughly 150 $\\mu$s. Room-temperature junction resistance, measured automatically on every qubit, predicts the cryogenic qubit frequency with 1.6% average deviation through the Ambegaokar-Baratoff relation, which the paper uses as the basis for chip preselection and frequency targeting.","pith_inferences":["A natural extension is to test whether qubits whose room-temperature resistance lies closest to target also have the highest $T_1$; the paper does not report that correlation.","If the wafer-level yield transfers to larger chips, thousands of junctions per quantum processor could be patterned with the same toolset, a scale that evaporation-based processing would struggle to match.","Combining subtractive fabrication with laser or thermal annealing for post-fabrication resistance trimming could close the remaining frequency-targeting gap and raise the pass rate for tight limits.","The 16-hour stability window is encouraging, but measurements over weeks or months would be needed to learn how often strongly coupled two-level systems drift into resonance."],"forward_implications":["A CMOS-compatible subtractive line can supply qubits whose coherence is comparable to evaporation-based devices, since the best split group reaches a median $T_1$ near 100 $\\mu$s.","Room-temperature wafer probing can screen for junction yield and qubit frequency, so only chips that pass tight resistance limits need to be cooled.","Without post-fabrication tuning, qubit frequencies land within about 2.5% of design on average across all four qubits per chip, with tighter limits available at the cost of chip count.","Long-term $T_1$ stability on one qubit and a chip where all four qubits exceed 100 $\\mu$s suggest low loss density and good local uniformity.","The combination of high junction yield and predictable frequency is a step toward scaling to larger chips and to architectures like fluxonium that need many series junctions."],"supporting_citations":[{"why":"Supplies the chip design, main process sequence, and characterization approach that this run extends.","marker":"[4]"},{"why":"The 300 mm wafer CMOS fabrication result that serves as the comparison baseline for industry-grade subtractive qubit performance.","marker":"[5]"},{"why":"The Ambegaokar-Baratoff tunneling relation used to predict qubit frequency from room-temperature junction resistance.","marker":"[9]"},{"why":"Earlier wafer-scale room-temperature characterization work establishing junction resistance probing as a yield and frequency predictor.","marker":"[7]"},{"why":"Presents the aluminum oxidation techniques used to form the junction barrier in the 200 mm wafer process.","marker":"[6]"}],"fun_headline_variants":["CMOS-processed qubits exceed 200µs T1 with 99.7% yield","Wafer-scale qubits: 200µs coherence, 99.7% junction yield","99.7% yield, 200µs T1: CMOS qubits from 200mm wafers","200mm wafer process: 99.7% yield, qubit T1 >200µs"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the chips measured at cryogenic temperature were representative of the whole wafer population, because they were deliberately picked after room-temperature electrical characterization.","fun_headline_variants_meta":{"raw":{"variants":["CMOS-processed qubits exceed 200µs T1 with 99.7% yield","Wafer-scale qubits: 200µs coherence, 99.7% junction yield","99.7% yield, 200µs T1: CMOS qubits from 200mm wafers","200mm wafer process: 99.7% yield, qubit T1 >200µs"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00111,"raw_usage":{"total_tokens":4585,"prompt_tokens":867,"completion_tokens":3718,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":483,"completion_tokens_details":{"reasoning_tokens":3622}},"tokens_in":483,"tokens_out":3718,"duration_ms":22883,"temperature":1.0,"reasoning_tokens":3622,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T21:55:56.340000+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Cool down a random sample of chips from all eight wafers without using room-temperature resistance as a selection filter, and count the qubits with $T_1$ below 20 $\\mu$s together with the sample median; if the median falls well below 100 $\\mu$s or many qubits fall below 20 $\\mu$s, the wafer-wide performance claim would not survive.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the chip design, main process sequence, and characterization approach that this run extends."},{"cited_title":"Van Damme, S","cited_arxiv_id":null,"evidence_quote":"The 300 mm wafer CMOS fabrication result that serves as the comparison baseline for industry-grade subtractive qubit performance."},{"cited_title":"Ambegaokar and A","cited_arxiv_id":null,"evidence_quote":"The Ambegaokar-Baratoff tunneling relation used to predict qubit frequency from room-temperature junction resistance."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Earlier wafer-scale room-temperature characterization work establishing junction resistance probing as a yield and frequency predictor."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Presents the aluminum oxidation techniques used to form the junction barrier in the 200 mm wafer process."}],"review_version":1}