{"id":"9237587d-457a-4411-8654-1244c801b1f0","arxiv_id":"2505.10060","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"low","formal_verification":"none","parameter_count":1,"one_line_summary":"A 34 mm2 Linux-capable 64-bit RISC-V SoC with 2.7 MGE was designed and fabricated using an end-to-end open-source EDA flow, reaching 62 MHz at 1.2 V.","lead":"Basilisk is a 34 square millimeter, 2.7 million gate equivalent system-on-chip with a 64-bit RISC-V core that runs Linux, built entirely with open-source chip design tools and fabricated in a 130 nanometer process. It shows that open-source electronic design automation can now produce large, industry-grade chips rather than just small test designs.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Flow-improvement claims rest on an underspecified ORFS baseline; the 2.3x timing and 1.6x area ratios are not reproducible as reported.","rationale":"The central claim of a functional, large, open-source SoC is well supported by the silicon evidence: a 34 mm2 die, 2.7 MGE complexity, ten packaged chips with measured leakage, and a Shmoo plot demonstrating operation up to 102 MHz. The reader's conditional verdict is appropriate and I do not see a reason to move it. The load-bearing weakness is the reproducibility of the OSEDA flow-improvement numbers, which are a major stated contribution. The paper gives only 'derived from [9]' as the baseline description, with no commit hash, tool versions, or scripts, and the comparison is made at post-synthesis rather than post-P&R or on silicon. This makes the 2.3x timing and 1.6x area improvements difficult to verify independently. A concrete reconstruction and re-run of both flows would settle whether the ratios hold. I agree with the reader's identification of this as the weakest assumption, and the requested additions (full baseline specification and measurement error bars) would make the paper fully convincing.","tokens_in":4566,"tokens_out":11460,"duration_ms":124826,"concrete_test":"In the Basilisk repository, reconstruct the exact baseline flow by identifying the ORFS commit/tag, tool versions, and synthesis script used. Re-run the baseline and the improved flow on the same RTL, PDK, and machine, reporting post-synthesis and post-P&R area, Fmax, runtime, and memory. If the corrected ratios fall below the claimed 1.6x area / 2.3x timing (e.g., to less than 1.3x/1.8x), revise the abstract's flow-improvement claim.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section III states the baseline is 'a baseline synthesis flow derived from [9]' but does not specify the ORFS commit or tag, the Yosys/Yosys-Slang and ABC versions, the frontend path (e.g., sv2v vs native elaboration), or the exact synthesis script used for the baseline. Since ORFS is under active development and QoR is sensitive to tool versions and scripts, a different or misconfigured baseline could materially change the reported 2.3x timing and 1.6x area improvements. The timing comparison is also only at the post-synthesis level (33 to 77 MHz); the paper does not report the baseline's post-place-and-route or measured silicon Fmax, so it is unclear whether the 2.3x improvement survives physical design. The same missing baseline description affects the 12% die-area reduction claim attributed to OpenROAD tuning. These flow comparisons are a headline contribution of the paper, even though the fabricated chip's functionality and the 'largest open-source SoC' claim would remain intact if the flow ratios were revised.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports the design, implementation, and first silicon measurements of Basilisk, a 34 mm2 SoC in IHP's open 130 nm BiCMOS technology. Basilisk is based on the Cheshire platform and the CVA6 64-bit RISC-V core, with a HyperRAM controller, USB 1.1 host, VGA output, C2C link, and other peripherals. The authors claim this is the largest end-to-end open-source SoC to date, with 2.7 MGE total complexity and 1.14 MGE standard-cell complexity. They also report OSEDA flow improvements: a Yosys-Slang frontend and synthesis optimizations that reduce post-synthesis cell area from 1.8 to 1.1 MGE (1.6x) and increase post-synthesis clock frequency from 33 to 77 MHz (2.3x), plus OpenROAD tuning that reduces die area from 39 to 34 mm2 (-12%). Measured silicon performance reaches 62 MHz at 1.2 V, 102 MHz at 1.64 V, and 18.9 DP MFLOP/s/W on FP64 GEMM at 0.88 V.","tokens_in":4809,"tokens_out":6725,"duration_ms":61833,"significance":"If the results hold, this is a notable milestone for open-source EDA: it demonstrates that an application-class, Linux-capable SoC can be designed end-to-end with open tools and fabricated in an open PDK. The silicon measurements are concrete and credible, and the availability of the source repository and the comparison to prior open-flow chips are valuable. The flow improvements, if made reproducible, would be a useful contribution to the OSEDA community, but the current manuscript does not yet provide enough detail to validate the claimed 2.3x timing and 1.6x area improvements or the 12% die-area reduction.","major_comments":[{"comment":"The baseline synthesis flow is underspecified: the authors do not state the ORFS commit or tag, the Yosys/Yosys-Slang and ABC versions, the frontend path (native Yosys-Slang vs sv2v conversion), or the exact synthesis script used for the baseline. Because ORFS quality-of-results varies strongly with tool versions and script configuration, this prevents reproducibility of the claimed 2.3x timing and 1.6x area improvements and the associated runtime and memory reductions. Please provide the exact configuration of the baseline flow, for example by committing the baseline scripts and tool versions to the repository.","section":"Section III, 'Compared to a baseline synthesis flow derived from [9]'"},{"comment":"The 2.3x timing improvement is reported only at the post-synthesis level (33 vs 77 MHz). It is not shown whether this improvement persists after placement and routing; the baseline's post-place-and-route Fmax or its measured silicon frequency should be reported, or the claim should be explicitly scoped to synthesis. Without this, the 'timing improvement' headline is not fully substantiated as an end-to-end flow result.","section":"Section III, timing comparison"},{"comment":"The 12% die-area reduction (from 39 to 34 mm2) is attributed to tuned OpenROAD hyperparameters and 'strategically added small routing blockages,' but no details are given about which hyperparameters were changed, where the blockages were placed, or their sizes. To make this result reproducible and auditable, please document the configuration, ideally as a commit or configuration file in the OpenROAD-flow-scripts repository, and state the OpenROAD version used.","section":"Section III, OpenROAD tuning"},{"comment":"The abstract and title describe Basilisk as 'Linux-capable,' but the silicon results section reports only a GEMM benchmark, frequency, and leakage measurements. Please clarify whether Linux was actually booted on the fabricated chip; if it was, report the boot and the peripherals tested, and if it was not, temper the claim or explicitly state that Linux capability is inherited from the CVA6 core and platform rather than demonstrated on this silicon.","section":"Section IV, silicon results"}],"minor_comments":[{"comment":"The abstract states that synthesis runtime is reduced by 2.5x, while Section III states a reduction from 5.4 h to 1.7 h, which is 3.2x; please reconcile these numbers.","section":"Abstract vs. Section III"},{"comment":"The 'specialized optimization mapping aligned shift operations to multiplexers' is mentioned without a reference or a code link; please provide a pointer to the implementation or a more detailed description so that the optimization can be evaluated.","section":"Section III, Yosys-Slang description"},{"comment":"The table footnotes for the 'd' and 'e' markers are difficult to parse, and the notation '130 d/110be' is unclear; please present the raw and normalized runtimes in separate columns or explain the normalization in the caption.","section":"Table I"},{"comment":"The paper claims an 'end-to-end' open-source flow but does not report whether logic equivalence checking, DRC, or LVS were performed and passed; if these checks were run, please state the results, and if not, consider qualifying the 'end-to-end' claim.","section":"End-to-end verification claim"},{"comment":"The statement that the flow improvements are portable, based on MLEM reusing Basilisk's tuned flow, is weak because MLEM is a simple microcontroller by the same authors; either temper the portability claim or provide evidence from a more distinct design.","section":"Section IV, portability claim"}],"recommendation":"major_revision","confidential_remarks":"The manuscript appears to be a short-format paper, and the missing flow details are likely due to page limits. However, the headline quantitative claims about flow improvements are not reproducible without specifying the baseline configuration, so the authors should be asked to provide the exact tool versions and scripts before acceptance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The thing to know about this paper: it delivers what it promises. Basilisk is the largest end-to-end open-source SoC to date, it runs Linux, and the silicon measurements are real. The authors took the Cheshire platform and CVA6 core, pushed it through Yosys-Slang and OpenROAD into IHP's open 130 nm PDK, fabricated it, and got a working 34 mm2, 2.7 MGE chip that does 62 MHz at 1.2 V and 102 MHz at 1.64 V. That is a concrete milestone for open-source hardware, not a simulation or a promise. The measured FP64 GEMM energy efficiency and the leakage data across ten chips are also credible and useful. Credit where it is due: the Yosys-Slang SystemVerilog frontend is a genuine tool contribution, and the OpenROAD tuning with routing blockages is specific enough that someone could reproduce it, assuming the scripts are in the repo.\n\nThe soft spots are real but not fatal. The biggest one is the baseline for the 2.3x timing and 1.6x area improvements. Section III says the baseline is \"derived from [9]\" and nothing more. No ORFS commit, no Yosys/Slang versions, no exact synthesis script. Since OpenROAD-flow-scripts changes fast and QoR is version-sensitive, that ratio is not reproducible as reported. The timing comparison is also only post-synthesis (33 to 77 MHz); we never learn whether the 2.3x survives place and route or shows up in measured silicon. The 12% die-area reduction from OpenROAD tuning has the same problem. If the baseline was reasonable, the improvements are probably real, but I cannot fully verify that from the paper text alone. A reproducibility appendix with exact versions, scripts, and the baseline's post-P&R numbers would close the gap.\n\nThe self-citations are not a problem: the paper builds directly on Cheshire, CVA6, and prior flow work, and it cites them properly. The circularity of engineering the flow on the same design you then measure is mild for a chip paper; the portability claim gets some support from MLEM reusing the flow. Measurement error bars or chip-to-chip frequency spread would be nice, but for a first silicon report the single shmoo curve is acceptable.\n\nWho is this for? Anyone working on open EDA flows, open PDKs, or open-source SoC enablement. It deserves a serious referee: the central claim is important and backed by silicon, and the questions about the baseline are answerable with a revision. I would take it for peer review and push for the reproducibility details before acceptance.","headline":"Basilisk is the first Linux-capable application-class SoC built end-to-end with open-source EDA tools and measured on silicon; a real milestone, though the flow-improvement ratios rest on a baseline that needs pinning down.","tokens_in":5330,"tokens_out":1057,"would_cite":true,"duration_ms":11908,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The largest end-to-end open-source SoC to date is a 34 mm², 64-bit Linux-capable RISC-V design that reaches 62 MHz at nominal voltage and 102 MHz at 1.64 V.","keywords":["open-source silicon","RISC-V SoC","system-on-chip","Yosys","OpenROAD","Linux-capable","130nm BiCMOS","energy efficiency"],"falsifier":"Re-run the Basilisk RTL through the unmodified baseline open synthesis flow on the same 130 nm process design kit and compare the resulting clock frequency and standard-cell area; if the gap is materially smaller than 2.3× and 1.6×, the claimed flow improvement is overstated.","tokens_in":4427,"feed_emoji":"🔓","tokens_out":9013,"duration_ms":81084,"temperature":0.7,"pith_summary":"This paper reports the largest end-to-end open-source system-on-chip to date: Basilisk, a 34 mm² design with about 2.7 million gate equivalents, built around a 64-bit Linux-capable RISC-V core. The central claim is that a fully open design toolchain can now carry an application-class SoC through synthesis, place and route, and fabrication, not just small microcontrollers. Supporting that claim, the authors' improvements to the open synthesis flow yield 2.3× better timing and 1.6× smaller standard-cell area relative to the baseline open flow, and their placement-and-routing tuning reduces die size by 12%. Silicon measurements show 62 MHz at the nominal 1.2 V supply, up to 102 MHz at 1.64 V, and a peak energy efficiency of 18.9 MFLOP/s/W on FP64 matrix multiply at 0.88 V. If true, this means the open EDA stack has crossed a scale threshold, making Linux-class chips feasible without proprietary tools.","feed_headline":"Open-source chip design flow yields largest Linux SoC yet","feed_subtitle":"A 34 mm² RISC-V chip built entirely with open tools hits 62 MHz at 1.2 V and up to 102 MHz at 1.64 V.","key_machinery":"The load-bearing mechanism is the open synthesis toolchain: Yosys-Slang, a SystemVerilog frontend for the open synthesizer Yosys built on the Slang compiler, which elaborates industry-grade SystemVerilog directly instead of converting it to simpler Verilog first. Around it, the authors build a high-effort synthesis script using the 'lazy man's synthesis' technique, add an optimization that maps shift operations to multiplexers, and then tune the open place-and-route flow, including small routing blockages near power-grid connections, to relieve congestion. This combination preserves design intent through elaboration, which yields smaller netlists, and then makes better use of the 130 nm cell library during logic optimization and physical design.","core_discovery":"In the authors' own framing, the discovery is that the gap between open-source and commercial electronic design automation has narrowed enough that a large, Linux-capable SoC can be produced end to end with open tools and still meet competitive performance targets. Basilisk is the demonstration: a 34 mm², 2.7 MGE design in an open 130 nm BiCMOS process, containing an RV64GC-compliant 64-bit RISC-V core, a 124 MB/s DRAM controller with a four-way 64 KiB last-level cache, a USB 1.1 host, a VGA output, and a 62 Mb/s chip-to-chip link. The measured chip reaches 62 MHz at 1.2 V and 102 MHz at 1.64 V, with 18.9 MFLOP/s/W on FP64 GEMM at 0.88 V, and its longest path is 51 logic levels, comparable to a commercial implementation of the same platform at 46 logic levels. The authors attribute the result to a new SystemVerilog frontend for the Yosys synthesizer, a tuned synthesis script, and targeted place-and-route adjustments, which together reduce standard-cell area from 1.8 to 1.1 MGE and raise post-synthesis frequency from 33 to 77 MHz.","pith_inferences":["If the same synthesis and place-and-route improvements transfer to other open process design kits, the cost and time to enter custom silicon could drop well below what the paper itself demonstrates; this is an extrapolation, since the paper evaluates one process.","The digital 62 Mb/s chip-to-chip link opens an implicit path to multi-die open-source systems, where several Basilisk-class chips are connected without proprietary high-speed transceivers; the paper does not develop this direction.","Because the frontend preserves SystemVerilog intent, designs that rely heavily on advanced SV constructs such as interfaces and structs may see larger synthesis gains than the simpler Verilog designs used in earlier open-flow demonstrations; this is a testable prediction.","The measured energy-efficiency peak is reported at 0.88 V and 10 MHz, well below nominal voltage; a reader could reasonably use this as evidence to under-clock rather than power-gate for floating-point workloads, though the paper does not make that recommendation."],"forward_implications":["Linux-capable 64-bit SoCs are no longer out of reach for fully open design flows, so a research group or small company can produce an application-class chip without licensing commercial EDA.","The 2.3× timing and 1.6× area synthesis gains imply that open synthesis is no longer the dominant quality bottleneck for designs of this size; more of the remaining gap sits in physical design and process design kit maturity.","At 62 to 102 MHz in 130 nm, the chip is fast enough for real embedded Linux workloads, and the 18.9 MFLOP/s/W peak suggests low-voltage operation is the sensible energy point.","The complexity-normalized runtime comparison in the paper suggests the tuned flow transfers to other designs, shortening the path from RTL to GDSII for future open chips."],"supporting_citations":[{"why":"Supplies the SoC platform that Basilisk builds on.","marker":"[4]"},{"why":"Supplies the 64-bit RISC-V core used as the main processor.","marker":"[5]"},{"why":"Supplies the open 130 nm process design kit used for fabrication.","marker":"[8]"},{"why":"Provides the baseline open synthesis and physical-design flow that the paper's improvements are measured against.","marker":"[9]"},{"why":"Describes the simpler microcontroller that reuses the tuned flow and serves as the portability data point.","marker":"[15]"},{"why":"Provides the SystemVerilog compiler underlying the new synthesis frontend.","marker":"[21]"},{"why":"Supplies the synthesis-optimization method used to build the high-effort logic script.","marker":"[22]"},{"why":"Provides the test harness that runs the on-chip workload and voltage/frequency sweeps.","marker":"[23]"}],"fun_headline_variants":["Open-source tools build largest Linux-capable RISC-V SoC","Basilisk: open-source SoC hits 102 MHz, runs Linux","Linux-capable RISC-V chip built entirely with open EDA","Largest open-source SoC: 34 mm² RISC-V runs Linux","Open EDA flow produces 64-bit RISC-V SoC in 130nm"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The reported 2.3× timing and 1.6× area improvements are measured against a baseline synthesis flow that the paper only describes as 'derived from [9]', so if that baseline is not representative of the prior state of the art, the improvements would be overstated even though the chip itself is real.","fun_headline_variants_meta":{"raw":{"variants":["Open-source tools build largest Linux-capable RISC-V SoC","Basilisk: open-source SoC hits 102 MHz, runs Linux","Linux-capable RISC-V chip built entirely with open EDA","Largest open-source SoC: 34 mm² RISC-V runs Linux","Open EDA flow produces 64-bit RISC-V SoC in 130nm"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000397,"raw_usage":{"total_tokens":2174,"prompt_tokens":1138,"completion_tokens":1036,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":754,"completion_tokens_details":{"reasoning_tokens":936}},"tokens_in":754,"tokens_out":1036,"duration_ms":6993,"temperature":1.0,"reasoning_tokens":936,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T21:16:44.086145+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-run the Basilisk RTL through the unmodified baseline open synthesis flow on the same 130 nm process design kit and compare the resulting clock frequency and standard-cell area; if the gap is materially smaller than 2.3× and 1.6×, the claimed flow improvement is overstated.","supporting_citations":[{"cited_title":"Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon","cited_arxiv_id":"2502.05090","evidence_quote":"Supplies the SoC platform that Basilisk builds on."}],"review_version":1}