{"id":"953c13e4-5763-42eb-89b7-402a2fab8b89","arxiv_id":"2505.11252","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A LIF-only SNN accelerator using differential time encoding reports 99.03% MNIST accuracy on FPGA and ASIC with no multiplication operations.","lead":"This paper reports a spiking neural network accelerator that works without any multiplication, using a time-based spike encoding, and reaches over 99% accuracy on handwritten digit recognition. It also provides synthesis results for an FPGA and a 7nm ASIC, plus a proof that multiple spike streams can be merged in this encoding.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Overflow symbols break the Section IV merge proof; the merger has no spike/overflow flag, so real streams can produce false spikes and the central correctness claim is unverified.","rationale":"The reader identified the encoding-weight quantization as the weakest assumption, which is a reasonable concern but is deferred to a companion paper and does not attack the architecture's core computation. The overflow issue is more structural: it targets the paper's new mathematical contribution (Proposition 1) and the entry point of the entire accelerator. The counterexample is simple, uses the paper's own b=2 setting, and does not depend on any external baseline or training configuration. The submitted text provides no mechanism for the merger to distinguish an overflow event from a spike event, so the hardware as described would add weights at overflow-derived times and compute a different SNN than intended. A corrected proof or released bit-accurate RTL could resolve this, but as written the central correctness claim is not established and appears demonstrably flawed. For these reasons the verdict should move from CONDITIONAL to REJECT.","tokens_in":13214,"tokens_out":14291,"duration_ms":158045,"concrete_test":"Write a bit-accurate simulator of the Section V merger for b=2 with overflow value 3, feed it the explicit pair A=[3,1], B=[2] plus random streams produced by the Section VII learned encoder, apply the Proposition 1 procedure, and decode the output by cumulative sum. Compare the decoded spike times, treating every output symbol as a spike as the hardware does, against ground-truth merged spike times. If a false A-spike appears at t=3, or any overflow-derived symbol is shifted past a real spike, the merge proof does not cover the actual encoding.","verdict_should_be":"REJECT","load_bearing_attack":"Section III defines the overflow symbol (2^b-1) as 'passage of time without a spike', and Section VII uses b=2 with inter-spike differences exceeding 3 (Fig. 1), so the actual streams fed to the Section V merger contain overflows. Section IV's Proposition 1 and proof, however, model each differential set as differences of absolute spike times and never introduce overflow or a spike/overflow type bit. Applying the stated rule to such streams can turn an overflow-derived delta into what the hardware will consume as a spike. With b=2, stream A=[3,1] (overflow at t=3, only spike at t=4) and stream B=[2] (spike at t=2) merge to output [2,1,1]; interpreted as spike deltas by the layer controller and synapse index, this creates a false A-spike at t=3 and triggers weight additions from A's synapse. Fig. 4's element and Section V's controller are described with no overflow flag, and Section V explicitly says output spikes can only be triggered at input-spike times, so the overflow event must be distinguishable. Proposition 1 is therefore incomplete for the encoding actually used, and the no-multiplier, sub-millisecond MNIST/ASIC claims rest on an unverified core.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a hardware accelerator for feedforward networks of leaky integrate-and-fire (LIF) neurons whose spikes are represented by differential time intervals rather than absolute timestamps. The authors argue that differential time encoding with learned patch-based encoding is bit-efficient, prove (Proposition 1) that differential spike trains can be merged by repeatedly emitting the smallest leading delta and subtracting it from the other leading deltas, and present an FPGA/ASIC implementation with no multipliers. They report >99% accuracy on MNIST, roughly 0.29 ms FPGA inference and 0.17 ms ASIC inference using the ASAP7 PDK, and compare favorably with earlier SNN accelerators. The paper extends the authors' prior designs [4,5] with the merger proof, an explicit bit-width analysis, and synthesis results.","tokens_in":1608,"tokens_out":1871,"duration_ms":135313,"significance":"The central claims are attractive and, if fully substantiated, would make a useful contribution: a multiplier-free LIF-only inference engine, an open-source ASAP7 synthesis flow, and sub-millisecond latency on an external benchmark. Strengths include the concrete area/power/timing tables, the use of an open-source PDK and toolchain, and the stated goal of a self-contained encoding justification. However, the main correctness proof and the hardware description do not currently account for overflow symbols in the actual encoding, and several accuracy-related claims are deferred to companion papers; therefore the significance is conditional on a substantial revision.","major_comments":[{"comment":"The merger proposition is stated and proved only for ordered sets of absolute spike times, where each delta is a difference of two actual spike times. The encoding defined in Section III, however, contains an overflow symbol 2^b-1 that represents elapsed time without a spike, and Section VII deploys b=2 on MNIST streams whose inter-spike differences exceed 3 (Fig. 1). Under the stated merge rule, overflow-derived deltas are indistinguishable from real spikes. For example, with b=2, stream A=[3,1] (overflow at relative time 3, spike at time 4) and stream B=[2] (spike at time 2) merge to [2,1,1], which the layer controller would read as spikes at times 2, 3, and 4, inserting a false spike at time 3. Neither Fig. 4 nor Section V-B describes a spike/overflow flag, and Section V-B explicitly states that output spikes are triggered only at input-spike times. As written, the proof does not cover the actual encoded streams and the hardware correctness claim is unverified. The revision should either extend Proposition 1 to overflow symbols with a type bit that suppresses false spikes, or show that the deployed encoding avoids overflows (which the histogram contradicts), and should verify the corrected merger in RTL simulation.","section":"Section IV, Proposition 1; Section V, Fig. 4"},{"comment":"The bit-width cost formula is inconsistent with the stated meaning of the overflow symbol. The text says a difference d_i with 2^b-1 <= d_i < 2^(b+1)-1 requires two symbols, but Eq. (2) uses ceil(d_i/(2^b-1)) symbols, which gives one symbol for d_i = 2^b-1. This matters because the claimed optimum b=2 (Fig. 2) is computed from that formula. In addition, the histogram in Fig. 1 comes from a single 400-128-10 MNIST network, so the optimal-bit-width conclusion is an empirical statement for that configuration, not a general property; the paper should say so explicitly and, ideally, show sensitivity to network size and dataset.","section":"Section III, Eqs. (2)-(5) and Fig. 2"},{"comment":"The no-multiplier property of the accelerator depends on restricting the learned encoding weights to {-1,0,1}. The paper states that the resulting accuracy loss is almost negligible and refers to [5], but no supporting numbers appear in this manuscript. Because this restriction is load-bearing for the central lightweight-accuracy claim, the revision should report the unrestricted-weight baseline accuracy on the same networks and datasets, or reproduce the relevant comparison from [5] in sufficient detail.","section":"Section VII, learned encoding"},{"comment":"The ASIC row in Table III reports 99.03% accuracy and about 6000 inferences/s, but Section VI describes the ASIC results as informative bounds due to non-ideal SRAM placement and does not state where the 99.03% figure comes from. If this accuracy is the trained software model's accuracy rather than that of the synthesized RTL or a bit-accurate hardware simulation, that should be stated explicitly; given the overflow-handling question above, an RTL-level accuracy check is needed before the hardware can be claimed to achieve the reported accuracy.","section":"Section VI and Table III"}],"minor_comments":[{"comment":"The proof does not define a tie-breaking rule when the first elements of two input streams are equal; specify whether simultaneous spikes are emitted as consecutive zero-delay symbols and how that interacts with the merge tree.","section":"Section IV, Proposition 1"},{"comment":"The quantity K_i is used in Eq. (5) but is not explicitly defined before its first use; define it as the number of inter-spike differences equal to i in the histogram.","section":"Section III, Eq. (5)"},{"comment":"The caption says difference times but the figure is a histogram of differential times; clarify the bit width used and how overflow symbols would be represented in the histogram.","section":"Section III, Fig. 1 caption"},{"comment":"References [33] and [46] are the same paper (Lunglmayr et al., DEXA 2021) and should be merged to avoid duplicate citations.","section":"References"},{"comment":"The comparisons in Table III mix different technology nodes, power-measurement conventions, and accuracy reporting conditions; add a footnote or table note stating what is and is not directly comparable.","section":"Table III"}],"recommendation":"major_revision","confidential_remarks":"The manuscript relies heavily on the authors' own prior work: the LIF parameter choices come from [4], the learned-encoding definition and the unrestricted-weight accuracy comparison are deferred to [5], and the FPGA MNIST row is labelled 'This work [5]'. Given that [5] is accepted at ISCAS 2025, this may be acceptable, but the TVLSI submission should be self-contained on the points that support the no-multiplier and accuracy claims. The overflow gap in Proposition 1 is serious enough that I would not recommend acceptance without a revised proof and hardware description; with those in place the contribution is publishable."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The genuinely new pieces here are the formal claim for the spike merger (Proposition 1), the bit-width cost analysis, CIFAR-10 results, and an ASAP7 synthesis run with an open-source flow. The paper does well to keep the architecture concrete and to be candid that the ASIC numbers are indicative bounds. A multiplier-free, LIF-only design at 99% MNIST with sub-millisecond latency is a useful building block for edge inference, if the merger actually works.\n\nThe merger proof, though, has a real gap. Section III defines the overflow symbol as the highest representable value, and Section VII selects b=2 while the spike differences in the histogram go far beyond 3. So the actual streams fed to the merger contain overflow symbols. Proposition 1 and its proof model only differences of absolute spike times, with no overflow handling. The hardware merger in Figure 4 has no overflow flag. Concretely, with b=2, stream A=[3,1] (overflow at t=3, spike at t=4) and B=[2] (spike at t=2) merge to [2,1,1] under the stated algorithm. The layer controller then sees a spike 1 time unit after t=2, even though t=3 was an overflow. That is a false spike, producing weight updates that should not happen. The proof and the hardware description need to distinguish overflow tokens from real spikes, or the central claim “this merges differential spike streams correctly” is unverified for the encoding actually used.\n\nOther soft spots are minor by comparison. No RTL is released, so the synthesis and accuracy claims cannot be reproduced. There is no same-hardware baseline against an alternative encoding. CIFAR-10 at 55% is weak, and the comparison table mixes process nodes and power methodologies. The bit-width analysis is empirical on one trained network, which is fine for an engineering paper but should be presented as case-study evidence, not a general law.\n\nThis is not a paper to desk-reject; the underlying idea is sound and likely fixable. A serious referee should ask the authors to extend the proof to overflowing streams, add the needed hardware flag, and ideally release RTL to confirm the measured results. If they can do that, the work becomes a genuinely useful reference for low-cost SNN inference.","headline":"A concrete multiplier-free SNN accelerator, but the key merger proof ignores overflow symbols, leaving the central correctness claim unverified as written.","tokens_in":14032,"tokens_out":5136,"would_cite":false,"duration_ms":52516,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"By representing spikes as time differences, a multiplier-free LIF-only accelerator merges spike trains with a compare-and-subtract rule and reports over 99% MNIST accuracy at sub-millisecond latencies.","keywords":["spiking neural networks","LIF-only","differential time encoding","learned encoding","hardware accelerator","FPGA","ASIC","MNIST"],"falsifier":"Train the same feedforward LIF network with learned encoding on CIFAR-10 in two versions, one with encoder weights limited to $\\{-1, 0, 1\\}$ and one unrestricted, and compare test accuracy; if the unrestricted version beats the restricted one by several points (the paper reports only $55.15\\%$ for the restricted case), the premise that the ternary restriction is 'almost negligible' would be false.","tokens_in":13007,"feed_emoji":"⚡","tokens_out":13346,"duration_ms":120887,"temperature":0.7,"pith_summary":"The paper aims to show that spiking neural networks keep their efficiency advantage on real hardware when spikes are represented as time differences instead of absolute times. The central result is a multiplier-free feedforward network built only from leaky-integrate-and-fire (LIF) neurons, in which synaptic inputs are added to neuron potentials and thresholding produces output spikes. Its key hardware primitive is a spike merger that, by comparing and subtracting leading time gaps, combines any number of differential-time spike trains into one, and a proof of this merge is given. With a learned encoder whose weights are restricted to $\\{-1, 0, 1\\}$, the design reports $99.03\\%$ accuracy on MNIST, roughly $0.29\\,\\mathrm{ms}$ per inference on an Ultrascale+ FPGA, and roughly $0.17\\,\\mathrm{ms}$ on a 7-nm open-source ASIC flow, with no multipliers in either target. This matters because it suggests low-latency, low-resource SNN inference is practical on standard digital hardware.","feed_headline":"Spiking accelerator reaches 99% on MNIST with no multipliers","feed_subtitle":"Differential-time spike encoding lets a lightweight LIF-only design reach sub-millisecond inference on FPGA and ASIC.","key_machinery":"The load-bearing object is the spike merger element, a hardware block that implements Proposition 1. Given two differential-time spike trains, at each step it outputs the smaller of the two leading delta times and subtracts that value from the other train's leading delta (or refills it from the next stored spike), so the merged train is produced without ever converting to absolute time; a binary tree of these blocks merges any number of input trains. The second essential piece is the differential time format itself, where a spike is the time since the previous spike and the all-ones symbol is an overflow marker; its bit width is chosen by minimizing $b\\sum_i \\lceil d_i/(2^b-1)\\rceil$, which for the MNIST network reaches a minimum at $b=2$. The neuron core uses a decay of $\\beta = 0.5$ and threshold $\\theta = 1$, so the LIF update is a shift, an add, and a comparison; because spikes are single bits, weighted sums are conditional additions, and restricting the learned encoder weights to $\\{-1, 0, 1\\}$ keeps the encoder multiplier-free as well.","core_discovery":"The central claim is that a feedforward LIF-only SNN can be computed with additions and threshold comparisons alone without losing accuracy, provided spike trains are kept in differential time and merged by the simple rule of Proposition 1: emit the smallest leading delta and subtract it from the other trains' leads. The paper proves that this procedure yields the correct merged delta sequence, because the leading deltas of the input trains are absolute distances to a common time origin, and subtracting the emitted minimum merely shifts that origin. The design reaches $99.03\\%$ test accuracy on MNIST with a feedforward LIF network and a $9\\times 9$ learned encoding, with per-image inference time of about $0.29\\,\\mathrm{ms}$ on an Ultrascale+ FPGA and about $0.17\\,\\mathrm{ms}$ on a 7-nm ASIC implementation, both without multipliers. The paper also reports $55.15\\%$ on CIFAR-10 with the same feedforward approach, and identifies $2$ bits as the optimal delta width for the MNIST encoder under its bit-cost measure.","pith_inferences":["A direct test of the central premise would be to train the same feedforward LIF model on CIFAR-10 with and without the $\\{-1, 0, 1\\}$ encoder-weight restriction; the reported $55.15\\%$ is only the restricted result, so the 'almost negligible' gap is asserted, not shown, for this dataset.","The compare-and-subtract merger is timing-agnostic, so it could be applied directly to event-based sensor streams without the patch-serialization used for static images; this is an extension the paper does not pursue.","Because the ASIC synthesis used only small SRAM macros from the open-source flow, the reported $0.17\\,\\mathrm{ms}$ and $538\\,\\mathrm{MHz}$ are presented as bounds; optimized wider SRAMs would likely shift both, an effect the authors flag but do not quantify.","The bit-cost function $b\\sum_i \\lceil d_i/(2^b-1)\\rceil$ could be recomputed at runtime to adapt the delta width per layer or input distribution, something the fixed-2-bit design does not do."],"forward_implications":["Feedforward LIF-only SNNs can be implemented on FPGAs and ASICs without any DSP slices: spike-weighted sums are conditional adds, and the ternary encoder adds only additions and subtractions.","The differential time representation with an overflow symbol is never worse than absolute time in bit count and can be much better for evenly spaced spikes; a 2-bit width suffices for the MNIST encoder.","The Proposition 1 merger tree works for any number of input spike trains, so the same architecture can process event-camera or level-crossing ADC streams without converting spikes to absolute time.","Because each network layer is directly instantiated and runs on the same merged event stream, deeper and wider feedforward LIF networks can be added at the cost of more merger-tree LUTs and weight memory, not more multipliers."],"supporting_citations":[{"why":"preceding accelerator and learned-encoding design that this paper extends and proves.","marker":"[5]"},{"why":"established the LIF-only differential-time processing and the beta=0.5, theta=1 settings used here.","marker":"[4]"},{"why":"introduced the differential time spike representation that the whole architecture uses.","marker":"[33]"},{"why":"supplies the 7-nm predictive PDK used for the ASIC synthesis.","marker":"[8]"},{"why":"provides the MNIST dataset for the main accuracy and latency results.","marker":"[6]"},{"why":"provides the CIFAR-10 dataset used to show the learned encoding beyond MNIST.","marker":"[7]"},{"why":"FPGA baseline (SyncNN) used in the comparison table to highlight speed and zero DSP blocks.","marker":"[26]"},{"why":"ASIC baseline used in the comparison table for accuracy, area, and power context.","marker":"[42]"}],"fun_headline_variants":["No-multiplier spiking chip hits 99% on MNIST","Differential-time spiking cuts MNIST inference to 0.29ms","LIF-only accelerator: 99% MNIST, no multiplications","Spiking NN without multipliers: sub-ms inference on FPGA","Differential-time encoding enables LIF-only spiking accelerator"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central premise is that restricting the learned encoder's weights to $\\{-1, 0, 1\\}$ costs almost no accuracy, a claim the paper inherits from its earlier work rather than demonstrating here; if the gap turns out large on other data or training setups, the 'lightweight with high accuracy' claim loses its basis.","fun_headline_variants_meta":{"raw":{"variants":["No-multiplier spiking chip hits 99% on MNIST","Differential-time spiking cuts MNIST inference to 0.29ms","LIF-only accelerator: 99% MNIST, no multiplications","Spiking NN without multipliers: sub-ms inference on FPGA","Differential-time encoding enables LIF-only spiking accelerator"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000817,"raw_usage":{"total_tokens":3594,"prompt_tokens":978,"completion_tokens":2616,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":594,"completion_tokens_details":{"reasoning_tokens":2523}},"tokens_in":594,"tokens_out":2616,"duration_ms":19517,"temperature":1.0,"reasoning_tokens":2523,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T20:54:42.630566+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Train the same feedforward LIF network with learned encoding on CIFAR-10 in two versions, one with encoder weights limited to $\\{-1, 0, 1\\}$ and one unrestricted, and compare test accuracy; if the unrestricted version beats the restricted one by several points (the paper reports only $55.15\\%$ for the restricted case), the premise that the ternary restriction is 'almost negligible' would be false.","supporting_citations":[{"cited_title":"Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding","cited_arxiv_id":"2501.07952","evidence_quote":"preceding accelerator and learned-encoding design that this paper extends and proves."},{"cited_title":"Robust and efficient bio- inspired data-sampling prototype for time-series analysis,","cited_arxiv_id":null,"evidence_quote":"introduced the differential time spike representation that the whole architecture uses."},{"cited_title":"Asap7: A 7-nm finfet predictive process design kit,","cited_arxiv_id":null,"evidence_quote":"supplies the 7-nm predictive PDK used for the ASIC synthesis."},{"cited_title":"A 4096-neuron 1m-synapse 3.8-pj/sop spiking neural network with on-chip stdp learning and sparse weights in 10-nm finfet cmos,","cited_arxiv_id":null,"evidence_quote":"ASIC baseline used in the comparison table for accuracy, area, and power context."}],"review_version":1}