{"id":"166035e4-6fcb-4850-a2fc-eb40da9f1ecb","arxiv_id":"2505.12960","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"A hardware-adaptive training algorithm for memristor Hopfield networks improves fault tolerance, doubles to triples capacity, and with multilayer extensions gives superlinear capacity scaling for binary and continuous patterns.","lead":"This paper trains memristor-based Hopfield networks with a hardware-aware loss, so associative memories keep working when many devices are broken. Stacking the network into multiple layers makes storage capacity grow faster than the number of neurons and also handles continuous patterns.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Capacity and fault-tolerance claims hinge on basin sizes that are neither trained nor proven; a single noise level in the capacity metric does not establish robust associative recall.","rationale":"The reader's weakest assumption is that fixed-point training yields sufficiently large basins of attraction and that the synchronous, asymmetric, multilayer dynamics converge. My stress-test identifies the same load-bearing point: the training loss on clean patterns does not control the behavior on corrupted inputs, the capacity metric is evaluated at a single noise level, and no convergence or basin-size analysis is provided. A concrete test varying noise severity and checking for non-convergent behavior near the claimed capacity would directly settle whether the empirical capacity exponents represent robust associative recall. Since the reader already issued a CONDITIONAL verdict with this concern, my analysis does not change the verdict; it sharpens the condition under which the central claim should be accepted.","tokens_in":15374,"tokens_out":4398,"duration_ms":56055,"concrete_test":"Train multilayer networks at N=784 (binary) and N=400 (continuous) for P equal to 50%, 75%, 90%, and 100% of the claimed capacity. For each configuration, present corrupted inputs at flip probabilities 0.05, 0.1, 0.2, and 0.3, and Gaussian noise levels σ=0.3, 0.6, and 1.0. Run the recurrent dynamics for at most 100 iterations and record the fraction of trials that converge to the correct stored pattern (cosine similarity >0.99) and the fraction that enter limit cycles or fail to converge. If retrieval success degrades sharply, or non-convergent dynamics appear, as P approaches the reported capacity, the superlinear capacity claim does not hold as an associative memory guarantee.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim of superlinear capacity (∝N^1.49 for binary, ∝N^1.74 for continuous) and the 3× fault-tolerance advantage depend on the recurrent dynamics converting corrupted inputs into the correct stored patterns. However, the training objective in Eqs. (5)–(6) only minimizes the distance between each stored pattern and the network output on the clean pattern itself. It does not train on corrupted inputs, and no theory is provided for the size of basins of attraction, convergence, or absence of oscillations for the recurrent map, which has asymmetric weights and synchronous updates. The reported capacity is measured at one fixed noise level — 5% bit flips for binary patterns and Gaussian noise with σ=0.6 for continuous patterns — with cosine similarity >0.99 as the success criterion. This single operating point does not reveal whether basins shrink as N or the number of stored patterns grows, nor whether the dynamics remain convergent near the claimed capacity limits. If basins become small or oscillatory cycles appear as capacity is approached, the fitted power-law exponents would overstate the useful associative memory capacity of the system. The fault-tolerance result is likewise reported at specific stuck-at-fault ratios without a demonstration that the advantage persists across fault patterns and noise levels.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a hardware-adaptive learning algorithm for memristor-based Hopfield networks (HNNs) for associative memory. Instead of using a fixed rule such as Hebbian or pseudo-inverse learning, the method trains the weights by gradient descent to make each stored pattern a stable fixed point under the recurrent update, using a tanh surrogate for the sign nonlinearity and a hardware-calibrated crossbar model that masks stuck-at-fault devices. The authors extend the approach to a two-layer recurrent architecture and demonstrate retrieval of binarized MNIST patterns on an integrated 64x64 memristor crossbar, with additional simulations of larger networks. They report that the method roughly triples capacity relative to a pseudo-inverse baseline at 50% stuck-at faults, and that the multilayer extension gives capacity scaling approximately proportional to N^1.49 for binary MNIST and N^1.74 for continuous MNIST patterns, versus roughly linear scaling for single-layer HNNs. The paper also reports energy and latency advantages of synchronous updates over asynchronous updates.","tokens_in":15608,"tokens_out":4746,"duration_ms":57080,"significance":"If the claims hold, this would be a useful engineering advance for memristor-based associative memory: it combines defect-aware training, multilayer recurrent architectures, continuous-valued patterns, and hardware demonstrations on an integrated crossbar. The paper includes a hardware prototype, open code, and comparisons against several classical learning rules, which are strengths. However, the central capacity and fault-tolerance claims are empirical power-law fits and hardware-model simulations rather than derived guarantees, and no comparison is made with modern dense associative memory models that already achieve superlinear or exponential capacity, so the novelty and robustness of the 'superlinear capacity' claim remain uncertain..","major_comments":[{"comment":"The training objective in Eqs. (5)-(6) enforces only that each stored pattern is approximately a fixed point; it contains no term for corrupted inputs, and the paper provides no analysis of basin size, convergence, or possible limit cycles for the synchronous, asymmetric-weight recurrent dynamics. Capacity is defined at a single operating point (5% random bit flips for binary patterns, Gaussian noise with sigma=0.6 for continuous patterns, cosine similarity >0.99), so the fitted power-law exponents may overstate useful associative memory capacity if basins shrink or oscillations appear as N or the number of stored patterns grows. This is load-bearing for the abstract's central claims, and I ask the authors to report capacity as a function of noise level, verify convergence at and beyond the claimed capacity limits, and either provide a theoretical convergence/basin argument or clearly frame the results as empirical with these caveats.","section":"Hardware-Adaptive Learning Algorithm; Pattern Retrieval Experiment (Eqs. 5-6, Fig. 3i-3j)"},{"comment":"The scaling exponents 1.49, 1.74, 1.06, and related values are fitted power-law exponents, but the manuscript reports no confidence intervals, no goodness-of-fit statistics, and no model comparison against, e.g., logarithmic or sublinear alternatives. The fits appear to be based on a small number of input sizes, and for MNIST the correlation structure of the patterns changes with resolution/preprocessing, so the comparison between single-layer and multilayer exponents may reflect the dataset rather than an architectural property. Please provide the raw capacity data for all points, error bars from repeated experiments, fitted exponents with uncertainties, and a sensitivity analysis with respect to the capacity threshold.","section":"Fig. 4(f), Fig. 5(f); Results on capacity scaling"},{"comment":"The paper claims superlinear capacity scaling as a central contribution, but it does not compare against dense associative memory models or modern Hopfield networks, which in the cited literature already achieve superlinear or exponential storage capacity. Because the claim is framed as a fundamental improvement over 'previous HNNs' rather than over classical Hebbian/pseudo-inverse rules, the absence of such a comparison leaves the novelty and significance of the capacity result unclear. I ask for a quantitative comparison under the same capacity metric and hardware constraints, or, failing that, a clearly scoped statement that the comparison is only against classical single-layer Hopfield networks.","section":"Introduction and Discussion; related work (Refs. 9,10)"},{"comment":"The fault-tolerance experiments model stuck-at-fault devices by setting the corresponding weights to zero during training, but a physical memristor stuck-at-fault is typically a stuck-on or stuck-off conductance, not a zero weight. Unless the differential-pair encoding or readout scheme makes a stuck device equivalent to a zero contribution, the claimed 3x effective capacity under 50% device faults may not transfer to actual hardware faults. The manuscript should either clarify the mapping, demonstrate fault injection with realistic stuck-on/stuck-off conductances, or explicitly restrict the claim to zero-conductance faults.","section":"Methods: Hardware-Adaptive Training Algorithm; Fig. 3(h-j)"}],"minor_comments":[{"comment":"The heading contains a typo: 'multiplayer network' should be 'multilayer network'.","section":"Heading 'Continuous Patterns associative Memory'"},{"comment":"The word 'periphral' appears in the first sentence of the Methods section and should be corrected to 'peripheral'.","section":"Methods: Memristor Integration"},{"comment":"Equation (3) includes a bias term b, but Eq. (5) omits it; please clarify whether the bias is trained and included in the hardware mapping or intentionally set to zero.","section":"Eqs. (3)-(5)"},{"comment":"The figure captions and text do not clearly state which capacity curves are from physical hardware measurements and which are from the calibrated crossbar model; this distinction should be explicit in the captions and main text.","section":"Fig. 3(i,j) and capacity measurements"},{"comment":"The tanh steepness parameter lambda is set to 1 without a sensitivity analysis; because the loss landscape and fixed-point accuracy may depend on lambda, a short study of its effect would strengthen the method's robustness claims.","section":"Eq. (4) and Methods"},{"comment":"The text says corrupted inputs are generated by flipping 10% of pixels in the demonstration, while the capacity metric uses 5% flips; please clarify that these are different protocols and motivate the choice of 5% for capacity measurements.","section":"Fig. 3(e) and capacity definition"}],"recommendation":"major_revision","confidential_remarks":"The paper's main results rest on empirical scaling exponents and simulated fault-masking rather than theoretical guarantees, and the related-work section cites modern dense associative memories without benchmarking against them. I would recommend that the editor require the requested comparisons and robustness analyses before considering the paper for publication; the hardware demonstration itself is valuable and worth preserving through revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThe short version: this is a genuine hardware paper with a working integrated memristor Hopfield system, and the hardware-adaptive training with stuck-at-fault masking is a real step forward. But the headline \"superlinear capacity\" is an empirical power-law fit from simulations, not a derived result, and the paper never compares against the dense Hopfield models that already give superlinear or exponential capacity in software.\n\nWhat is genuinely new: they train HNN weights by minimizing a fixed-point loss (Eq. 5) on clean patterns, using a calibrated crossbar model that masks known stuck-at faults, then deploy the weights on a real CMOS-integrated 64x64 memristor array. The small-scale retrieval experiments look credible: 10% flips recover stored MNIST patterns within a few synchronous iterations, conductance maps match targets, and they quantify programming noise. The multilayer extension is a nice engineering trick: a bottleneck hidden layer gives higher capacity on correlated patterns with fewer memristors, and they show continuous-pattern recall on hardware. The synchronous-update latency and energy numbers are striking (99%+ latency reduction), though these are estimates for a 64-neuron system, not measured at scale.\n\nThe soft spots are concentrated where the abstract oversells. The exponents (∝N^1.49, ∝N^1.74) are fitted to a few points on MNIST with no confidence intervals, and there is no comparison to dense Hopfield networks—whose papers they cite but never bench against. The training objective only enforces clean patterns as fixed points; it does not train on corrupted inputs or analyze basins of attraction. Since capacity is measured at one noise level (5% bit flips; Gaussian σ=0.6) with a cosine >0.99 threshold, we don't know whether basins shrink as N or pattern count grows. For the single-layer case, capacity is still linear (2x better than pseudo-inverse), which is honest; the superlinear multiplier comes entirely from multilayer compression and only shows on correlated MNIST. Also, the stuck-at-fault handling is underspecified: they mask fault locations to zero weights in the model, but a real stuck device would contribute a nonzero conductance. Maybe they only used devices stuck at zero; the text doesn't say.\n\nNone of this kills the paper. The hardware demonstration stands on its own. But the capacity claims need dense-Hopfield baselines, error bars, and some discussion of basins before they can be taken as architectural laws rather than fitting curves.\n\nI think this deserves serious peer review. The experiments are there, code is public, and the adaptive-training idea is worth careful attention. A conditional accept with requests for baselines, error bars, and basin analysis would be the right outcome.","headline":"Real hardware, adaptive training, and credible small-scale retrieval, but the superlinear-capacity exponents are empirical fits that need baselines and basin-size analysis before they carry the load.","tokens_in":16143,"tokens_out":3310,"would_cite":true,"duration_ms":36564,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A hardware-adaptive training rule triples defect-ridden memristor memory capacity and gives Hopfield networks superlinear storage scaling.","keywords":["associative memory","Hopfield network","memristor crossbar","hardware-adaptive training","stuck-at-fault tolerance","multilayer recurrent network","continuous patterns","capacity scaling"],"falsifier":"Retrieve a pattern from the trained multilayer network while increasing the corruption rate from 5% to 40% pixel flips; if retrieval accuracy collapses at corruption rates where the single-layer network still succeeds, the superlinear-capacity claim would not correspond to robust associative recall. A second check is to measure whether every stored pattern is still a fixed point after applying the measured conductance variation ($\\sigma \\approx 3.9\\,\\mu\\text{S}$), since the training loss only guarantees fixed points at the converged target weights.","tokens_in":15173,"feed_emoji":"🧠","tokens_out":6396,"duration_ms":59056,"temperature":0.7,"pith_summary":"This paper claims that associative memory in memristor hardware stops being fragile and capacity-limited once the Hopfield network weights are trained by gradient descent on a fixed-point objective that is calibrated to the actual device array. The same training rule, extended to a network with a hidden layer, makes storage capacity grow superlinearly with neuron count for correlated patterns and lets the memory store continuous-valued patterns, which classical sign-activation Hopfield networks cannot. If correct, memristor-based associative memories become practical for pattern completion under hardware faults, with much higher capacity per device and flexible capacity tuning by choosing hidden-layer size. The claims are backed by experiments on integrated 64x64 memristor crossbars.","feed_headline":"Memristor memory triples capacity with half devices broken","feed_subtitle":"Hardware-aware Hopfield training also scales capacity superlinearly and recalls continuous patterns.","key_machinery":"The load-bearing object is the fixed-point training objective. At a stored fixed point, $X = \\mathrm{sgn}(WX+b)$; replacing sgn by tanh makes the objective differentiable, so gradient descent can drive every stored pattern toward being a fixed point while respecting a mask of stuck-at-fault devices in the crossbar model. In the multilayer version the same loss is applied to the full two-layer map $f(\\xi^m)$, and the hidden layer acts as a data compressor, which is what the paper credits for superlinear capacity and continuous-pattern support.","core_discovery":"The paper's central claim is that a Hopfield network can be made hardware-adaptive by treating associative-memory storage as an optimization problem: minimize the squared distance between each stored pattern and its relaxed one-step update, $\\tanh(W\\xi^m+b)$, instead of using Hebbian or pseudo-inverse weight formulas. Because the objective is differentiable, the weights can be trained with gradient descent through a crossbar model that masks stuck-at-fault devices, so the remaining devices compensate for the broken ones. The paper further claims that the same loss, applied to a two-layer recurrent network with a hidden layer whose output feeds back, gives a system whose capacity scales as $\\propto N^{1.49}$ for correlated binary patterns and $\\propto N^{1.74}$ for continuous patterns, versus roughly linear scaling for single-layer Hopfield networks, and that synchronous updates on memristor hardware cut energy and latency dramatically.","pith_inferences":["The mechanism suggests that any compute-in-memory substrate whose non-idealities can be modelled, not just oxide memristors, could inherit the same defect tolerance, since the training objective is substrate-agnostic once a mask is available.","Because training enforces only clean-pattern fixed points, the reported capacity numbers likely depend on the corruption level used to define 'retrievable'; a testable extension would be to include noisy or partial patterns in the loss and measure whether basin size increases.","The superlinear exponent appears tied to pattern correlation: the paper itself reports a much weaker advantage ($\\propto N^{1.11}$ vs $\\propto N^{1.06}$) for random patterns, so the practical gain depends on how structured the stored data are; applying the same architecture to other correlated datasets would probe that dependence."],"forward_implications":["Storing patterns in a memristor Hopfield network no longer requires fault-free or precisely programmed devices; the training loop compensates for stuck-at-fault locations, and the paper reports triple the capacity of the pseudo-inverse baseline when 50% of devices are stuck.","Adding one hidden layer with the same synapse count turns the capacity scaling from linear to superlinear ($\\propto N^{1.49}$ on correlated MNIST binary patterns), so larger memories need not demand quadratically more devices for the same pattern size.","Continuous-valued patterns become storable and retrievable through the multilayer tanh dynamics, with capacity scaling $\\propto N^{1.74}$, a capability conventional sign-based Hopfield networks lack.","Capacity can be tuned by changing hidden-neuron count at fixed input dimension, and the hidden layer reduces required memristors by 43.7% to 95% for small pattern sets.","Synchronous updates exploit memristor parallelism, cutting latency by up to 99.7% and improving energy efficiency by up to 8.8x compared with asynchronous update schemes reported earlier."],"supporting_citations":[{"why":"Introduces the Hopfield network and its associative-memory dynamics, the architecture this paper retrains.","marker":"[5]"},{"why":"Defines pseudo-inverse learning, the state-of-the-art baseline whose capacity and fault tolerance this paper compares against.","marker":"[43]"},{"why":"Shows Hopfield learning rules can be cast as objective-function minimization, the basis of the paper's differentiable fixed-point loss.","marker":"[44]"},{"why":"Supplies the experimentally validated crossbar model with defect-aware training that lets the algorithm mask stuck-at-fault devices.","marker":"[45]"},{"why":"Describes the CMOS-integrated oxide memristor process used to build the hardware on which the method is demonstrated.","marker":"[46]"},{"why":"Provides equilibrium-propagation memristor recurrent network results used as a baseline in capacity comparisons.","marker":"[47]"},{"why":"Another memristor training baseline (activity-difference training) compared in the retrieval-quality experiments.","marker":"[48]"},{"why":"Supports the multilayer extension by showing overparameterized neural networks can implement associative memory.","marker":"[52]"}],"fun_headline_variants":["Hardware-adaptive memristor memory resists faults, scales superlinearly","Memristor Hopfield net: 3x capacity under half faults, 8.8x less energy","Self-healing memristor memory boosts capacity, cuts energy 8.8x","Defect-tolerant memristor associative memory scales superlinearly","Memristor network survives broken devices, recalls continuous patterns"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument assumes that patterns made into fixed points by the squared-distance loss also have large enough basins of attraction that corrupted inputs converge back to them, and this is not proven for the multilayer dynamics with asymmetric weights and synchronous updates.","fun_headline_variants_meta":{"raw":{"variants":["Hardware-adaptive memristor memory resists faults, scales superlinearly","Memristor Hopfield net: 3x capacity under half faults, 8.8x less energy","Self-healing memristor memory boosts capacity, cuts energy 8.8x","Defect-tolerant memristor associative memory scales superlinearly","Memristor network survives broken devices, recalls continuous patterns"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000625,"raw_usage":{"total_tokens":2927,"prompt_tokens":1015,"completion_tokens":1912,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":631,"completion_tokens_details":{"reasoning_tokens":1808}},"tokens_in":631,"tokens_out":1912,"duration_ms":13791,"temperature":1.0,"reasoning_tokens":1808,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T20:23:22.678850+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Retrieve a pattern from the trained multilayer network while increasing the corruption rate from 5% to 40% pixel flips; if retrieval accuracy collapses at corruption rates where the single-layer network still succeeds, the superlinear-capacity claim would not correspond to robust associative recall. A second check is to measure whether every stored pattern is still a fixed point after applying the measured conductance variation ($\\sigma \\approx 3.9\\,\\mu\\text{S}$), since the training loss only guarantees fixed points at the converged target weights.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Introduces the Hopfield network and its associative-memory dynamics, the architecture this paper retrains."},{"cited_title":"& Manton, J","cited_arxiv_id":null,"evidence_quote":"Shows Hopfield learning rules can be cast as objective-function minimization, the basis of the paper's differentiable fixed-point loss."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the experimentally validated crossbar model with defect-aware training that lets the algorithm mask stuck-at-fault devices."},{"cited_title":"electronic materials5, 1800876 (2019)","cited_arxiv_id":null,"evidence_quote":"Describes the CMOS-integrated oxide memristor process used to build the hardware on which the method is demonstrated."},{"cited_title":"& Corinto, F","cited_arxiv_id":null,"evidence_quote":"Provides equilibrium-propagation memristor recurrent network results used as a baseline in capacity comparisons."},{"cited_title":"D., Williams, R","cited_arxiv_id":null,"evidence_quote":"Another memristor training baseline (activity-difference training) compared in the retrieval-quality experiments."},{"cited_title":"& Uhler, C","cited_arxiv_id":null,"evidence_quote":"Supports the multilayer extension by showing overparameterized neural networks can implement associative memory."}],"review_version":1}