{"id":"4f482664-3a1a-4b59-92fb-3b27b521d837","arxiv_id":"2505.13049","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Physics-Aware Compilation (PAC) speeds up neutral atom quantum circuit compilation by partitioning both the hardware plane and the circuit graph, achieving up to 202.81x faster solving than DPQA with comparable circuit depth.","lead":"This paper presents a compilation method for neutral atom quantum computers that splits the hardware and circuit into independent regions, cutting compilation time by up to roughly 200x while keeping circuit depth about the same. It matters because slow compilation is a practical bottleneck for neutral atom systems as they scale up.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The reported speedups presuppose that the independently compiled regions never violate the Rydberg restriction zone, yet no constraint or validation checks inter-region or resolved-SLM distances; a distance violation would invalidate the parallel schedule.","rationale":"The reader's conditional verdict is appropriate. I examined the strongest claim, that PAC achieves large speedups with comparable depth, and the weakest link is the validity of the parallel schedule rather than the compilation-time measurement. Section 3.2 declares regional independence without checking distances, and the constraints in Eqs. (2)-(5) do not enforce a minimum separation between active-gate locations and resolved SLM qubits during the global phase, nor between simultaneous local gates across the region boundary. If violations exist, PAC's schedules are not physically executable, so the comparison against DPQA would be invalid. The concrete distance audit would settle this. I also note a separate reproducibility defect: Algorithm 3's termination condition 'n_iter <= Max_iter' and its failure to update E1/E2/E3 after swaps make the published pseudocode unable to reproduce the ablation in Figure 8. That is concerning but secondary. The distance audit is the more central check: if it passes, the empirical claims stand; if it fails, the verdict should be REJECT. Since the current CONDITIONAL verdict already anticipates additional validation, I leave the verdict unchanged.","tokens_in":24133,"tokens_out":14843,"duration_ms":162106,"concrete_test":"Run a geometric audit on the released PAC code for rand3reg_70_1 on the 16x16 array: for each time step of the merged schedule, compute all pairwise distances between atoms that are not jointly executing a two-qubit gate, and flag any pair closer than the Rydberg blockade/restriction-zone radius used by DPQA, including the diagonal boundary pair between Region 1's (7,7) cell and Region 2's (8,8) cell. If any violation is found, the regional independence assumption fails and the reported schedule is not executable on the modeled hardware.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim, that PAC preserves DPQA-quality schedules while being orders of magnitude faster, rests on the Section 3.2 assertion that 'AOD arrays in separate regions can operate independently without interference.' This is asserted, not derived. Algorithm 1 partitions the array into two diagonal quadrants, so simultaneous gate sites in Region 1 and Region 2 can be separated by only one diagonal step of the discretized grid. Whether that separation exceeds the Rydberg blockade/restriction-zone radius used in DPQA is never stated or checked. More importantly, during the global phase, resolved qubits are parked in SLM traps, but Eq. (3) only forbids active qubits from occupying the exact same SLM coordinate; no constraint keeps a resolved SLM qubit out of the restriction zone of a two-qubit gate being executed by active qubits. Because the local-phase solves are independent, nothing couples their gate locations. If two simultaneous gates in different regions, or a global-phase gate near a parked resolved qubit, violate the parallel execution constraint defined in Section 2.1, DPQA's globally solved schedules would enforce that constraint while PAC's merged schedule would not, making the speedup and depth comparison a comparison against an invalid schedule.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes Physics-Aware Compilation (PAC), a compile-time optimization for neutral atom quantum computers with AOD/SLM trap architectures. PAC splits the hardware plane into two diagonal regions and, using an improved Kernighan–Lin algorithm, partitions the input commuting circuit into local sub-circuits (one per region) and a global sub-circuit crossing regions. The local sub-circuits are compiled independently in parallel, resolved qubits are parked in SLM traps, and the remaining global sub-circuit is compiled over the whole array; the results are merged into a single schedule. The authors evaluate PAC against the DPQA baseline on random 3-regular graph circuits (60–90 qubits) across array sizes from 16×16 to 64×64, reporting up to 78.5× speedup on 16×16, up to 202.81× on 24×24, and comparable average circuit depth (e.g., 12.6 vs. 12 on 16×16), with code made openly available.","tokens_in":24389,"tokens_out":8679,"duration_ms":80966,"significance":"If the reported results are valid, PAC addresses a real bottleneck: DPQA-style solver-based compilation of neutral atom circuits can take thousands of seconds for 70–80 qubits, and a method that cuts this to tens or hundreds of seconds while preserving circuit depth would be practically valuable for QAOA and related commuting-circuit workloads. The paper has several strengths: it is evaluated on the same benchmark family as the baseline, it compares against an external state-of-the-art method rather than a self-derived variant, the open-sourced code supports reproducibility, and the decomposition idea is intuitive and plausible. However, the central physical-validity claim—that the independently compiled local regions can be executed in parallel without interference—is asserted rather than demonstrated, and the experimental presentation has gaps (inconsistent baseline timings, incomplete quality comparison for timeout cases) that must be addressed before the speedup and quality claims can be accepted.","major_comments":[{"comment":"The load-bearing premise that the two local regions can be compiled and executed independently without physical interference is not established. The parallel execution constraint in §2.1 requires that no third qubit be within a certain vicinity of any two-qubit gate. Algorithm 1 compiles QC1 on A1 and QC2 on A2 as separate subproblems with no cross-region constraint on gate placement, and the two regions are diagonal quadrants whose boundary sites are one grid step apart; whether that distance exceeds the restriction-zone radius is never stated or verified. Similarly, in the global phase, Eq. (3) only forbids an active qubit from occupying the same SLM coordinate as a resolved qubit; it does not keep a resolved SLM-trapped qubit out of the restriction zone of an active two-qubit gate. Consequently the merged schedule produced by PAC may violate the parallel execution constraint even if each sub-schedule is internally valid, while DPQA's global solve enforces that constraint. The reported speedups and depth comparisons could therefore be against a schedule that is not executable on hardware. Please add explicit distance constraints between regions and between resolved and active qubits (or a post-hoc validation of the merged schedule against the §2.1 constraints), and report the physical discretization spacing used in the experiments.","section":"§3.2, Algorithm 1, Eq. (3)"},{"comment":"The DPQA baseline timings are inconsistent across tables for the same circuits. For example, rand3reg_70_0 is reported as 2906.7 s in Table 1 but 5539.06 s in Table 2 on a 16×16 array, and rand3reg_80_3 is 9696.3 s in Table 1 but times out (TO) in Table 2. The paper does not state whether Table 1 reproduces numbers from the DPQA publication, whether Tables 2–3 and C.4–C.7 are runs on the authors' own machine, or why the environment differs. Since every speedup ratio is computed against these baseline times, the provenance and reproducibility of the DPQA timings is essential. Please clarify the source of each DPQA timing, report the machine and software versions used for both PAC and DPQA, and, if feasible, report variance over repeated runs.","section":"Tables 1 and 2"},{"comment":"The claim that PAC 'maintains comparable circuit quality' is only supported for circuits on which DPQA terminates within the 10,000 s timeout (mostly 60–70 qubits and a few 80-qubit cases). For 90-qubit circuits, DPQA times out in every configuration and no baseline depth (N_L,baseline) is available, so the layer-reduction ratio in Eq. (6) is undefined. The abstract and highlights state the quality claim unconditionally. Please restrict the quality-comparison claim to the DPQA-solvable subset, or provide a fair proxy for the timeout cases (for example, the best depth found by DPQA within a bounded budget, or a theoretical depth lower bound), and explicitly state which circuits enter each average.","section":"§4.2, Tables 2–3, abstract"}],"minor_comments":[{"comment":"The termination condition `if (Q_s1 == {} and Q_s2 == {}) or not swap_flag or n_iter ≤ Max_iter then break` is inverted: with n_iter initialized to 0, the condition `n_iter ≤ Max_iter` is true immediately, so the loop never performs a swap. The accompanying text describes continuing until the swap limit is reached; the pseudocode should use `n_iter > Max_iter` (or `>=`).","section":"Algorithm 3"},{"comment":"The pseudocode contains a duplicated branch (`e[0] in Q1 and e[1] in Q2`) and the set-update lines such as `Qa1∪{e[0]};` do not assign the result back to Qa1. These should be `Qa1 = Qa1 ∪ {e[0]}` and the second occurrence of the Q1/Q2 branch should be removed.","section":"Algorithm 2"},{"comment":"The free parameters k in Eq. (1) and Max_iter in Algorithms 2–3 are never given values for the experiments, and the partition ratio is fixed at 1/2 without discussion. Please report the chosen values and, ideally, a brief sensitivity analysis for k.","section":"§3.3 and Appendix B"},{"comment":"All timings appear to be single runs with no error bars or repeated measurements. Since the speedup figures are central to the paper, please either provide statistics over multiple runs (at least three) or explicitly justify why single-run measurement is appropriate for the comparison.","section":"Appendix B"},{"comment":"The y-axis label in Figure 7 is rendered as a series of escaped Unicode tokens (`/uni00000034/...`), and Figure 9's y-axis description is incomplete. The figures should be regenerated with readable labels.","section":"Figures 7 and 9"},{"comment":"The Discussion acknowledges the limitation of equal-size partitioning and suggests future work on circuit-aware and fidelity-aware strategies, but it does not mention the restriction-zone/inter-region interference issue raised in the major comments; this should be listed as a limitation or resolved by the requested validation.","section":"§5"},{"comment":"There is a typo, 'as qquantum circuits continue to grow', which should be corrected to 'as quantum circuits'.","section":"§2.3"},{"comment":"The abstract highlights a 78.5× speedup on 16×16 arrays while the Highlights and Section 5 also cite 202.81× from the 24×24 configuration; please ensure the headline numbers are presented with their array sizes consistently throughout the paper.","section":"Abstract and Highlights"}],"recommendation":"major_revision","confidential_remarks":"The paper is within scope for a quantum compilation / quantum systems venue and the open-sourced code is a clear plus. The central concern is not circularity or hype but a genuine physics-validity gap in the partitioning argument: the asserted independence of the two local regions is not checked against the parallel execution constraint. This is fixable by adding constraints or a validation step, which is why I am recommending major revision rather than rejection. Please also ask the authors to reconcile the DPQA timing discrepancies between Table 1 and Tables 2–3; an unexplained baseline change could overstate the speedups."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two things you should know. The speedup claim is plausible and the data is consistent: splitting the Max-SAT solve into two smaller local problems plus one global solve should cut solver time, and PAC delivers 50-200x across array sizes from 16x16 to 64x64. The problem is that the paper never establishes that the merged parallel schedule is physically valid. Region 1 and Region 2 are diagonal quadrants of the array; simultaneous gates near the boundary can be one diagonal grid step apart. The restriction zone from the parallel execution constraint (Section 2.1) is never checked across the boundary, and the assertion that 'AOD arrays in separate regions can operate independently without interference' conflates AOD channel independence with Rydberg blockade distance. Whether the boundary separation violates the restriction zone depends on the radius, which the paper never states. If the merged schedule is invalid, the comparison to DPQA is against an invalid schedule.\n\nThe stress-test's second concern—resolved SLM qubits in the global phase—is weaker: a DPQA-style solver would normally enforce the parallel execution constraint for all qubits, but the paper does not say the global solver does that, so the lack of an explicit statement is still a clarity gap worth fixing.\n\nWhat is genuinely new: the two-phase local/global compilation with resolved-versus-active qubit classification, and the improved Kernighan-Lin loss function that trades active qubit count against cross-region edges. The ablation in Figure 8 shows the loss decreasing over iterations with compilation time dropping in step, which is honest evidence that the circuit division is doing the work. The comparison against DPQA uses the same 3-regular graph benchmarks, and circuit depth is roughly maintained where DPQA completes.\n\nSoft spots, in order of seriousness. First, the inter-region restriction-zone gap is load-bearing; fix it with a constraint, a buffer zone, or a post-hoc validity check, and state the radius. Second, the depth comparison only covers circuits where DPQA finishes, mostly 60-70 qubits; for 80-90 qubits we only have PAC's depths, so 'comparable quality' is only partially supported. Third, Algorithm 3's termination condition as written (`n_iter ≤ Max_iter`) stops after one swap, which contradicts the multi-iteration ablation; it should be `≥`. That is a pseudocode bug, likely not an implementation bug, but it needs fixing. Fourth, single runs with no error bars. Solver timings are noisy, so this matters a little. Fifth, the paper says code is available but gives no link. Sixth, no comparison against PARALLAX, which they cite.\n\nThis is for compiler researchers working on neutral atom platforms, not for a broad theory audience. It addresses a real bottleneck, and the central speedup claim is credible. It deserves a serious referee, and the referee should push on the physical validity of the merged schedules. If the authors can close that gap, this is a conditional accept. I would bring it to the reading group.","headline":"A real engineering contribution to neutral atom compilation with consistent speedup data, but the physical validity of its parallel schedules is asserted, not checked, and the main claim needs referee scrutiny before it can be trusted.","tokens_in":24899,"tokens_out":9243,"would_cite":true,"duration_ms":87876,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"PAC claims that partitioning the neutral-atom trap plane and the circuit into independent regions compiles commutable 60–90 qubit circuits tens to hundreds of times faster than DPQA while preserving circuit depth.","keywords":["Neutral Atom Quantum Computing","Quantum Compilation","Qubit Mapping","Physics-Aware Optimization","Parallel Circuit Execution","Hardware Plane Partitioning","Kernighan-Lin Algorithm"],"falsifier":"Take a PAC-produced schedule for any benchmark circuit and compare, for every time step, the positions of qubits executing two-qubit gates in Region 1 with those in Region 2; if any pair from different regions lies within the Rydberg blockade or restriction-zone radius used by the discretized model, the parallel local-phase execution is invalid.","tokens_in":23954,"feed_emoji":"⚛️","tokens_out":7358,"duration_ms":73718,"temperature":0.7,"pith_summary":"PAC is a compilation method for neutral atom quantum computers that aims to break the link between compile time and hardware flexibility. The method partitions the trap plane into two independent regions and, using an improved Kernighan–Lin graph partition, splits the quantum circuit so that most two-qubit gates are compiled inside one region or the other and only cross-region gates are left for a global phase. On 40 commutable 3-regular graph circuits with 60 to 90 qubits, PAC compiles every tested circuit within 1200 seconds on a $16\\times16$ array and within 200 seconds on a $64\\times64$ array, while the baseline DPQA frequently times out at 10,000 seconds. Reported speedups reach $78.5\\times$ on $16\\times16$ arrays and $202.81\\times$ on $24\\times24$ arrays, with average circuit depth staying within about one layer of DPQA's. If correct, this makes neutral atom compilation practical for the circuit sizes where existing solvers become prohibitive.","feed_headline":"Quantum compiler hits 200x speedup on neutral atom arrays","feed_subtitle":"Partitioning the trap plane and circuit into independent regions keeps circuit depth nearly unchanged.","key_machinery":"The load-bearing object is a two-stage decomposition: Hardware Plane Partitioning splits the trap plane into two subarrays whose AOD columns and rows are independent, and Quantum Circuit Division uses an improved Kernighan–Lin algorithm to split the qubit-interaction graph into two communities. The improved Kernighan–Lin algorithm iteratively swaps 'swap qubits' — active qubits with more external than internal connections — to minimize $L = k(N_{f,1}+N_{f,2})+(1-k)N_{E,\\text{cross}}$, where $N_{f,1},N_{f,2}$ count active qubits in each community and $N_{E,\\text{cross}}$ counts cross-community two-qubit gates. This decomposition converts one large Max-SAT-style solver problem over the whole plane into two smaller local problems solved in parallel plus a small global problem, with constraints (2)–(5) gluing the phases together.","core_discovery":"The central discovery is that the computational bottleneck in neutral atom compilation is mostly unnecessary coupling between regions that the hardware can keep independent. PAC cuts the $N\\times N$ array into two subarrays and compiles the circuit assigned to each region in parallel, exploiting the fact that AOD arrays in separate regions can operate independently. The circuit is split by an improved Kernighan–Lin algorithm operating on the qubit-interaction graph; its loss function $L = k(N_{f,1}+N_{f,2})+(1-k)N_{E,\\text{cross}}$ penalizes both the number of active qubits that must cross regions and the number of cross-region two-qubit gates, shrinking the work left for the global phase. The global phase inherits qubit positions from the local phase through constraints (2)–(5) and finishes the remaining gates over the whole plane. Across array sizes from $16\\times16$ to $64\\times64$, PAC is reported to compile all 60–90 qubit random 3-regular circuits while keeping average circuit depth between 12.6 and 13.95 layers, compared with 12 to 12.8 for DPQA.","pith_inferences":["This divide-and-conquer strategy likely transfers to other reconfigurable architectures beyond the specific SLM/AOD setup, since the key ingredient is physical independence of regions rather than a particular trap technology.","The reported advantage may depend on the sparse structure of 3-regular graph benchmarks; dense or all-to-all circuits could produce many cross-region edges and reduce the speedup, a testable extension.","For non-commutable circuits the method would need an extra commuting step or dependency handling; measuring that overhead is a natural next experiment.","A hardware-level check of simultaneous gates across the region boundary, rather than only the solver model, would confirm whether the parallel execution is physically valid."],"forward_implications":["Compilation time for 60–90 qubit commuting circuits would drop from thousands of seconds to tens or hundreds of seconds on arrays from $16\\times16$ to $64\\times64$.","Circuits that currently time out after 10,000 seconds under DPQA, most of the 80- and 90-qubit benchmarks, become compilable within a few minutes under PAC.","The speedup grows with array size, so the method becomes more useful as neutral atom hardware scales toward larger arrays.","Circuit depth stays comparable to DPQA within about one layer, so the speedup does not appear to come at the cost of longer execution schedules."],"supporting_citations":[{"why":"DPQA is the baseline method PAC is compared against and the source of the solver variables and constraints PAC reuses.","marker":"[20]"},{"why":"Defines the discretized working space, restriction zone, and solver-based compilation formulation that both DPQA and PAC build on.","marker":"[19]"},{"why":"Documents that current AOD atom arrays reach 16x16 configurations, anchoring the smallest hardware size used in the evaluation.","marker":"[22]"},{"why":"Demonstrates coherent transport of entangled atom arrays, the reconfigurability mechanism PAC assumes for moving qubits between regions.","marker":"[6]"},{"why":"Provides the NP-hardness of Max-SAT that motivates the need for faster compilation than a whole-plane solver.","marker":"[23]"}],"fun_headline_variants":["Physics-aware compilation gives 78x speedup on neutral atom arrays","PAC compiler: up to 78.5x faster neutral atom quantum execution","Parallel region compiler scales neutral atom arrays to 64x64","Splitting trap plane yields 78x faster neutral atom compilation","Neutral atom compiler: 78x speedup via physics-aware partitioning"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim depends on the physical assumption that the two halves of the AOD array can be operated simultaneously without any gate in one region interfering with a gate in the other, yet the paper never checks the inter-region separation against the Rydberg blockade radius.","fun_headline_variants_meta":{"raw":{"variants":["Physics-aware compilation gives 78x speedup on neutral atom arrays","PAC compiler: up to 78.5x faster neutral atom quantum execution","Parallel region compiler scales neutral atom arrays to 64x64","Splitting trap plane yields 78x faster neutral atom compilation","Neutral atom compiler: 78x speedup via physics-aware partitioning"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000313,"raw_usage":{"total_tokens":1806,"prompt_tokens":1003,"completion_tokens":803,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":619,"completion_tokens_details":{"reasoning_tokens":710}},"tokens_in":619,"tokens_out":803,"duration_ms":7214,"temperature":1.0,"reasoning_tokens":710,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T20:21:07.423077+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a PAC-produced schedule for any benchmark circuit and compare, for every time step, the positions of qubits executing two-qubit gates in Region 1 with those in Region 2; if any pair from different regions lies within the Rydberg blockade or restriction-zone radius used by the discretized model, the parallel local-phase execution is invalid.","supporting_citations":[],"review_version":1}