{"id":"14f012b1-907d-4f5e-97fa-ea6346a53527","arxiv_id":"2505.24363","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"On the same SoC and 22nm technology, a RISC-V-compliant out-of-order core matches the energy efficiency of in-order cores above 500 MHz, while an enhanced dual-issue core is most area-efficient.","lead":"The authors modified an out-of-order RISC-V core, the XuanTie C910, to use only standard RISC-V interfaces, and they built an enhanced dual-issue core they call CVA6S+. They then compared all three cores on the same SoC and 22nm process, finding that the out-of-order core matches the energy efficiency of simpler cores at high clock speeds, and that the superscalar in-order core offers the best area efficiency.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The energy-efficiency crossover is measured on a single high-ILP benchmark (matmult-int), so the broad OoO-versus-in-order claim in Section 6 is not yet established; the paper's own Figure 9 suggests workload dependence.","rationale":"The reader's weakest_assumption points to the same risk: the energy-efficiency comparison is based exclusively on matmult-int. This is the most load-bearing assumption because the headline result is a broad comparative claim about microarchitecture classes, not a statement about a single kernel. A single high-ILP, cache-resident benchmark is the scenario where OoO should look best; a conclusion based on it does not generalize to memory-stalled or low-ILP workloads. The ideal memory model compounds the issue by removing the latency that OoO is meant to hide. The paper already has the data needed for a decisive test at 900 MHz, so the concern is addressable without new fabrication runs. I therefore keep the reader's CONDITIONAL verdict unchanged.","tokens_in":14397,"tokens_out":10180,"duration_ms":125060,"concrete_test":"For each benchmark with power measurements in Figure 9 (matmult-int, nbody, statemate, seqcopy, sgcopy), compute GOPS/W at 900 MHz by combining the per-benchmark IPC values reported in the performance evaluation (Figure 3 / Section 5.1) with the corresponding power values in Figure 9. If C910 is not the most energy-efficient core on statemate, nbody, seqcopy, or sgcopy, the Section 6 conclusion must be scoped to compute-intensive integer workloads with cache-resident data; if it is the most efficient on all five, the single-benchmark concern is substantially mitigated.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Figure 8, the only cross-frequency energy-efficiency evidence, is built from power traces of the matmult-int benchmark alone (Section 5.5). matmult-int is a cache-resident, high-ILP integer kernel; it is the favorable case for an OoO core. The Section 6 conclusion ('beyond the 500 MHz timing target, the C910 core surpasses in-order cores in energy efficiency') is stated generally, without restricting it to compute-intensive, L1-resident workloads. The paper's own Figure 9 shows that at 900 MHz, C910's power disadvantage grows substantially for the memory-intensive RaiderSTREAM kernels (seqcopy, sgcopy) relative to matmult-int, and its IPC advantage on those kernels is not shown to compensate. The ideal main-memory model (Section 2.3) removes the very latency that an OoO core is designed to hide, further weakening the link between these measurements and realistic operation. Thus the central claim currently rests on a single, favorable workload.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a controlled comparison of three open-source RISC-V cores—the single-issue in-order CVA6, the dual-issue in-order CVA6S+ (an enhanced superscalar variant), and the out-of-order XuanTie C910—implemented in GF22FDX technology and integrated into the same Cheshire SoC. The authors modify the C910 to achieve RISC-V standard compliance in its interrupt, debug, and memory interfaces, and they add register renaming, branch prediction, operand forwarding, and FPU integration to create CVA6S+. Using identical tools, technology, and benchmarks, they report performance (IPC, Coremark/MHz, RaiderSTREAM bandwidth), timing, area, power, and energy-efficiency results. The central claim is that out-of-order execution is not inherently much less energy-efficient than in-order execution: beyond a 500 MHz timing target, the C910 surpasses the in-order cores in energy efficiency (GOPS/W), while CVA6S+ remains the most area-efficient design.","tokens_in":14582,"tokens_out":6709,"duration_ms":85840,"significance":"If the results hold, the paper makes a valuable contribution to the open-source RISC-V ecosystem: it provides a RISC-V-compliant C910 variant with a clean integration path, a publicly described CVA6S+ microarchitecture, and one of the most carefully controlled apples-to-apples comparisons of in-order and out-of-order RISC-V cores to date. The methodological strengths are substantial: same ISA, same SoC platform, same 22nm technology, same EDA tools and flow, and the same benchmark binaries across all three cores. The detailed area and power breakdowns and the open-source release plans enhance reproducibility. The quantitative area and performance trends are internally consistent, and the paper clearly identifies the microarchitectural components responsible for the power and area overheads. These strengths make the paper a useful reference for core selection and for future open-source high-performance RISC-V designs.","major_comments":[{"comment":"The energy-efficiency crossover that supports the central claim is computed from power measurements of a single benchmark, matmult-int, as stated in Section 5.5 ('The power consumption ... using VCD files generated from ... matmult-int benchmark'). Figure 9 shows that the power relationship is workload-dependent: at 900 MHz, C910's power is much higher relative to the in-order cores on the memory-intensive RaiderSTREAM kernels seqcopy and sgcopy than on matmult-int. Because matmult-int is L1-resident and high-ILP, it is the favorable case for an out-of-order core. The Section 6 conclusion that 'beyond the 500 MHz timing target, the C910 core surpasses in-order cores in energy efficiency' is therefore not yet established for general workloads; please either restrict the claim to compute-intensive, L1-resident workloads or provide energy-efficiency results for memory-intensive and low-ILP benchmarks.","section":"Section 5.5, Figure 8(b), Section 6"},{"comment":"The main memory is modeled as an ideal component with no internal latency, and the power traces cover a 30,000-cycle window from the steady-state benchmark body. This removes the memory latency that out-of-order execution is specifically designed to hide and excludes cold-cache behavior. The reported performance and energy results therefore cannot be directly extrapolated to realistic memory hierarchies or to workloads with capacity and conflict misses. Please discuss how the ideal-memory assumption and the finite power window affect the generality of the Section 6 conclusion, or add a sensitivity study with a latency model.","section":"Section 2.3, Section 4.2"},{"comment":"The energy-efficiency crossover is partly driven by circuit-level timing slack rather than by microarchitecture alone: at 900 MHz, C910 is far from its maximum frequency and consequently uses fewer LVT cells and has lower leakage, while CVA6 and CVA6S+ are near their timing limit. This is a legitimate design-point comparison, but it conflates the OoO microarchitecture with the ability to downclock a deeper pipeline. To support the 'not inherently less energy-efficient' claim, please compare at matched operating points (e.g., equal voltage/frequency, equal slack, or each core at its maximum frequency) or explicitly scope the conclusion to these specific implementations compared at equal target frequency.","section":"Section 5.2, Figure 4, Section 5.4"}],"minor_comments":[{"comment":"The metric 'GOPS' is used in GOPS/mm² and GOPS/W but never defined; please specify how GOPS is computed from the benchmark results (e.g., IPC × frequency × instruction count, or Coremark/MHz).","section":"Section 5.5"},{"comment":"The abstract and introduction report a '119.5% improvement in IPC' for C910 over CVA6, but the average IPC values in Section 5.1 (1.61 vs. 0.70) imply an improvement of roughly 130%; please reconcile these numbers.","section":"Abstract, Section 1"},{"comment":"The 'Rest' category in the area and power breakdowns is not explained; a one-sentence definition would help readers interpret what components are included.","section":"Figure 6, Figure 7"},{"comment":"The text says RaiderSTREAM is used with cold caches, while power analysis is performed after warm-cache iterations 'where present'; please clarify which configuration is used for the RaiderSTREAM power measurements.","section":"Section 4.2"},{"comment":"There is a missing space in 'analysis ofRISC-V open-source cores' in the first sentence; please fix this typo.","section":"Section 6"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the scope of Computing Frontiers and the controlled empirical methodology is a clear strength. The headline energy-efficiency conclusion, however, rests on a single benchmark and an ideal memory model, so the revision should focus on scoping or extending the claim. The required changes are substantive but feasible without new silicon; I would not support rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is a solid engineering paper with a useful artifact: a RISC-V-standard-compliant version of the XuanTie C910 core, plus an enhanced CVA6S+ with register renaming, better branch prediction, and FPU integration. The comparison methodology is about as controlled as one can get in this space—same ISA, same Cheshire SoC, same GF22FDX technology, same tools, same benchmark binaries. The area and performance numbers are internally consistent: CVA6S+ gets 34% IPC for 6% area, C910 gets 119% IPC for 75% area. That part is well done and credible.\n\nThe soft spot is the energy-efficiency crossover claim in Section 6. The GOPS/W curves in Figure 8 come exclusively from the matmult-int benchmark (Section 5.5), which is L1-resident and compute-heavy—the friendliest case for a wide OoO core. The paper's own power numbers in Figure 9 show a different story for memory-intensive RaiderSTREAM kernels: at 900 MHz, C910's power advantage largely disappears or reverses. Adding to that, the main memory is modeled as ideal with zero latency, which removes the very stalls an OoO core is designed to hide. So the statement that \"beyond 500 MHz C910 surpasses in-order cores in energy efficiency\" is too broad. It should be restricted to compute-intensive, L1-resident workloads, or supported by energy measurements on a wider set of benchmarks.\n\nMinor point: the paper says the cores will be released as open-source but gives no link or repository. Given the contribution is explicitly an open-source port, shipping the code would make the result much more reproducible and citable.\n\nOverall: this is a useful data point for anyone choosing between in-order and OoO cores in energy-constrained systems. It deserves peer review—the methodology is sound, the contributions are concrete, and the issues are fixable with revised claims and, ideally, additional measurements.\n\nRecommendation: send it to review, with a request that the authors temper the general claim and either add more energy benchmarks or clearly scope the conclusion.","headline":"A controlled same-technology comparison of three open-source RISC-V cores with a genuinely useful C910 port; the headline energy-efficiency claim is workload-dependent and needs tempering.","tokens_in":15185,"tokens_out":2560,"would_cite":false,"duration_ms":30364,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"An out-of-order RISC-V core can beat in-order cores on energy efficiency once clocks pass roughly 500 MHz, according to a controlled three-core comparison on the same SoC, the same 22 nm technology, and the same tools.","keywords":["RISC-V","out-of-order execution","superscalar","energy efficiency","open-source hardware","XuanTie C910","CVA6","22nm FDSOI"],"falsifier":"Re-run the same GOPS-per-watt frequency sweep with a memory-bound workload under a realistic, nonzero-latency memory model (for example, RaiderSTREAM scatter/gather with cold caches) and check whether the C910 curve still crosses the in-order curves near 500 MHz; if the crossover disappears or climbs above 1 GHz, the general claim is refuted.","tokens_in":14182,"feed_emoji":"⚡","tokens_out":14758,"duration_ms":146293,"temperature":0.7,"pith_summary":"This paper tries to settle a practical question: does buying superscalar, out-of-order execution force you to surrender energy efficiency? The authors built the apples-to-apples comparison the field usually lacks — three open-source RISC-V cores, one out-of-order and two in-order, implemented in the same 22 nm FDSOI technology with the same EDA tools, integrated into the same open-source SoC, and run on identical benchmark binaries. They also did the enabling engineering: a XuanTie C910 core made fully RISC-V compliant in its debug, interrupt, and memory interfaces, and CVA6S+, a dual-issue superscalar CVA6 with register renaming, a two-level branch predictor, operand forwarding, and a working FPU, which gains 34.4% in IPC over vanilla CVA6 at a 6% area cost. The headline result is that energy efficiency (GOPS per watt) is not a simple in-order win: beyond roughly 500 MHz the out-of-order C910 overtakes both in-order cores, while the superscalar in-order CVA6S+ keeps the best area efficiency (GOPS per mm²). This matters because it contradicts the common belief that high-performance out-of-order execution inherently costs energy efficiency, and because the cores and SoC are open-source, so the measurement can be repeated and extended.","feed_headline":"Out-of-order RISC-V core beats in-order rivals on energy past 500 MHz","feed_subtitle":"Same SoC, same 22nm process, same tools: the out-of-order core wins on energy efficiency at high clock speeds.","key_machinery":"The load-bearing mechanism is a same-everything comparison environment: the three cores drop into the same Cheshire SoC, are implemented in the same 22 nm FDSOI technology, go through the identical synthesis, place-and-route, and power-analysis flow, and run the same benchmark binaries compiled with the same toolchain, so the microarchitecture is the only variable. Inside that frame, the decisive objects are the two modified cores: the C910 stripped of its proprietary interrupt, debug, and AXI-ACE memory protocol and made fully RISC-V compliant, and CVA6S+, the dual-issue in-order CVA6 enhanced with register renaming, a two-level branch predictor, ALU-to-ALU operand forwarding, and FPU integration. The argument is carried by the frequency-swept efficiency curves — GOPS per watt versus target frequency — which reveal the crossover near 500 MHz where the deeper-pipeline out-of-order core's higher IPC per watt overtakes the simpler in-order designs.","core_discovery":"The paper's central claim is that the XuanTie C910, a 12-stage, three-issue out-of-order core, becomes more energy-efficient than in-order cores once the clock target passes 500 MHz: 'beyond the 500 MHz timing target, the C910 core surpasses in-order cores in energy efficiency' (Section 6). Measured on the same Cheshire SoC in 22 nm FDSOI, the C910 reaches an average IPC of 1.61 and 4.86 Coremark/MHz, versus 0.70 and 2.19 for the vanilla single-issue CVA6, at a 75% area increase — yet its power draw stays competitive at high frequency, and it achieves the highest maximum frequency of the three (1718 MHz at the fast corner, against 1340 MHz and 1227 MHz for CVA6 and CVA6S+). The frequency-swept efficiency data show all three cores' GOPS/W first rising and then falling as timing constraints tighten, with the out-of-order core's curve crossing above the in-order cores' beyond 500 MHz. The authors read this as a direct challenge to the long-standing assumption that superscalar and out-of-order execution inherently carries a significant energy-efficiency penalty.","pith_inferences":["My extension: the frequency sweep that produces the crossover is built on a single compute-intensive benchmark (matmult-int). Repeating the sweep with a branch-heavy kernel (statemate) or a floating-point kernel (nbody) would likely move the crossover, since those workloads exercise the out-of-order core's extra fetch, issue, and retirement machinery differently.","My extension: the ideal, zero-latency main memory probably favors the out-of-order core, whose deep reorder buffer and large load/store queues exist precisely to hide memory latency. A realistic DRAM latency model is the natural stress test and could push the crossover above 500 MHz or erase it entirely.","My extension: if the effect scales, the crossover frequency between in-order and out-of-order energy efficiency may drift downward on smaller process nodes, because deeper pipelines gain more frequency headroom while the relative energy cost of wide issue and retirement logic changes; this is testable by repeating the same setup on the next generation of these open-source cores."],"forward_implications":["If the crossover claim holds, a designer targeting clocks above roughly 500 MHz can pick an out-of-order core without assuming an energy penalty: its performance per watt is higher, not lower, than the in-order alternatives.","The in-order superscalar design point (CVA6S+) delivers the best area efficiency (GOPS/mm²) and the best combined area-energy efficiency, making it the rational choice when silicon area is the binding constraint.","Because every core's energy efficiency peaks at an intermediate frequency and then falls as timing closure forces low-threshold cells into the design, the operating frequency itself becomes a first-order efficiency control.","With the C910's debug, interrupt, and memory interfaces made RISC-V-standard-compliant, the open-source out-of-order design becomes usable with standard industrial EDA flows, the Cheshire software stack, and Linux, removing the integration barriers that previously excluded it from open-source SoCs."],"supporting_citations":[{"why":"Supplies the XuanTie C910 out-of-order core that the authors modify for RISC-V compliance and then evaluate; it is the object at the heart of the energy-efficiency claim.","marker":"[7]"},{"why":"Provides the dual-issue CVA6S superscalar baseline that CVA6S+ extends with register renaming, branch prediction, forwarding, and FPU support.","marker":"[1]"},{"why":"Describes the vanilla single-issue CVA6 core that serves as the base in-order reference in all three-way comparisons.","marker":"[20]"},{"why":"Defines the Cheshire SoC platform into which all three cores are integrated, the shared environment that makes the comparison apples-to-apples.","marker":"[12]"},{"why":"Supplies the HPDCache L1 cache used by the CVA6 and CVA6S+ cores, configured to match the C910's cache sizes for fairness.","marker":"[9]"},{"why":"One of the conventional energy-performance tradeoff analyses the paper's result challenges, anchoring the claim that OoO should be judged energy-inefficient.","marker":"[2]"},{"why":"Another statement of the prevailing view that out-of-order complexity costs efficiency, which the C910 crossover result is explicitly positioned against.","marker":"[13]"},{"why":"Source of the Embench-IoT suite, including the matmult-int benchmark that drives the Figure 8 energy-efficiency frequency sweep.","marker":"[6]"}],"fun_headline_variants":["OoO RISC-V core surpasses in-order energy efficiency past 500 MHz","Out-of-order RISC-V wins on energy beyond 500 MHz, same 22nm SoC","C910 out-of-order core beats in-order on energy efficiency at high clocks","Energy-efficient OoO: RISC-V C910 outperforms in-order past 500 MHz"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The energy-efficiency crossover is measured on one compute-intensive benchmark (matmult-int) over a 30,000-cycle power window and against an idealized main memory with no latency, so the claim that out-of-order execution wins above 500 MHz could fail for workloads that stall on memory or branches.","fun_headline_variants_meta":{"raw":{"variants":["OoO RISC-V core surpasses in-order energy efficiency past 500 MHz","Out-of-order RISC-V wins on energy beyond 500 MHz, same 22nm SoC","C910 out-of-order core beats in-order on energy efficiency at high clocks","Energy-efficient OoO: RISC-V C910 outperforms in-order past 500 MHz"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000253,"raw_usage":{"total_tokens":1711,"prompt_tokens":1238,"completion_tokens":473,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":854,"completion_tokens_details":{"reasoning_tokens":379}},"tokens_in":854,"tokens_out":473,"duration_ms":5339,"temperature":1.0,"reasoning_tokens":379,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T12:24:27.796480+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-run the same GOPS-per-watt frequency sweep with a memory-bound workload under a realistic, nonzero-latency memory model (for example, RaiderSTREAM scatter/gather with cold caches) and check whether the C910 curve still crosses the in-order curves near 500 MHz; if the crossover disappears or climbs above 1 GHz, the general claim is refuted.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the XuanTie C910 out-of-order core that the authors modify for RISC-V compliance and then evaluate; it is the object at the heart of the energy-efficiency claim."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the dual-issue CVA6S superscalar baseline that CVA6S+ extends with register renaming, branch prediction, forwarding, and FPU support."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Describes the vanilla single-issue CVA6 core that serves as the base in-order reference in all three-way comparisons."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the Cheshire SoC platform into which all three cores are integrated, the shared environment that makes the comparison apples-to-apples."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the HPDCache L1 cache used by the CVA6 and CVA6S+ cores, configured to match the C910's cache sizes for fairness."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"One of the conventional energy-performance tradeoff analyses the paper's result challenges, anchoring the claim that OoO should be judged energy-inefficient."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Another statement of the prevailing view that out-of-order complexity costs efficiency, which the C910 crossover result is explicitly positioned against."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Source of the Embench-IoT suite, including the matmult-int benchmark that drives the Figure 8 energy-efficiency frequency sweep."}],"review_version":1}