{"id":"d3532316-206f-4123-89c3-217f360207dd","arxiv_id":"2506.00007","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":0.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A literature review of machine learning techniques for analog and RF electronic design automation, organized by design task, with no new experimental results.","lead":"This paper surveys how machine learning and AI are being applied to automate the design of analog and RF circuits, an area where manual design is still common. It organizes recent approaches by design task, from constraint detection and topology generation to circuit sizing, placement, and routing.","discovery_kind":"review","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Survey's central claim rests on inaccurate citation summaries; specific misattributions in §2.1.2 and §3.6 undermine the evidence base.","rationale":"The reader's weakest assumption identified the lack of a disclosed literature search and the risk of selective coverage, and I agree that this is the key vulnerability for a survey. My read adds concrete internal evidence: specific citation/summary mismatches that are verifiable from the manuscript itself. This strengthens the fidelity concern from a hypothesis about methodology to an observed problem in execution. However, the issue does not warrant rejecting the survey outright. The affected claims are local and correctable, and the broader qualitative picture of ML-assisted analog/RF design may still hold. The appropriate disposition remains CONDITIONAL, with revisions to correct misattributions, add a methodology note, and temper the 'proven' language. Since the reader already arrived at CONDITIONAL, I am not moving the verdict; I am sharpening the basis for it and making the required check concrete.","tokens_in":13433,"tokens_out":4686,"duration_ms":46471,"concrete_test":"Build a verification table mapping every one-sentence method description in Sections 2 and 3 to the abstract or full text of the cited paper. Independently check the flagged cases: does [12] describe routing or well generation? does [67] describe a VAE? does [72] describe common-centroid routing? Then sample at least 20 additional citations at random and confirm that the claimed task, method class (e.g., GAN/VAE/GNN/RL), and reported result match the source. If the error rate exceeds about 10%, the survey requires corrections and a methodology statement before its central claim can be treated as supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The survey's central claim that ML has proven to improve productivity and design quality in analog/RF EDA depends on the accuracy of its one-sentence summaries of prior work. At least two summaries appear to be wrong. In §2.1.2, the text states that GANs have been applied to guide analog IC routing and cites [12]; however, [12] is WellGAN, a GAN for well generation in analog/mixed-signal layout, not routing. In §3.6, the text says a variational autoencoder is used to learn and generate routes and cites [67]; [67] is a matched-routing common-centroid MOM capacitor layout paper, while the VAE layout-synthesis work is [72], which is a different method and task. These are not cosmetic errors: a reader using this survey to locate methods would be misled about both the technique and the problem being solved. They also indicate that the summaries were not systematically verified against sources, which is especially damaging for a survey whose value is its fidelity as a map of the field. The lack of disclosed inclusion criteria amplifies this risk: without a search protocol, the cited set cannot be shown to be representative, and the clustering of self-citations in sections on GNNs, parasitic modeling, and benchmarks (e.g., refs [8,11,14,16,31,32,48,69,79,81,82,85]) raises the possibility of selective coverage. The conclusion that ML has 'proven' its value is therefore asserted on an evidence base that has not been demonstrated to be accurate or complete.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript is a survey of machine-learning and AI techniques applied to analog and RF electronic design automation (EDA). It organizes the literature by design task: constraint and hierarchy extraction, topology generation, device and EM-structure modeling, performance modeling and sizing, placement, and routing, and it additionally discusses cross-cutting challenges (PVT variation, interconnect parasitics) and the need for standardized benchmarks and datasets. The survey's stated conclusion is that ML has proven to be a powerful complement to traditional analog/RF design methods, improving productivity and design quality. The paper also includes a summary figure (Fig. 2) that maps techniques and algorithms to tasks.","tokens_in":13651,"tokens_out":4023,"duration_ms":37012,"significance":"If the survey's descriptions are accurate, it would be a useful map of a fragmented and rapidly growing literature, especially for readers entering the field, and it correctly identifies important open problems such as parasitic-aware design and the lack of standard analog benchmarks. The manuscript also has strengths that deserve explicit credit: it covers recent LLM-based approaches and benchmark/dataset efforts, and it draws attention to cross-cutting challenges that are often treated only in passing in similar surveys. However, the value of a survey rests on the fidelity and completeness of its citations, and this manuscript currently contains several concrete citation misattributions that mislead readers about which techniques are used for which tasks. It also provides no methodology for literature selection, which makes its coverage claims unverifiable. The survey is therefore potentially valuable but not yet reliable as a reference map.","major_comments":[{"comment":"The manuscript contains two load-bearing citation misattributions. In §2.1.2, the text states that GANs have been applied to guide analog IC routing and cites [12], but [12] is WellGAN, a GAN for well generation in analog/mixed-signal layout, not routing; the manuscript itself correctly describes WellGAN in §3.5 as generating analog layouts. In §3.6, the text states that a variational autoencoder is used to learn and generate routes and cites [67], but [67] is a matched-routing common-centroid 3-D MOM capacitor paper, while the VAE-based layout-synthesis work is [72]. These errors are not cosmetic: a reader using the survey to locate a technique for routing would be directed to the wrong papers, and the errors indicate that the one-sentence summaries were not systematically verified against sources. Please correct both passages and audit the remaining summaries against their references.","section":"§2.1.2 and §3.6"},{"comment":"The survey does not disclose any systematic methodology for selecting or screening the literature: there is no search protocol, inclusion/exclusion criteria, time window, or quality assessment described anywhere in the manuscript. Without such disclosure, the reader cannot assess whether the 85 cited papers are representative of the current state of the art, which is the central evidentiary base for the survey's conclusion that ML has 'proven' its value. The concentration of self-citations (roughly 12 of 85 references, concentrated in Sections 3.1–3.4 and 4.2) heightens this concern, as coverage of the authors' own GNN and parasitic-estimation work may crowd out independent validation. Please add a methodology section that describes how papers were collected and screened, and reconsider the balance of self-citations.","section":"§1 and §2 (methodology)"},{"comment":"Several factual claims are supported by outdated or incomplete evidence. The motivating statistics in §1 (analog circuits account for approximately 20% of chip area, 40% of design effort, and 50% of design iterations) are attributed to a 2003 IBS report [1]; given the age of the source, the numbers may no longer hold and should either be updated with recent data or explicitly flagged as historical. In §3.6, the claim that design-rule complexity has surpassed 10,000 rules below 22 nm is supported only by an incomplete reference [61] that lacks author, venue, and year. In §5, the claim that analog sizing comparisons are 'often erroneously completed' cites [81], which is an EDA-schema dataset paper for digital design, not a study of analog sizing evaluation. Please correct or temper these statements and complete the references.","section":"§1, §3.6, §5"}],"minor_comments":[{"comment":"The same paper appears twice in the reference list: [28] and [57] are both 'A General Approach for Identifying Hierarchical Symmetry Constraints for Analog Circuit Layout' by Kunal et al. from ICCAD 2020. Please deduplicate.","section":"References"},{"comment":"The figure entry 'Common-Centroid Routing [72]' is misleading, since [72] is the VAE-based layout-synthesis paper, not a common-centroid routing paper; the common-centroid routing reference is [62]. Please correct the citation in the figure.","section":"Figure 2"},{"comment":"There is a typographical issue in the sentence 'In [12],𝑊𝑒𝑙𝑙𝐺𝐴𝑁 is proposed', where the font for 'WellGAN' is corrupted. Please fix the formatting throughout.","section":"§3.5"},{"comment":"There are minor spelling and grammar errors, including 'mimick' in §3.5 and 'errorneously' in §5; please proofread the manuscript.","section":"§3.5 and §5"},{"comment":"The phrase 'provide benefit when analyzing' in §2.1.1 is awkward; rephrase as 'are beneficial when analyzing' or similar.","section":"§2.1.1"},{"comment":"Several references are incomplete or inconsistently formatted, including [23] (no venue), [24] (no full author list), [61] (no author/venue/year), and [40] (no venue). Please bring all references to a consistent, complete format.","section":"Various references"}],"recommendation":"major_revision","confidential_remarks":"For the editor: This is a survey manuscript from a single group with a relatively high rate of self-citation, and the reference list contains duplicates and incomplete entries; both warrant editorial scrutiny. The citation misattributions identified in the major comments are concrete and fixable, but they are central to the survey's utility. I would also suggest that the journal verify whether the survey offers sufficient differentiation from existing surveys on ML for analog EDA, since the manuscript does not discuss prior survey literature in this area. Overall, the paper is a reasonable starting point but needs a genuine round of verification and methodological disclosure before it can be accepted."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague — this survey is a decent first map of ML for analog/RF EDA, and its main value is organizational: it groups recent work under constraint formulation, topology generation, device modeling, sizing, placement, and routing, with two summary figures that help. It is not a critical review, and it does not need to be. For a newcomer, the task-by-task structure is the right skeleton.\n\nThe bigger problem is accuracy of the map. Two citations are wrong in ways that would mislead a reader. Section 2.1.2 says GANs have guided analog IC routing and cites [12]; [12] is WellGAN, which generates wells for analog/mixed-signal layout, not routing. Section 3.6 describes a VAE learning and generating routes and cites [67]; [67] is a matched-routing common-centroid MOM capacitor paper, while the VAE layout-synthesis work is [72]. These are not cosmetic. A survey's entire value is being a reliable pointer to the literature, and these pointers are broken. The fact that Section 3.5 later describes WellGAN correctly makes the Section 2 sentence an internal inconsistency, not a one-off typo.\n\nThe other weaknesses are more standard for surveys but still matter. There is no disclosed search protocol or inclusion criteria, so the reference set cannot be defended as representative. About 12 of 85 references are the authors' own work, clustered in GNN, parasitic modeling, and benchmark/standardization sections; that raises a legitimate selection-bias concern even if each self-citation is topically appropriate. The motivating statistics from a 2003 industry report appear dated. And the conclusion that ML has 'proven' its value is stronger than the evidence presented, especially given the citing errors.\n\nOn the positive side, most one-sentence summaries read as plausible, and the survey does name the right classical anchors (BLADES, BAG2, LAYGO, MAGICAL, ALIGN) alongside ML work. The typos are minor.\n\nMy take: this deserves a serious referee, but not acceptance as is. I would ask for a short methodology paragraph, correction of the two misattributed citations (and a pass through the rest of the references against their abstracts), toning down the conclusion, and broadening the self-citation mix. After that, I'd point newcomers to it. I would not cite it in its current form.","headline":"A useful organizational survey of ML for analog/RF EDA, but two cited summaries are wrong and the lack of methodology undercuts its authority until fixed.","tokens_in":14208,"tokens_out":2724,"would_cite":false,"duration_ms":26628,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Machine learning now demonstrably improves productivity and design quality in analog and RF circuit design, complementing traditional EDA rather than replacing it.","keywords":["analog EDA","RF design automation","machine learning","graph neural networks","Bayesian optimization","circuit sizing and layout","parasitic modeling","large language models"],"falsifier":"A fair test would be a standardized benchmark spanning multiple circuit topologies, technology nodes, and PDKs, the very resource the survey calls for, in which ML-based sizing, placement, and routing are compared against traditional flows on circuits excluded from model training; if ML methods failed to beat or complement the baselines on such held-out circuits, the central claim of proven productivity and quality gains would collapse. A cheaper partial falsifier is a replication check of the headline numbers, such as rerunning the cited 24-times simulation reduction on a different amplifier family.","tokens_in":13198,"feed_emoji":"⚙️","tokens_out":7143,"duration_ms":67907,"temperature":0.7,"pith_summary":"This survey claims that machine learning has become a dependable complement to traditional electronic design automation for analog and RF circuits, cutting both simulation cost and manual layout effort across the design flow. It gathers recent work into six task areas—constraint formulation, topology generation, device modeling, sizing, placement, and routing—and shows that in each area data-driven surrogates or learned optimizers now improve on purely knowledge-driven practice. The survey's central conclusion is that ML improves productivity and design quality while meeting target specifications, lowering the historically steep learning curve of analog design, but that it augments rather than replaces existing techniques. A reader should care because analog and RF layout remains a major bottleneck: the survey opens with figures of roughly 20% of chip area, 40% of design effort, and 50% of costly design iterations.","feed_headline":"ML now complements, not replaces, analog chip design","feed_subtitle":"A survey maps learning and optimization methods across sizing, placement, routing, and topology generation.","key_machinery":"The load-bearing idea is the learned surrogate model: a statistical or neural model that maps circuit features and design variables to performance targets, standing in for costly simulations and giving an optimizer a cheap surface to search. The survey repeatedly ties this to circuit-graph representations, where vertices are devices, and sometimes nets, while edges encode connectivity, so that GNNs can learn topology, hierarchy, and symmetry; when interconnect features matter, both device and net nodes are included. Around this core sit three supporting mechanisms: Bayesian optimization and reinforcement learning as the search engines, transfer learning to reuse models across technology nodes and topologies, and, since 2023, large language models that translate unstructured text specifications into design strategies or layouts. The named classes of objects include graph neural networks, generative adversarial networks, variational autoencoders, and Gaussian process surrogates; together they carry the argument that each design task can be accelerated by a learned model of that task's cost or outcome.","core_discovery":"The central claim is that across both synthesis and physical design, machine learning has moved from proposal to proven practice: learned models predict device and interconnect behavior, guide optimization, and even generate topologies and layouts. The survey identifies a common pattern: replace expensive SPICE or electromagnetic simulations with a trained surrogate, such as a graph neural network, Gaussian process, or autoencoder, then let Bayesian optimization, reinforcement learning, or evolutionary search explore the design space against that surrogate. For structure-heavy tasks, representing the circuit as a graph—devices as nodes and nets as edges—lets GNNs encode connectivity, hierarchy, and symmetry, and transfer learning carries these models across technology nodes and topologies. The survey also reports specific demonstrations, such as an actor-critic sizing flow that cuts executed SPICE simulations by up to 24 times, a deep generative placement tool that handles multiple amplifier topologies in under 150 ms, and an inverse-design flow for millimeter-wave power amplifiers with 16–24.7% power-added efficiency across 30–94 GHz. It notes that ML parasitic models are reliable only up to about a few gigahertz, because RF interconnects behave as transmission lines, and it closes by arguing that the main remaining obstacle is not any single algorithm but the absence of standardized benchmarks and open datasets.","pith_inferences":["Editorial inference: the survey's low-frequency caveat for parasitic models points to a concrete near-term opportunity, namely hybrid models that combine transmission-line physics with learned corrections, an approach the survey already sees under the label of physics-integrated device modeling.","Editorial inference: if LLM-based layout passes DRC and LVS on small blocks, a testable next step is scaling to larger hierarchical circuits; the current 44% pass rate likely trades off against block size, and reporting that trade-off explicitly would sharpen the picture.","Editorial inference: because the reviewed methods rely on training data quality, transfer learning across technology nodes may determine whether ML-EDA works for groups that do not own large PDK datasets, a practical consequence the survey mentions but does not develop.","Editorial inference: a community benchmark built around the survey's call for standardization could falsify or confirm the central claim, since it would test whether ML gains persist on circuits and process nodes excluded from training sets."],"forward_implications":["Designers can expect fewer slow simulations: the survey cites an RL-based sizing flow that reduces executed SPICE simulations by up to 24 times, and batch-constrained Bayesian optimization that parallelizes the search.","Layout generation becomes fast enough for design-space exploration: a deep generative placer places several amplifier topologies in under 150 ms, and a decision-tree RF placer placed a 6–13 GHz LNA in 86 ms.","Millimeter-wave RF blocks can be inverse-designed from specifications: one cited flow achieves 16–24.7% power-added efficiency over a 30–94 GHz bandwidth without restricting design to predefined templates.","Natural-language layout entry starts to work for small circuits: a fine-tuned LLM layout flow reaches 70% task completion with 44% of generated layouts passing DRC and LVS checks for blocks up to four transistors.","The next bottleneck is measurement, not method: the survey argues that standardized benchmarks and open datasets are required before different ML-EDA techniques can be compared fairly."],"supporting_citations":[{"why":"Supplies the motivating statistics: analog occupies roughly 20% of chip area, 40% of design effort, and 50% of costly design iterations.","marker":"[1]"},{"why":"Provides the statistical pattern-search sizing baseline that later ML-based sizing methods build on.","marker":"[2]"},{"why":"Supplies the ALIGN analog layout system, a load-bearing example of GNN-guided hierarchical routing and placement.","marker":"[3]"},{"why":"Exemplifies surrogate-assisted optimization with batch-constrained Bayesian optimization for analog synthesis.","marker":"[20]"},{"why":"Shows reinforcement learning with a policy-gradient network constructing circuit topologies from predefined building blocks.","marker":"[21]"},{"why":"Provides the graph-based compact model in Verilog-A, a stated success of ML device modeling integrated with SPICE.","marker":"[45]"},{"why":"Supports the 24-times reduction in executed SPICE simulations via an actor-critic reinforcement-learning sizing flow.","marker":"[51]"},{"why":"Demonstrates fast scalable placement of multiple amplifier topologies in under 150 ms using deep generative models.","marker":"[55]"},{"why":"Shows deep-learning inverse design of millimeter-wave passives and power amplifiers, the survey's strongest RF physical-design example.","marker":"[60]"},{"why":"Anchors the survey's standardization argument by noting how unified frameworks and open datasets improve comparability in digital EDA.","marker":"[81]"}],"fun_headline_variants":["AI slashes analog SPICE simulations 24x","Graph neural nets learn analog circuits for EDA","ML surrogates replace costly analog simulations","Survey maps ML for analog and RF design automation","From sizing to layout, ML speeds analog EDA"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The survey's conclusion depends on the cited papers faithfully representing the current state of the art, but it does not disclose a systematic literature search, inclusion criteria, or quality screening, so selective coverage, including sections that lean heavily on the survey authors' own papers, could bias the picture.","fun_headline_variants_meta":{"raw":{"variants":["AI slashes analog SPICE simulations 24x","Graph neural nets learn analog circuits for EDA","ML surrogates replace costly analog simulations","Survey maps ML for analog and RF design automation","From sizing to layout, ML speeds analog EDA"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000251,"raw_usage":{"total_tokens":1534,"prompt_tokens":896,"completion_tokens":638,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":512,"completion_tokens_details":{"reasoning_tokens":566}},"tokens_in":512,"tokens_out":638,"duration_ms":5957,"temperature":1.0,"reasoning_tokens":566,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T22:02:32.967225+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"A fair test would be a standardized benchmark spanning multiple circuit topologies, technology nodes, and PDKs, the very resource the survey calls for, in which ML-based sizing, placement, and routing are compared against traditional flows on circuits excluded from model training; if ML methods failed to beat or complement the baselines on such held-out circuits, the central claim of proven productivity and quality gains would collapse. A cheaper partial falsifier is a replication check of the headline numbers, such as rerunning the cited 24-times simulation reduction on a different amplifier family.","supporting_citations":[{"cited_title":"An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble,","cited_arxiv_id":null,"evidence_quote":"Exemplifies surrogate-assisted optimization with batch-constrained Bayesian optimization for analog synthesis."},{"cited_title":"Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning,","cited_arxiv_id":null,"evidence_quote":"Shows reinforcement learning with a policy-gradient network constructing circuit topologies from predefined building blocks."},{"cited_title":"Graph-based compact model (GCM) for efficient transistor parameter extraction: A machine learning approach on 12 nm FinFETs,","cited_arxiv_id":null,"evidence_quote":"Provides the graph-based compact model in Verilog-A, a stated success of ML device modeling integrated with SPICE."},{"cited_title":"DNN- Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks,","cited_arxiv_id":null,"evidence_quote":"Supports the 24-times reduction in executed SPICE simulations via an actor-critic reinforcement-learning sizing flow."},{"cited_title":"DeepPlacer: A Custom Integrated OpAmp Placement Tool Using Deep Models,","cited_arxiv_id":null,"evidence_quote":"Demonstrates fast scalable placement of multiple amplifier topologies in under 150 ms using deep generative models."},{"cited_title":"Deep-learning-based inverse-designed millimeter-wave passives and power amplifiers,","cited_arxiv_id":null,"evidence_quote":"Shows deep-learning inverse design of millimeter-wave passives and power amplifiers, the survey's strongest RF physical-design example."},{"cited_title":"EDA-schema: A graph datamodel schema and open dataset for digital design automation,","cited_arxiv_id":null,"evidence_quote":"Anchors the survey's standardization argument by noting how unified frameworks and open datasets improve comparability in digital EDA."}],"review_version":1}