{"id":"01303dc5-a409-4249-9288-bc6c434daf8d","arxiv_id":"2506.01029","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"AEQUAM compiles OpenQASM 2.0 circuits into customizable FPGA emulators and demonstrates six-qubit emulation on a low-cost Cyclone 10LP FPGA with 20-bit fixed-point arithmetic.","lead":"AEQUAM is a toolchain that turns OpenQASM 2.0 quantum circuits into FPGA hardware emulators, using a sparsity-aware butterfly method to cut redundant operations. On a small Intel Cyclone 10LP FPGA it emulates up to six qubits while supporting rotational gates, which some earlier FPGA emulators lacked.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Abstract's 'better scalability' claim is contradicted by the paper's own Figure 26 and Table 3, which show [18] scaling better; the claim needs re-scoping to survive.","rationale":"The reader's weakest assumption—that logic-element counts across different FPGA families are not directly comparable—is a valid methodological concern. However, I found a more direct and load-bearing problem: the paper's own Section V-C3 and Figure 26 identify [18] as scaling better, which contradicts the unqualified abstract claim of 'better scalability than other state-of-the-art emulators.' This is not a matter of external standards or normalization choices; it is an internal inconsistency that can be checked by reading the text. The engineering work described (synthesis, simulation against Qiskit, detailed toolchain) appears sound, and the claim is repairable by re-scoping to 'competitive scalability with broader gate support,' so the reader's CONDITIONAL verdict remains appropriate. My concern does not move the verdict; it reinforces the need for revision, hence verdict_should_be is UNCHANGED.","tokens_in":22825,"tokens_out":6307,"duration_ms":66000,"concrete_test":"Re-plot Figure 26 using a normalized resource metric (e.g., LE-equivalent per qubit: convert ALMs via the vendor's ALM-to-LE ratio for Cyclone V/Arria 10 and treat Stratix LC as 1 LE) and add gate-set capability as a separate axis, then check whether AEQUAM remains below all general-purpose emulators. If AEQUAM's normalized curve is not the lowest among emulators supporting rotational gates, revise the abstract and conclusion 'better scalability' wording to 'competitive scalability with broader gate support'.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central scalability claim is internally inconsistent. The abstract and conclusions assert AEQUAM achieves 'better scalability than other state-of-the-art emulators' and 'outperforming prior FPGA-based solutions in terms of resource efficiency.' Yet Section V-C3 explicitly states, regarding Figure 26, that 'the architecture proposed by [18] is the only one with better scalability than ours.' Table 3 lists [18] at 9 qubits using 4019 LCs versus AEQUAM's 6 qubits using 11702 LEs (serial) and 5 qubits using 20993 LEs (parallel). Even ignoring the LE-vs-LC unit mismatch, the paper's own comparison places AEQUAM behind [18] in raw qubit-per-resource scalability. The 'better scalability' claim is therefore either false as stated or requires an unstated qualifier (e.g., 'among emulators supporting rotational gates and on-chip state storage'). The metric-mixing problem identified by the reader compounds this: ALM/LC/LE counts are not commensurate across Cyclone V, Arria 10, Stratix, and Cyclone 10LP, and precision differs (10-bit to 64-bit), so even the 'competitive' claim is not established by Table 3 as presented. A corrected, normalized comparison should be a condition for the scalability claim.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces AEQUAM, an open-source FPGA-based toolchain for quantum circuit emulation. It compiles OpenQASM 2.0 into RISC-like instructions, provides Cython software models for selecting fixed-point number representations, and generates VHDL for a processor that applies gates to interacting amplitude pairs through a butterfly selection mechanism. The authors synthesize a 20-bit fixed-point configuration on an Intel Cyclone 10LP and report 6-qubit full-serial and 5-qubit full-parallel emulation, with windowed variants trading parallelism for area. They benchmark emulation accuracy against Qiskit using mqt-bench and public circuits, and compare resource usage with prior FPGA emulators.","tokens_in":23073,"tokens_out":4312,"duration_ms":42833,"significance":"If the resource-efficiency and scalability claims are supported, AEQUAM would be a useful low-cost platform for teaching and for validating small quantum circuits, with configurable precision and parallelism and support for both Clifford+T and rotational gates. The public GitHub repository, automated testbench scripts, and the systematic software-model study of numeric precision are concrete strengths that aid reproducibility. However, the headline scalability claim currently rests on a comparison that mixes non-commensurable FPGA resource units and precision choices, so the significance as stated is not yet established.","major_comments":[{"comment":"The central claim of \"better scalability\" is contradicted by the paper's own comparison. The abstract says the architecture \"demonstrates better scalability than other state-of-the-art emulators,\" and Section VII claims \"outperforming prior FPGA-based solutions in terms of resource efficiency.\" Yet Section V-C3 explicitly states that \"the architecture proposed by [18] is the only one with better scalability than ours.\" Table 3 shows [18] reaching 9 qubits with 4019 LCs versus AEQUAM's 6 qubits with 11702 LEs (serial) and 5 qubits with 20993 LEs (parallel). The abstract and conclusion claims must either be qualified (e.g., \"among emulators supporting rotational gates and without external memories\") or the comparison must be revised.","section":"Abstract; Section V-C3; Section VII"},{"comment":"The resource comparison shown in Table 3 and Figure 26 is not normalized across FPGA families or numerical precisions. Logic utilization is reported as LEs for Cyclone 10LP, ALMs for Cyclone V and Arria 10, and LCs for Stratix; these units are not directly comparable, and the precision ranges from 10-bit fixed point to 64-bit floating point. As a result, the \"competitive\" and \"resource efficiency\" statements in Sections V-C3 and VI are unsupported as written. The authors should report a normalized metric (e.g., area per complex amplitude, or area per amplitude-bit) or synthesize at least one earlier design with the same tool, device family, and precision.","section":"Table 3; Figure 26; Section V-C3"},{"comment":"The scalability comparison uses only logic-element count versus qubit count and does not account for gate-set coverage, execution throughput, or memory architecture. Since [17] uses external memory and [18] supports only a restricted gate set (Pauli X, CNOT, Toffoli, Hadamard), the raw qubit-per-resource plot conflates architectural capability with scalability. A fair comparison should also report throughput (e.g., gates per second) and specify the supported gate set and whether on-chip state storage is used for each data point.","section":"Figure 26; Section V-C3"}],"minor_comments":[{"comment":"Figures 24(c) and 24(d) are referenced twice in the text, once for variation with Q and once for variation with W; the figure numbering and captions need correction.","section":"Figure 24"},{"comment":"The legend in Figure 26 lists references [14]-[17], while Table 3 compares AEQUAM with [15]-[18]; the reference numbering should be aligned.","section":"Figure 26"},{"comment":"The sentence \"It is also the address of the first state\" appears twice in the description of the control unit.","section":"Section III-D1"},{"comment":"The phrase \"opta-core\" appears to be a typo for \"octa-core\".","section":"Section V-A1"},{"comment":"References [13] and [21] are duplicate entries for the same OpenQASM paper; one should be removed or cross-referenced.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The engineering contribution is real and the experimental work appears internally consistent, but the abstract and conclusion overstate the scalability result in a way that the body already contradicts. A revision that re-scopes the claims and provides a normalized comparison would make the paper acceptable."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague, quick take on the AEQUAM paper. It's a real, working FPGA emulation toolchain: an OpenQASM-to-VHDL compiler, Cython models for precision analysis, and a windowing architecture that trades parallelism for area. That combination is new relative to the cited prior work, and the authors are honest about provenance—the butterfly selection is explicitly attributed to [19]. The engineering effort is substantial: actual synthesis on a Cyclone 10LP, functional verification against Qiskit, and accuracy metrics (fidelity, KLD, MCD, ACD). The core is sound.\n\nWhere it falls apart is the headline. The abstract and conclusions claim 'better scalability than other state-of-the-art emulators,' but Section V-C3 states the opposite: 'the architecture proposed by [18] is the only one with better scalability than ours.' Table 3 backs the Section V-C3 statement—[18] reaches 9 qubits with 4019 LCs, while AEQUAM reaches 6 qubits with 11702 LEs (serial) or 5 with 20993 LEs (parallel). Even ignoring the LE/ALM/LC unit mismatch, the paper's own data puts AEQUAM behind [18] in raw qubit-per-resource. The claim only survives with qualifiers: 'better scalability among emulators supporting rotational gates and on-chip state storage.' The comparison is also not normalized across FPGA families or bit widths (10- to 64-bit), so the 'competitive' claim is not established as presented.\n\nAlso: the code is said to be on GitHub but no URL or commit hash appears, so the reproducibility claim is unverifiable. And V-C3 contains figure-reference errors—the Q and Nq discussions point at the W subfigures in Figure 24. These are fixable but made me double-check the numbers.\n\nNone of this sinks the toolchain's value. Read it as 'a complete, configurable FPGA emulation flow for teaching and small-circuit verification' and it's a credible contribution. The flaw is in the framing, not the engineering. Recommendation: send to peer review with major revisions. Require the re-scoped scalability claim, a normalized or at least honestly discussed comparison, and a repository link. A serious referee can get value from this paper; the current version just overreaches.","headline":"Real FPGA emulation toolchain with an overreaching scalability claim that its own Section V-C3 contradicts; worth reviewing after re-scoping.","tokens_in":23609,"tokens_out":3727,"would_cite":false,"duration_ms":35484,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"AEQUAM claims an FPGA toolchain that emulates quantum circuits up to six qubits on a low-cost Cyclone 10LP, scaling better in logic elements than most earlier FPGA emulators while supporting Clifford+T and rotational gates.","keywords":["quantum circuit emulation","FPGA","butterfly selection","sparse gate matrices","fixed-point arithmetic","SIMD","windowing","quantum algorithm verification"],"falsifier":"A reader could re-synthesize AEQUAM and the cited emulators on one FPGA family with identical precision and synthesis settings; if AEQUAM no longer uses fewer logic elements at equal qubit counts, the scalability claim is a comparison artifact. A simpler check is to reproduce the reported synthesis numbers: the serial 6-qubit and parallel 5-qubit configurations must fit on the 24,624-LE Cyclone 10LP at the stated 80/109 MHz clocks and with roughly 11.7k and 21.0k LEs.","tokens_in":22627,"feed_emoji":"⚛️","tokens_out":9281,"duration_ms":88405,"temperature":0.7,"pith_summary":"AEQUAM is a toolchain that turns OpenQASM 2.0 circuits into a compact, RISC-style instruction set and then into a custom FPGA hardware emulator, aiming to make quantum-algorithm verification faster and cheaper than software simulation. The paper's central claim is that a sparsity-aware butterfly selection mechanism, which applies each gate only to the pairs of probability amplitudes that actually interact, lets the emulator fit six qubits in full-serial mode and five qubits in full-parallel mode on a small Intel Cyclone 10LP FPGA, with better logic-element scaling than most earlier FPGA emulators. A second claim is that a 20-bit fixed-point representation with nearest rounding keeps emulation error small while sharply cutting area, and that the architecture supports both Clifford+T gates (the standard discrete gate set) and rotational gates, unlike the closest sparse-emulator predecessor. The authors present this as a practical low-cost platform for debugging and teaching quantum algorithms, validated on standard benchmark circuits and against a reference state-vector simulator.","feed_headline":"Sparsity trick puts 6-qubit quantum emulation on a low-cost FPGA","feed_subtitle":"Butterfly-style gate selection and 20-bit fixed-point math beat earlier FPGA emulators' logic-element scaling.","key_machinery":"The load-bearing mechanism is the butterfly-like couple-selection scheme. For an $N$-qubit state vector, applying a single-qubit gate to a target qubit splits the equivalent $2^N \\times 2^N$ gate matrix into $2^{N-1}$ identical $2\\times2$ kernels, each acting on one pair of probability amplitudes; the positions of those pairs follow an FFT-like butterfly pattern set by the target qubit. For controlled gates, half of the kernels become identity matrices, and those couples are skipped, eliminating redundant work and removing any need to build or store layer matrices. On top of this, the windowing mechanism shrinks the datapath count from $2^{N-1}$ to $2^{N-W-1}$ by processing $W$ windows of amplitude couples serially, so the user can interpolate between full-parallel speed and full-serial area, at the cost of doubling gate-execution time per increment of $W$.","core_discovery":"The paper's central claim is that a quantum state vector can be evolved on an FPGA by processing only the interacting amplitude couples selected by a butterfly-style pattern, one gate at a time, instead of materializing layer matrices or multiplying full state vectors. On the authors' chosen device, an Intel Cyclone 10LP with roughly 24.6k logic elements, this yields a 6-qubit emulator in full-serial mode (11,702 LEs) and a 5-qubit emulator in full-parallel mode (20,993 LEs) at 20-bit fixed-point precision with nearest rounding. The authors compare against four published FPGA emulators and report that AEQUAM's logic-element curve is better than all but one, whose better scaling comes at the cost of supporting only X, CNOT, Toffoli, and Hadamard gates; AEQUAM instead covers Clifford+T and rotational gates, so it can run any generic circuit accepted by the compiler. They further claim that the fixed-point precision, chosen through their software models, keeps error small (maximum and average complex distances generally below 0.05 in their benchmarks) while the software model itself runs at least an order of magnitude faster than the reference state-vector simulator.","pith_inferences":["A testable extension the authors leave implicit: sweep the windowing order $W$ at fixed qubit count on a larger FPGA to map the full area-time Pareto curve; the reported serial and parallel endpoints suggest intermediate $W$ values are the practical operating points for real circuits.","Because rotation angles are precomputed into a table at compile time, variational circuits with many distinct angles will exhaust the sine-cosine register file before the qubit limit; replacing the table with an on-chip trigonometric unit, which the authors list as future work, would remove that bottleneck.","If fixed-point error accumulates with circuit depth, the 20-bit recommendation will eventually fail on very deep circuits; the software models' precision sweep effectively turns bit width into a tunable parameter, so a user can choose the smallest width that keeps the maximum complex distance below a target threshold.","The toolchain currently ignores measurement and rejects measurement-conditioned branches, so the emulator certifies ideal state evolution rather than measurement-feedback behavior; the circuit-partitioning scheme sketched for future releases would extend it to those programs."],"forward_implications":["On the tested Cyclone 10LP part, full-serial emulation supports 6 qubits (11,702 LEs) and full-parallel supports 5 qubits (20,993 LEs), with windowing orders filling the area-time tradeoff between them.","The architecture executes Clifford+T and rotational gates, so any OpenQASM 2.0 circuit without measurement-conditioned branches can be emulated, unlike the closest sparse-emulator predecessor that stops at X, CNOT, Toffoli, and Hadamard.","Fixed-point 20-bit nearest representation keeps maximum and average complex amplitude errors generally below 0.05 on the tested circuits while using far fewer resources than floating-point datapaths.","The software model runs benchmark circuits at least an order of magnitude faster than the reference state-vector simulator, so the butterfly mechanism itself, independent of FPGA synthesis, already accelerates validation.","Because area grows exponentially with qubits as the state-vector size $2^N$, the practical ceiling on this FPGA class is around six to eight qubits, and larger qubit counts require external memory or larger devices."],"supporting_citations":[{"why":"Defines the OpenQASM 2.0 input language that the AEQUAM compiler consumes.","marker":"[13]"},{"why":"Supplies the baseline FPGA emulator built on layer matrix-vector products, whose 2-qubit result AEQUAM compares against.","marker":"[15]"},{"why":"Supplies the floating-point FPGA emulator baseline whose 4-qubit result AEQUAM uses for scalability comparison.","marker":"[16]"},{"why":"Supplies the external-memory emulator baseline, contrasting its flat scalability and QFT-specific design.","marker":"[17]"},{"why":"Provides the closest sparse-emulator predecessor, whose limited gate set AEQUAM extends beyond.","marker":"[18]"},{"why":"Introduces the butterfly-style couple-selection mechanism that AEQUAM adopts and implements in hardware.","marker":"[19]"},{"why":"Supplies the benchmark circuits used to validate the emulator against a reference state-vector simulator.","marker":"[25]"}],"fun_headline_variants":["Sparsity trick runs 6-qubit quantum circuits on a budget FPGA","FPGA emulator uses sparsity to beat bigger rivals on quantum circuits","AEQUAM: 6-qubit quantum emulation on a low-cost FPGA via butterfly gates","Butterfly gate method shrinks quantum emulation to fit cheap FPGAs","Low-cost FPGA emulates 6 qubits with sparsity-based quantum gates"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The scalability comparison assumes that logic-element counts from different FPGA families, such as Cyclone 10LP LEs, Cyclone V and Arria 10 ALMs, and Stratix LCs, are directly comparable without normalizing for architecture, synthesis settings, or numerical precision.","fun_headline_variants_meta":{"raw":{"variants":["Sparsity trick runs 6-qubit quantum circuits on a budget FPGA","FPGA emulator uses sparsity to beat bigger rivals on quantum circuits","AEQUAM: 6-qubit quantum emulation on a low-cost FPGA via butterfly gates","Butterfly gate method shrinks quantum emulation to fit cheap FPGAs","Low-cost FPGA emulates 6 qubits with sparsity-based quantum gates"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000859,"raw_usage":{"total_tokens":3735,"prompt_tokens":959,"completion_tokens":2776,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":575,"completion_tokens_details":{"reasoning_tokens":2670}},"tokens_in":575,"tokens_out":2776,"duration_ms":19108,"temperature":1.0,"reasoning_tokens":2670,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T11:52:00.448297+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"A reader could re-synthesize AEQUAM and the cited emulators on one FPGA family with identical precision and synthesis settings; if AEQUAM no longer uses fewer logic elements at equal qubit counts, the scalability claim is a comparison artifact. A simpler check is to reproduce the reported synthesis numbers: the serial 6-qubit and parallel 5-qubit configurations must fit on the 24,624-LE Cyclone 10LP at the stated 80/109 MHz clocks and with roughly 11.7k and 21.0k LEs.","supporting_citations":[{"cited_title":"Pilch and J","cited_arxiv_id":null,"evidence_quote":"Supplies the baseline FPGA emulator built on layer matrix-vector products, whose 2-qubit result AEQUAM compares against."},{"cited_title":"Mahmud and E","cited_arxiv_id":null,"evidence_quote":"Supplies the floating-point FPGA emulator baseline whose 4-qubit result AEQUAM uses for scalability comparison."},{"cited_title":"Mahmud, B","cited_arxiv_id":null,"evidence_quote":"Supplies the external-memory emulator baseline, contrasting its flat scalability and QFT-specific design."},{"cited_title":"Conceição and R","cited_arxiv_id":null,"evidence_quote":"Provides the closest sparse-emulator predecessor, whose limited gate set AEQUAM extends beyond."},{"cited_title":"Negovetic, M","cited_arxiv_id":null,"evidence_quote":"Introduces the butterfly-style couple-selection mechanism that AEQUAM adopts and implements in hardware."}],"review_version":1}