{"id":"2b6fe5fa-3f77-44e4-a366-06f2b3147ccf","arxiv_id":"2506.02030","paper_version":1,"verdict":"REJECT","confidence":"HIGH","novelty_score":3.0,"correctness_risk":"high","formal_verification":"none","parameter_count":1,"one_line_summary":"A position paper that organizes existing NAND flash secure-deletion techniques into four adaptive privacy levels, without implementing or empirically validating the design.","lead":"The paper proposes an adaptive SSD design with four privacy levels (PL0 to PL3) that choose among block erase, page scrubbing, parity corruption, and block map-out for secure deletion. The generalist might read it as a conceptual framework for balancing privacy, performance, and wear in IoT storage.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The paper's central trade-off conclusions rest on Table 2 scores that are unmeasured and contradicted by the text's own caveats about raw-cell recoverability, so the adaptive-privacy claim lacks evidential support.","rationale":"The reader's weakest-assumption analysis correctly identifies Table 2 as the load-bearing quantity: the adaptive architecture's privacy-versus-performance balance is derived from those scores, and no measurement or methodology backs them. My stress-test confirms this and adds a stronger point: the paper's own qualitative discussion contradicts several Table 2 entries. ECC modulation and flag locking are described as leaving raw data physically recoverable, so their Efficacy=5 and Verification=5 scores cannot be taken at face value. Because PL2 is the distinctive contribution of the paper, this internal inconsistency attacks the core contribution, not just the presentation. I also note the explicit self-admission in Section 6 that empirical validation is future work, which precludes treating the table as experimentally grounded. This is not a disagreement with the community's consensus about NAND privacy risks; it is an evidentiary failure within the paper's own argument. I see no reason to change the reader's REJECT verdict, though the paper could later become a useful research agenda if the table is replaced with reproducible measurements. No ad hominem is intended; the issue is that the central claim is unsupported as written.","tokens_in":8628,"tokens_out":2492,"duration_ms":34003,"concrete_test":"On a 3D TLC NAND test platform, implement each of the eight deletion techniques from Table 2, delete a known data pattern, and then perform chip-off raw page reads in vendor/test mode. For ECC modulation and flag locking specifically, measure the fraction of raw payload bits that remain recoverable and whether an attacker can reconstruct the original pattern. If the raw bytes are recoverable above the ECC-unrecoverable threshold, the Efficacy=5 scores are wrong. Also measure flag-cell hardware cost and overhead against a baseline block-erase implementation. If any score change reverses the ranking that makes PL2 superior, the paper's central balance conclusion fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The load-bearing premise is that Table 2's ordinal scores (Efficacy, Speed, Durability, Overhead, Verification, Cost) are meaningful enough to rank deletion techniques and to justify the PL0-PL3 adaptive architecture. This premise is not merely unverified; it is internally contradicted by the paper's own text. Table 2 gives ECC modulation and flag locking Efficacy=5 and Verification=5, yet Section 4.2 states that ECC modulation is 'anti-forensic rather than cryptographically final' and that 'a determined attacker with direct flash access could still extract the underlying bytes'; it likewise says for flag locking that 'the raw bytes still exist' and 'highly sensitive data still needs stronger sanitization.' If raw payload bytes remain physically recoverable via chip-off or vendor-mode reads, an Efficacy score of 5 is indefensible, and the claimed PL2 privacy advantage collapses. The same section also says flag cells require dedicated hardware and redundant SLC copies, which contradicts the '5' cost and overhead scores. Additionally, Section 6 explicitly admits that 'Empirical validation of various deletion mechanisms remains a priority for future work,' and no measurement methodology, simulator, or dataset is provided for Table 2. The ML-based automatic level adjustment is described only in general terms, so the 'negligible performance overhead and complexity' claim is also unsupported. If Table 2 is only an illustrative sketch, then the paper's quantitative balancing of efficacy, latency, endurance, and cost is not established; if it is meant as evidence, it is internally inconsistent.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes an adaptive SSD architecture with four privacy levels (PL0–PL3) that select among address, data, and parity deletion techniques for NAND flash storage in IoT devices. It claims a quantitative analysis balancing efficacy, latency, endurance, and cost, and an ML-based automatic adjustment of privacy levels with negligible performance overhead. The manuscript presents a taxonomy of secure deletion techniques, a four-level architecture, and a performance comparison in Table 2 with hand-assigned scores. No implementation, measurements, formal derivations, or empirical validation are provided; Section 6 explicitly defers validation to future work.","tokens_in":8972,"tokens_out":4647,"duration_ms":52182,"significance":"If the claims were substantiated, the framework would provide a useful design guideline and taxonomy for privacy-preserving NAND flash storage, organizing techniques into address, data, and parity management and articulating a graduated privacy-level model. The paper's strength lies in its systematic classification and its explicit statement of open problems. However, the central quantitative claim is unsupported: the evidentiary basis is an unverified score matrix, and the ML adaptation claim lacks any algorithmic or experimental grounding. As a conceptual position paper it could stimulate discussion, but in its current form it does not meet the evidentiary bar for a research contribution.","major_comments":[{"comment":"The quantitative foundation of the paper is unsupported. The 1–5 scores in Table 2 for efficacy, speed, durability, overhead, verifiability, and cost are presented without any methodology, measurements, or citations. The text states that scores were assigned and rated as High, Medium, or Low, but the table uses numeric values with no defined scale orientation (e.g., for 'Overhead' and 'Cost', it is not stated whether 1 or 5 is better). All subsequent trade-off conclusions, including the claimed advantage of parity-management techniques (PL2) and the rationale for ML-based adaptation, derive from this matrix. Section 6 admits that 'Empirical validation of various deletion mechanisms remains a priority for future work,' confirming that the scores are not evidence-based. Without a principled or empirical basis for these numbers, the paper's quantitative balancing claim collapses.","section":"§5, Table 2"},{"comment":"The paper's own descriptions of ECC modulation and flag locking directly contradict their Table 2 scores. For ECC modulation, Section 4.2 states that 'A determined attacker with direct flash access could still extract the underlying bytes, so the method is anti-forensic rather than cryptographically final,' yet Table 2 assigns Efficacy=5. For flag locking, the text says 'the raw bytes still exist' and 'highly sensitive data still needs stronger sanitization,' yet Table 2 assigns Efficacy=5 and Verification=5, and the text also says flag cells require dedicated hardware and redundant SLC copies, which conflicts with a low-cost/low-overhead rating. These contradictions undermine the claimed PL2 privacy advantage and show that the score matrix is not merely unverified but internally inconsistent with the described security properties.","section":"§4.2 vs. Table 2"},{"comment":"The abstract claims that machine learning adjusts privacy levels contextually, 'boosting privacy with negligible performance overhead and complexity.' This claim is not supported by any algorithm description, training methodology, dataset, implementation, or experiment. Section 4.1 describes the AI-based adaptation only in general terms, and Section 6 states that a prototype and empirical measurements remain future work. The 'negligible performance overhead and complexity' assertion is therefore a conjecture presented as a result, and it is load-bearing for the paper's overarching contribution of an adaptive, ML-driven privacy architecture.","section":"Abstract and §4.1, §6"}],"minor_comments":[{"comment":"The heading 'Trad-off between block erase cost and privacy exposure' contains a typo; it should be 'Trade-off'.","section":"§2.2"},{"comment":"The text describing the flowchart says 'P Data Destruction'; this should be clarified as 'Page Data Destruction' or a similar term for consistency with the Level 2 description.","section":"§4.1"},{"comment":"The scale semantics for the numeric scores are undefined; the text mentions ratings of High, Medium, or Low, but the table uses numbers without a mapping, and the direction for 'Overhead' and 'Cost' is ambiguous.","section":"§5, Table 2"},{"comment":"The phrase 'file-aqbd1yjbourpdqkdsbs3vm' appears in the introduction and appears to be an artifact of document preparation; it should be removed.","section":"Introduction"}],"recommendation":"reject","confidential_remarks":"The paper is a conceptual proposal with no empirical or analytical support for its quantitative claims. The central Table 2 is internally contradicted by the text, and the ML adaptation claim is unsupported. The authors' reliance on their own prior work for the underlying deletion techniques is not itself problematic, but the lack of a methodology for the score matrix makes the contribution fragmentary. I do not see a feasible revision within the current scope that would address these load-bearing issues; the authors would need to either substantially reframe the paper as a qualitative position piece or add real empirical evaluation."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is a position paper dressed as a research result. The adaptive privacy-level framing (PL0–PL3) is a clean way to organize secure-deletion techniques for NAND flash, and the three-way taxonomy (address, data, parity) is sensible. The authors clearly know the literature, including their own prior work on ECC modulation and deletion pulses. That part is worth something.\n\nBut there is no implementation, no measurement, no simulation. The quantitative centerpiece, Table 2, is a set of hand-assigned 1–5 scores with no methodology, no source, and no sensitivity analysis. Worse, several scores contradict the paper's own text. ECC modulation and flag locking receive Efficacy=5, yet Section 4.2 admits raw bytes remain physically recoverable and the methods are \"anti-forensic rather than cryptographically final.\" If a determined attacker with chip-off access can still extract the data, an efficacy score of 5 is indefensible. The claimed privacy advantage of PL2 collapses.\n\nThe ML-based automatic level selection is described only in general terms; the abstract's claim of \"negligible performance overhead and complexity\" is unsupported by any experiment or derivation. Section 6 concedes that empirical validation is future work, so the paper's \"quantitative analysis\" is really an opinionated sketch.\n\nWhat's genuinely useful is the framing: privacy level as a tunable cost metric, and the comparison of deletion targets. That could inform a more rigorous empirical study. But as submitted, the paper does not establish its central claims. I agree with the reader's REJECT. It is not a desk-reject because the topic is relevant and the taxonomy has merit, but it would need major revision and real measurements to be acceptable.\n\nIf you have a workshop that accepts vision papers, this might be worth a look as a position statement. Otherwise, I'd advise against spending referee time on it in its current form.","headline":"A sensible taxonomy and privacy-level framing undermined by hand-assigned scores and no experiments.","tokens_in":9425,"tokens_out":3476,"would_cite":false,"duration_ms":41263,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":false},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A four-level adaptive deletion ladder can make SSD privacy protection a tunable cost, not a fixed feature.","keywords":["secure deletion","NAND flash","solid state drive","privacy levels","data remanence","IoT storage","ECC modulation","adaptive privacy"],"falsifier":"On a test SSD with 3D NAND flash, repeatedly delete the same set of pages using scrubbing (PL1) and ECC modulation (PL2), measuring endurance loss and delete latency. If PL2 does not show clearly lower wear and latency than PL1, or if the ECC-poisoned pages' data can be recovered with commodity NAND readers without a full block erase, then the Table 2 ordering that carries the framework collapses.","tokens_in":8435,"feed_emoji":"🔐","tokens_out":7097,"duration_ms":83033,"temperature":0.7,"pith_summary":"This paper argues that complete deletion on NAND-flash SSDs cannot be a one-size-fits-all operation, because block erase is slow and wears the drive, while weaker methods leave recoverable remnants. It proposes an adaptive SSD architecture with four privacy levels—block erase, page scrubbing, parity/ECC destruction, and controller-level block map-out—and claims this graduated menu balances deletion efficacy, latency, endurance, verification, and cost. The paper also sketches how machine learning could pick the right level automatically, though the quantitative case rests on the architectural and method comparison rather than on an implemented ML controller. A sympathetic reader takes away that privacy-preserving storage in resource-constrained IoT devices is a tunable cost problem rather than a single built-in security feature.","feed_headline":"Four privacy levels turn SSD erasure into a tunable trade-off","feed_subtitle":"Privacy can now be dialed per file instead of paying the full cost of block erase every time.","key_machinery":"The load-bearing mechanism is the privacy-level ladder PL0–PL3 mapped to specific deletion techniques, together with the parity-management trick of making a page unreadable by corrupting its ECC parity or locking it with a flag-cell bit in the spare area. These parity techniques let an SSD invalidate a single page on-chip without an immediate block erase, which is what makes low-latency, low-wear deletion possible while still blocking normal readout. The second mechanism is the three-way classification of deletion methods—address management, data management, and parity management—which gives the paper a uniform set of performance axes for comparing methods that operate at very different layers of the storage stack.","core_discovery":"The paper's central claim is an escalation ladder for secure deletion: PL0 uses a full block erase; PL1 destroys target data at page level through scrubbing, overwriting, deletion pulses, or down-level programming; PL2 renders a page unreadable by corrupting its ECC parity or setting a flag cell in the spare area; and PL3 permanently invalidates the physical region through bad-block map-out, paying usable capacity instead of deletion latency. The authors classify all existing deletion methods into address management, data management, and parity management, then score eight techniques on six axes—efficacy, speed, durability, overhead, verifiability, and cost—in Table 2. Their conclusion is that no single technique dominates on all axes, so an adaptive policy that matches deletion strength to data sensitivity and context can outperform uniform deletion policies. The claim is presented as a design guideline for IoT storage rather than as a measured benchmark.","pith_inferences":["The same privacy-level ladder could transfer to managed-flash devices such as eMMC and UFS, which share block-erase granularity and spare-area metadata; the paper's cost axes would need re-scoring for those controllers, but the PL0–PL3 structure likely carries over.","A concrete testable extension is to implement PL1 and PL2 in an FPGA-based flash controller emulator and measure read-fail rate, wear, and latency over tens of thousands of delete cycles; that experiment would turn Table 2's assigned scores into measured curves.","The ML-based level selection could likely be driven by file metadata alone—type, size, and access recency—without environmental sensors, which would make the adaptive controller simpler to deploy on existing IoT hardware than the paper's sensor-oriented sketch suggests.","The verifiability scores hint at a compliance use the paper does not develop: PL2's instant read-fail confirmation could serve as machine-checkable proof of deletion for regulatory or audit purposes, a property slower block erase does not offer."],"forward_implications":["An SSD exposing PL0–PL3 could serve both privacy-critical and performance-critical workloads on the same device, running routine deletions at PL1 or PL2 and reserving block erase and block map-out for high-sensitivity data.","The three-way classification gives designers a selection rule: choose address management when cost dominates, page-level destruction when endurance can be sacrificed, and parity management when low latency, low wear, and verifiability are wanted.","Because PL2 leaves the raw charge in the cells, the paper's own scheme implies that parity-based deletion should be paired with encryption or with eventual full block erase to resist chip-off forensics.","If the Table 2 ordering holds, adaptive level selection should outperform any fixed deletion policy on total cost, since no single method wins on all six axes.","Flag-cell and ECC-modulation methods give verifiable deletion instantly: a failed read or a flipped flag bit serves as immediate confirmation that the page is inaccessible through normal means."],"supporting_citations":[{"why":"It documents residual data persisting in secondhand IoT devices, motivating the need for deletion beyond logical removal.","marker":"[5]"},{"why":"It describes accelerated sub-block erase in 3D NAND flash, grounding the claim that block erase is costly and motivates finer-grained deletion methods.","marker":"[8]"},{"why":"It introduces ECC modulation as an on-chip secure deletion scheme for IoT appliances, the central parity-management technique behind PL2.","marker":"[9]"},{"why":"It analyzes forensic issues and secure-deletion techniques in SSDs with flex capacity, supplying the scrubbing and overwrite baseline for PL1.","marker":"[12]"},{"why":"It details privacy data destruction schemes in NAND flash, including deletion pulses and down-level programming, which are the page-level techniques behind PL1.","marker":"[13]"},{"why":"It presents an architectural flag-cell mechanism for efficient data sanitization, forming the basis of PL2's read-out locking method.","marker":"[15]"}],"fun_headline_variants":["SSD deletion becomes context-aware with four privacy tiers","Machine learning picks deletion strength per file on IoT SSDs","Four-tier privacy erasure: from block erase to capacity trade-off","Adaptive SSD privacy: tune deletion cost against data sensitivity","Privacy levels for SSD deletion: from full erase to bad-block mapping"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the 1-to-5 scores in Table 2—for efficacy, speed, durability, overhead, verifiability, and cost of eight deletion techniques—are meaningful and correct; the paper presents them without measurements, sources, or methodology, and every privacy-versus-performance conclusion in the paper derives from that matrix.","fun_headline_variants_meta":{"raw":{"variants":["SSD deletion becomes context-aware with four privacy tiers","Machine learning picks deletion strength per file on IoT SSDs","Four-tier privacy erasure: from block erase to capacity trade-off","Adaptive SSD privacy: tune deletion cost against data sensitivity","Privacy levels for SSD deletion: from full erase to bad-block mapping"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000165,"raw_usage":{"total_tokens":1160,"prompt_tokens":765,"completion_tokens":395,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":381,"completion_tokens_details":{"reasoning_tokens":311}},"tokens_in":381,"tokens_out":395,"duration_ms":4912,"temperature":1.0,"reasoning_tokens":311,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T12:17:27.185157+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On a test SSD with 3D NAND flash, repeatedly delete the same set of pages using scrubbing (PL1) and ECC modulation (PL2), measuring endurance loss and delete latency. If PL2 does not show clearly lower wear and latency than PL1, or if the ECC-poisoned pages' data can be recovered with commodity NAND readers without a full block erase, then the Table 2 ordering that carries the framework collapses.","supporting_citations":[{"cited_title":"Secondhand Smart IoT Devices Data Recovery and Digital Investigation,","cited_arxiv_id":null,"evidence_quote":"It documents residual data persisting in secondhand IoT devices, motivating the need for deletion beyond logical removal."},{"cited_title":"Accelerating Sub -Block Erase in 3D NAND Flash Memory,","cited_arxiv_id":null,"evidence_quote":"It describes accelerated sub-block erase in 3D NAND flash, grounding the claim that block erase is costly and motivates finer-grained deletion methods."},{"cited_title":"IoT security: On -chip secure deletion scheme using ECC modulation in IoT appliances","cited_arxiv_id":null,"evidence_quote":"It introduces ECC modulation as an on-chip secure deletion scheme for IoT appliances, the central parity-management technique behind PL2."},{"cited_title":"Forensic Issues and Techniques to Improve Security in SSD With Flex Capacity Feature,","cited_arxiv_id":null,"evidence_quote":"It analyzes forensic issues and secure-deletion techniques in SSDs with flex capacity, supplying the scrubbing and overwrite baseline for PL1."},{"cited_title":"Schemes for Privacy Data Destruction in a NAND Flash Memory,","cited_arxiv_id":null,"evidence_quote":"It details privacy data destruction schemes in NAND flash, including deletion pulses and down-level programming, which are the page-level techniques behind PL1."},{"cited_title":"Evanesco: Architectural support for efficient data sanitiz ation in modern flash-based storage systems","cited_arxiv_id":null,"evidence_quote":"It presents an architectural flag-cell mechanism for efficient data sanitization, forming the basis of PL2's read-out locking method."}],"review_version":1}