{"id":"1253a2a3-bc3a-4f92-8744-c43daf633668","arxiv_id":"2506.07665","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"FREESS is an open-source educational simulator that visualizes Tomasulo-based superscalar execution, including register renaming, reorder buffer, and load/store queues, cycle by cycle.","lead":"FREESS is a free, open-source command-line simulator that shows, cycle by cycle, how a RISC-V-inspired superscalar processor using Tomasulo's algorithm executes instructions out of order. It is built for computer architecture classrooms: students can change issue widths, buffer sizes, and unit latencies, and print a trace that matches a paper-and-pencil exercise.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The cycle-accuracy claim is unverified: no test suite or independent trace checks the simulator's Tomasulo semantics, and the provided screenshots are generated by the same code being validated.","rationale":"Good-faith reading: the paper is a workshop tool description; its claims are about usability and correctness of an educational simulator. I found no demonstrated arithmetic contradiction in the examples (e.g., 21 instructions / 20 cycles = IPC 1.05, and 15 instructions / 14 cycles ≈ IPC 1.07 are consistent). I also considered whether §3.3.2's description of always-taken branch handling is internally inconsistent with fetch redirection to the branch target, but the machine-code listing is not sufficient to distinguish a wording artifact from a real simulator bug; the proposed golden-trace test would settle it. The most load-bearing gap is the absence of any independent check that the C implementation matches the described Tomasulo semantics. The reader's weakest assumption was exactly this unverified implementation correctness, and the CONDITIONAL verdict is appropriate: with the golden-trace test the tool could be accepted; without it, the central cycle-accuracy and pedagogical claims are not established.","tokens_in":10149,"tokens_out":8128,"duration_ms":95857,"concrete_test":"Clone and compile https://github.com/robgiorgi/freess, then run all three shipped examples with the parameters shown in Figures 11, 14, and 15, capturing the full per-cycle screen and stall.log. Build an independent golden trace for the same machine-code programs using a small reference Tomasulo model that allocates physical registers from the free pool, records source readiness in the IW, issues ready instructions to FUs with the stated latencies, broadcasts write-backs, commits in order, and redirects fetch to the predicted-taken target. Diff every cycle's RM, FP, IW, ROB, LQ, and SQ entries and the final IPC/stall counters. Any discrepancy invalidates the cycle-accurate claim; a match would substantiate it for the shipped examples.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim is that FREESS provides a cycle-accurate view of the Tomasulo-based superscalar structures (Contributions, §1) and that students can reproduce the trace by hand. That claim requires the simulator's C code to implement renaming, IW/ROB allocation, issue, write-back, commit, and always-taken branch speculation exactly as described in §3.3. The paper provides no executable test suite, no golden per-cycle trace, and no comparison against an independent reference model; Appendix A only gives a repository URL. The three examples are internally plausible, but that is weak evidence here: the screenshots are produced by the same untested code that the claim is about. An off-by-one in the Cj/Ck readiness timestamps or in the branch-fetch redirect would change the issue/commit cycles and IPC while still yielding self-consistent, printable output. Since the pedagogical value is specifically that students can verify the machine's behavior on paper, any such bug would propagate the wrong dynamic-scheduling semantics.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents FREESS, an educational C simulator of a RISC-V-inspired superscalar processor implementing a Tomasulo-based dynamic scheduling algorithm. The tool models fetch, rename, dispatch, issue, execute, write-back, commit, and branch speculation, with configurable widths, buffer sizes, and latencies. The paper describes the tool's parameters and screen layout, walks through a first example in detail, reports IPC and stall statistics for two further examples, and gives an informal account of classroom use since 2010. The stated contributions are a paper-and-pencil teaching methodology aligned with a single-screen cycle-by-cycle view, a 'cycle-accurate' simulator, and an open-source release.","tokens_in":10300,"tokens_out":4987,"duration_ms":56710,"significance":"FREESS addresses a real pedagogical gap with a single-screen, text-based visualization that students can reproduce on paper, and it is implemented in a compact, portable C codebase (~2000 lines) with three runnable examples. The open-source repository and command-line configuration are practical strengths. If the simulator's behavior is correct, the three examples provide useful reference exercises and the reported IPC/stall statistics are plausible teaching material. However, the paper does not itself establish that correctness, and the educational-impact evidence is anecdotal, leaving the two central claims only partially supported.","major_comments":[{"comment":"The central claim that FREESS 'provides a cycle-accurate view' (Contributions, §1) is not verified by any independent reference. The only evidence for correctness is the simulator's own screenshots (e.g., Fig. 2, 7-11, 14-15) and the repository URL in Appendix A. Because the proposed teaching method assumes students can reproduce the trace on paper, a bug in the ~2000-line C code would silently propagate incorrect dynamic-scheduling semantics. I recommend adding to the repository a golden-trace test suite for the three examples, with per-cycle states of the RM, FP, IW, ROB, LQ/SQ, and stall counters, and a statement of how these traces were validated (hand trace or independent reference model).","section":"§1 Contributions; §3.3"},{"comment":"The educational-effectiveness claim ('effective teaching tool', Abstract and §5) rests on anecdotal self-reports ('students consistently report feeling more confident') and 15 years of classroom use, with no student-performance data, no comparison with a control condition or alternative tool, and no analysis of exam results. Since this is one of the two stated contributions, please provide quantitative evidence (e.g., pre/post test scores, pass rates on manual-trace exercises) or temper the claim to 'anecdotal classroom experience suggests promise.'","section":"§5 Impact"},{"comment":"The instruction encoding and branch-redirect policy are underspecified, preventing independent verification of the IPC and stall counts. In §3.2 the machine-code lines (e.g., '1 3 4 0') do not define the field order, and the branch immediate is described only as 'the number of instructions to jump' without stating whether the target is PC+4+imm or PC+imm, or when the fetch is redirected (decode vs. branch resolution). §3.3.2 says the branch 'forces the fetch stage to break fetching,' but no cycle is given for the redirect. Please add a precise encoding table and a worked branch-target calculation for the Example-1 loop so that the reported trace (IPC 1.05, 20 cycles) can be reproduced.","section":"§3.2, §3.3.2"}],"minor_comments":[{"comment":"Reference [1] appears as 'SIMDE [1]]' with a duplicate closing bracket.","section":"§2"},{"comment":"'adoptsuperscalar' is missing a space and should read 'adopts superscalar'.","section":"§1"},{"comment":"The sentence 'In the first example (Fig. 13), we got 9 stalls...' cites Fig. 13, which is the auto-generated text for Example-2, not the first example; the stall counts presumably refer to Example-1 in Fig. 9 or Fig. 11.","section":"§4.1"},{"comment":"'Ci indicates the cycle when the reload is queued' should likely read 'when the load is queued'.","section":"§3.3.4"},{"comment":"Reference [5] formatting: 'InICS’24' should be 'In ICS’24'.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The paper's self-citation of WebRISC-V is contextual and not problematic. The main issue is the gap between the strong 'cycle-accurate' claim and the absence of validation; for a workshop venue, a call for a test suite and a modest educational evaluation is proportionate. You may want to verify that the repository is public and runnable before acceptance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"FREESS is a serious, unpretentious teaching tool. The genuinely new thing is the single printable text screen that mirrors a sheet of paper: students see the full cycle-by-cycle evolution of the register map, IW, ROB, and queues in one place, and can reproduce the trace by hand. That is a real pedagogical contribution, and the paper explains it clearly. The stall-cause log is also a plus; it turns 'why did IPC drop?' from a black box into an explicit list of cycles and reasons. The three examples are internally consistent, the parameter sweep is well motivated, and the writing is straightforward.\n\nThe soft spots are real but proportionate. The 'cycle-accurate' claim in the contributions is asserted, not demonstrated. There is no test suite, no golden trace, no comparison against an independent reference model. The screenshots are produced by the same code being validated, so an off-by-one in a Cj/Ck timestamp would propagate wrong semantics into the printed output and still look plausible. For a teaching tool this is not fatal—the value is the workflow, not the exact cycle counts—but a determined student could be misled. The educational impact section rests on an informal 'students consistently report feeling more confident' line; that is anecdotal, but honestly labeled as experience, not a study.\n\nThe citation pattern is fine. The only self-citation is WebRISC-V, which is contextual. The paper also correctly limits its scope: it explicitly says it is not a production tool and lists what it does not model.\n\nThe paper is exactly what a workshop on computer architecture education should publish: a clear description of a working open-source tool, a concrete teaching workflow, and honest limitations. It deserves a serious referee, and with a small request—put a few golden traces in the repository, or at least a self-check mode that compares the simulator's output against a hard-coded expected result—the accuracy concern becomes much smaller.","headline":"A genuinely useful teaching simulator whose central 'cycle-accurate' claim is plausible but unverified; worth reviewing with a request for a test suite.","tokens_in":10822,"tokens_out":1774,"would_cite":false,"duration_ms":18750,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims FREESS gives students a cycle-accurate, paper-traceable view of a Tomasulo-based superscalar processor, backed by three worked examples and a configurable open-source simulator.","keywords":["superscalar processor","Tomasulo's algorithm","out-of-order execution","educational simulator","RISC-V","register renaming","reorder buffer","instruction-level parallelism"],"falsifier":"Hand-trace Example 1 on paper and compare it cycle by cycle with the printed output: if any IW-slot readiness flag, ROB completion flag, or stall counter disagrees with the documented Tomasulo semantics—or if the final reported IPC is not 1.05 over 20 cycles—the simulator does not provide the claimed cycle-accurate view.","tokens_in":9907,"feed_emoji":"🖥️","tokens_out":4888,"duration_ms":52350,"temperature":0.7,"pith_summary":"The paper presents FREESS, a command-line simulator that claims to provide a cycle-accurate view of the key hardware structures of a RISC-V-inspired superscalar processor built on an extended Tomasulo algorithm. The goal is pedagogical: students watch fetch, rename, dispatch, issue, execute, write-back, and commit for tiny programs while seeing the Instruction Window, Register Map, Free Pool, Reorder Buffer, and Load/Store Queues update every cycle. The simulator is designed so its entire textual output can be replicated on a single sheet of paper, letting students verify by hand what the machine does. If the claim is right, FREESS gives advanced computer-architecture courses a lightweight, open, configurable tool for teaching out-of-order execution and understanding stall causes.","feed_headline":"FREESS shows a Tomasulo superscalar's state, cycle by cycle, on one screen","feed_subtitle":"A free C simulator lets students trace fetch, rename, dispatch, issue, execute, and commit by hand, matching every printed line.","key_machinery":"The central object is the single-screen, cycle-by-cycle textual state display driven by an extended Tomasulo algorithm—rename registers through a free pool, issue instructions as soon as their source values are ready, and commit in program order through a reorder buffer. Each instruction carries a dynamic program counter and records the cycle it enters F (fetch), D (decode/rename), P (dispatch), I (issue), X (execute), W (write-back), and C (commit); alongside it, the screen shows the register map and free pool, the instruction window slots with source-ready flags, the ROB slots with old-physical-register and completion flags, the load/store queues, and a set of stall counters. These structures together determine when instructions issue, write back, and commit, and the printed state is meant to match what a student could write on paper.","core_discovery":"FREESS claims that a superscalar machine's dynamic behavior—how instructions flow through an out-of-order pipeline and how architectural resources are consumed—can be captured on a single text screen and traced by hand. The simulator models seven RISC-V-like instructions (ADD, ADDI, BEQ, BNE, LW, MUL, SW), assumes branches are speculatively taken, and shows each cycle the state of physical registers, the register map, the free pool, the instruction window, the ROB, the load/store queues, and stall counters. Its three worked examples report concrete results: a 21-instruction vector loop yields 1.05 IPC over 20 cycles in the default 4-way configuration, a shorter five-instruction loop reaches 1.36 IPC with a 12-slot window, and the same loop on a 2-way machine drops to 1.07 IPC with identical total stalls. The author's main claim is that this provides a cycle-accurate visualization of the key Tomasulo structures, making dynamic scheduling teachable by direct observation and manual verification.","pith_inferences":["If the simulator's semantics are correct, the same engine could serve as a reference model for validating student-written Tomasulo implementations, since every internal structure is printed each cycle.","Because branches are assumed always taken, the tool presently illustrates misspeculation rollback only through ROB state and saved old physical registers; adding a configurable predictor would let students study prediction accuracy without changing the core teaching loop.","The minimal seven-instruction ISA and manual opcode entry could naturally extend toward deeper memory-hierarchy effects, such as store-to-load forwarding, while keeping the single-screen teaching interface intact."],"forward_implications":["Students can verify a full superscalar trace by hand: the on-screen layout is designed to match a paper worksheet, so a traced solution can be compared cycle by cycle with the simulator.","Configurable widths and latencies let an instructor generate fresh exercises and let students see the direct effect of dispatch width, issue width, window size, and functional-unit counts on IPC and on where stalls occur.","The stall log and per-stage counters turn bottleneck analysis into a concrete exercise: students can identify whether a stall is structural, data, or control related by reading the logged cycle and reason.","The three prebuilt examples give reproducible baselines (IPC 1.05, 1.36, and 1.07) that a correctly implemented simulator should reproduce, supporting self-checking during coursework."],"supporting_citations":[{"why":"Supplies the original Tomasulo algorithm that FREESS implements and visualizes with extended structures.","marker":"[11]"},{"why":"SIMDE is an earlier ILP teaching simulator using Tomasulo and scoreboarding, whose status-table approach FREESS extends to a unified cycle-by-cycle screen.","marker":"[1]"},{"why":"SATSim is the interactive superscalar trace simulator that FREESS contrasts with, adding stall diagnostics and load/store queue modeling.","marker":"[12]"},{"why":"PSATSim extends SATSim with power and performance metrics but lacks the per-cycle pipeline visualization FREESS provides.","marker":"[9]"},{"why":"Jaros is a web-based RISC-V superscalar simulator used as a comparison point for architectural configurability and memory pipeline modeling.","marker":"[5]"},{"why":"Ripes models RISC-V pipelines without detailed superscalar support, serving as a baseline that lacks the structures FREESS shows.","marker":"[8]"},{"why":"The Hennessy and Patterson textbook supplies the conceptual vocabulary for Tomasulo, reorder buffers, and superscalar execution that the course and tool rely on.","marker":"[3]"}],"fun_headline_variants":["Tomasulo superscalar, cycle by cycle, on one screen","Free simulator puts Tomasulo's algorithm on single screen","FREESS: Trace superscalar pipeline cycles by hand","Single-screen view of Tomasulo superscalar teaches ILP","See every pipestage of a RISC-V superscalar, one cycle at a time"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"Everything rests on the unverified premise that the simulator's C implementation actually behaves as described—that the register map, free pool, instruction window, ROB, load/store queues, branch speculation, and stall counters all follow the intended Tomasulo semantics exactly.","fun_headline_variants_meta":{"raw":{"variants":["Tomasulo superscalar, cycle by cycle, on one screen","Free simulator puts Tomasulo's algorithm on single screen","FREESS: Trace superscalar pipeline cycles by hand","Single-screen view of Tomasulo superscalar teaches ILP","See every pipestage of a RISC-V superscalar, one cycle at a time"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000218,"raw_usage":{"total_tokens":1488,"prompt_tokens":1040,"completion_tokens":448,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":656,"completion_tokens_details":{"reasoning_tokens":355}},"tokens_in":656,"tokens_out":448,"duration_ms":5423,"temperature":1.0,"reasoning_tokens":355,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T05:28:43.735832+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Hand-trace Example 1 on paper and compare it cycle by cycle with the printed output: if any IW-slot readiness flag, ROB completion flag, or stall counter disagrees with the documented Tomasulo semantics—or if the final reported IPC is not 1.05 over 20 cycles—the simulator does not provide the claimed cycle-accurate view.","supporting_citations":[{"cited_title":"Tomasulo","cited_arxiv_id":null,"evidence_quote":"Supplies the original Tomasulo algorithm that FREESS implements and visualizes with extended structures."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"SATSim is the interactive superscalar trace simulator that FREESS contrasts with, adding stall diagnostics and load/store queue modeling."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"PSATSim extends SATSim with power and performance metrics but lacks the per-cycle pipeline visualization FREESS provides."},{"cited_title":"Petersen","cited_arxiv_id":null,"evidence_quote":"Ripes models RISC-V pipelines without detailed superscalar support, serving as a baseline that lacks the structures FREESS shows."},{"cited_title":"Hennessy and David A","cited_arxiv_id":null,"evidence_quote":"The Hennessy and Patterson textbook supplies the conceptual vocabulary for Tomasulo, reorder buffers, and superscalar execution that the course and tool rely on."}],"review_version":1}