{"id":"6692d4ed-9f76-4939-9b2e-20dec473ae34","arxiv_id":"2506.09856","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A multi-FPGA clock synchronization and fiber data communication framework for the QubiC control stack passes bench tests, keeping three boards synchronized for 16 hours and enabling cross-board feed-forward at about 1600 ns.","lead":"This paper shows how several FPGA boards can share one precise clock and exchange quantum measurement results over fiber, so qubit control pulses stay time-aligned across many boards. It matters because open-source, low-cost multi-board control is a known bottleneck for scaling superconducting quantum computers beyond about ten qubits.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The central time-aligned claim rests on indirect evidence: per-board jitter and an unspecified-resolution counter-offset test, with no direct cross-board RF phase or skew measurement.","rationale":"The reader's weakest assumption identifies exactly the same load-bearing gap: the paper's headline synchronization claim is supported by per-board jitter and an unspecified-resolution counter test, but not by a direct measurement of relative RF phase between boards. I agree with that reading. The feed-forward demonstration is genuine evidence that the data communication path works and that the two boards are functionally coordinated at the pulse-trigger level, and the jitter numbers are useful for understanding single-output stability. However, none of the reported measurements bounds the absolute inter-board skew, which is the quantity that matters for phase-aligned qubit control. The zero-delay PLL and matched-cable design make the claim plausible, but the paper itself does not quantify residual skew or lock asymmetry. This is an engineering demonstration where the missing measurement is straightforward to perform with commonly available lab equipment, so the appropriate verdict remains CONDITIONAL, not REJECT. I would not change the reader's verdict; I would only emphasize that the cross-board phase test is the single decisive experiment for the central claim.","tokens_in":8621,"tokens_out":2748,"duration_ms":37028,"concrete_test":"Connect the RF outputs of Board 1 and Board 2 to two channels of a single high-bandwidth oscilloscope sharing a common timebase, program both boards to emit identical synchronized pulses at 6.50 GHz, and measure the residual inter-board phase/skew. Repeat the measurement over a 16-hour run and after several PLL re-locks or re-boots to check stationarity and determinism. Also report the counter resolution used in the 16-hour offset test. If the measured skew is within the target tolerance (e.g., a few picoseconds or about 1 degree at 6.5 GHz) and is repeatable across re-locks, the time-aligned claim is supported; otherwise it should be qualified accordingly.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim is that multiple RFSoC boards generate time-aligned RF pulses for quantum control (Sections III and V). The supporting evidence is: (1) single-output RMS jitter of 1.8 ps and 7.4 ps at 6.50 GHz, measured on an individual signal, and (2) a 16-hour test reporting a counter offset of zero across boards. Neither measurement establishes the relative phase of two boards' RF outputs. A low-jitter output is fully compatible with a constant, board-specific timing skew relative to another board; the same is true of numerically synchronized counters if the DAC sample clocks on different boards have different phase offsets relative to their counters. The paper asserts matched-length cables and zero-delay PLL configuration produce deterministic phases, but it does not report any measurement of residual cable skew, PLL lock asymmetry, or SYSREF alignment across boards. The 16-hour zero-offset result is also quoted without stating the counter resolution, so the bound it provides on timing error is unknown. Consequently, the phrase 'perfectly phase-synchronized' in Section III is stronger than the Section V data can support, and the practical claim of time-aligned qubit control pulses is plausible but not directly demonstrated.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a clock synchronization and data-communication framework for multi-FPGA RFSoC-based quantum control, integrated into the open-source QubiC system. Clock synchronization is achieved by distributing a 10 MHz reference over matched-length cables, using zero-delay PLL and multi-tile synchronization on each board, and running a minimal PTP protocol over copper links in a ring topology to align clock counters. Data communication uses the Aurora 64B/66B protocol over four SFP fiber links in a star topology, with readout and feed-forward state machines that broadcast measurement results across boards. The authors report single-output RF jitter of 1.8 ps RMS (10 Hz--100 MHz) and 7.4 ps RMS (0.1 Hz--100 MHz) at 6.50 GHz, a 16-hour test with zero counter offset across boards, and a room-temperature qubit readout emulator demonstration of mid-circuit measurement and conditional feed-forward in which Board 2 emits pulses conditioned on Board 1 measurement results, with an observed start-to-conditional-pulse interval of about 1600 ns. The paper claims to provide the first open-source solution for multi-FPGA time synchronization and data communication for quantum control.","tokens_in":8817,"tokens_out":4345,"duration_ms":56024,"significance":"If the central synchronization claim holds, the work is a valuable open-source building block for scaling superconducting-qubit control beyond a single RFSoC board. The manuscript has concrete strengths: it reports measured jitter numbers, a 16-hour stability test, a working end-to-end feed-forward demonstration on emulated readout, and detailed engineering choices (Aurora configuration, GPIO-based minimal PTP, ring topology, star data network) that are directly useful to practitioners. The integration with QubiC also makes the contribution easier to adopt. However, the load-bearing claim that RF pulses on different boards are time-aligned and 'perfectly phase-synchronized' is supported only indirectly: the jitter measurement is per-board, and the 16-hour test is a digital counter comparison. A direct cross-board RF phase or skew measurement is absent, so the central contribution is plausible but not yet demonstrated at the level the paper claims.","major_comments":[{"comment":"The central claim of time-aligned RF pulses across multiple boards is not directly measured. The reported 1.8 ps and 7.4 ps RMS jitter values are measured on individual output signals with a signal source analyzer; they characterize single-output noise, not the relative phase between two boards' RF outputs. The 16-hour counter-offset test is a digital counter comparison, and synchronized counters do not by themselves guarantee synchronized DAC sample-clock phases unless the PLL/SYSREF alignment is also verified. Please add a direct cross-board measurement, for example capturing the RF outputs of two boards on a high-bandwidth oscilloscope and reporting the measured channel-to-channel phase or time skew (with cable delays calibrated out), or report the measured SYSREF alignment and PLL lock phase across boards. Without such a measurement, the phrase 'perfectly phase-synchronized' in Section III is stronger than the evidence in Section V supports.","section":"Section V, Experiments"},{"comment":"The statement that 'all boards remained synchronized with a counter offset of zero' over 16 hours is reported without stating the counter resolution, tick period, or the method used to measure the offset. A zero offset could mean simply that the offset is less than one counter tick, and if the counter tick is, for example, a sample clock period of a few nanoseconds, the bound on timing error would be far looser than the sub-picosecond jitter quoted elsewhere. Please state the counter clock frequency and the resolution of the offset measurement, and clarify whether the PTP offset correction was applied once at boot or periodically during the test. This is necessary to interpret the test as evidence for sustained RF phase alignment.","section":"Section V, 16-hour test"},{"comment":"The paper quotes a data-communication latency of approximately 450 ns (Section V, 'hold latency') but does not present an isolated measurement of that latency. The observed 1600 ns interval between the start pulse and the conditional pulse on Board 2 is the sum of the 1 microsecond readout pulse, the 600 ns hold, and the actual communication/demodulation latency, so it does not independently verify the 450 ns figure. Please provide a direct latency measurement, for example a loopback test with timestamps at the transmitting and receiving boards, and report the link jitter and CRC error behavior. This is needed to support the 'hundreds of nanoseconds' latency claim that motivates the feed-forward architecture.","section":"Section V, data communication latency"},{"comment":"The minimal PTP offset calculation assumes symmetric transit times between the two GPIO ports, but the paper provides no measurement or calibration of the asymmetry of the copper link. Any fixed asymmetry in the transmit or receive paths directly biases the computed clock offset and hence the counter alignment. Please report the measured or estimated asymmetry of the synchronization link, or at least quantify the residual offset after correction. With the current presentation, the accuracy of the PTP-based counter synchronization is not bounded independently of the unsupported assumption of symmetric transit times.","section":"Section III, minimal PTP"}],"minor_comments":[{"comment":"There are typographical and naming inconsistencies: 'synotization' should be 'synchronization', 'Prestol' appears to be 'Presto', and 'Linayage et al.' should likely be 'Liyanage et al.'.","section":"Section II, Related Work"},{"comment":"The phrase 'prolong period' should be 'prolonged period'.","section":"Section V, Experiments"},{"comment":"The indentation of the else and if statements in the pseudocode makes the control-flow nesting ambiguous; please clarify which else corresponds to which if, or use explicit braces or labels.","section":"Listing 1"},{"comment":"The caption states that the pulses generated by Board 2 are 'shown in red', but the figure description does not identify which trace is Board 1's readout pulse and which are Board 2's conditional pulses; please label the traces explicitly.","section":"Figure 3"},{"comment":"The sentence 'connects to the rest of the design through a 64-bit data and a valid signal interface, two per lane' is incomplete and awkward; please rephrase to state clearly how many interfaces per lane are used and how they connect to the control system.","section":"Section IV, Data Communication"},{"comment":"The claim of being 'the first open-source solution for multi-FPGA time synchronization and data communication in the quantum domain' should be qualified, since open-source systems such as ARTIQ/DRTIO already provide distributed real-time I/O; the comparison in Section II should more clearly state what is new relative to those systems, e.g., the RFSoC-specific implementation and the integration with QubiC.","section":"Section VI, Conclusion"}],"recommendation":"major_revision","confidential_remarks":"This is an engineering paper with a plausible and potentially useful architecture, and the end-to-end feed-forward demonstration is encouraging. The main obstacle to acceptance is that the paper's central synchronization claim is not backed by a direct cross-board RF phase or skew measurement, and the 16-hour test lacks resolution details. These are fixable within the scope of the manuscript by adding targeted measurements. If the authors add such measurements and report the counter resolution and isolated data-communication latency, I would support acceptance. The paper fits a quantum-control engineering venue, though the presentation would benefit from more precise claims relative to existing open-source distributed control systems."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take on arXiv:2506.09856. This is a straightforward engineering contribution: the authors add a minimal PTP ring for clock synchronization plus Aurora fiber links for data to the QubiC control system, with a job server that lets multi-board programs execute and do cross-board feed-forward. That integration is genuinely new in the open-source RFSoC space. The demonstration is honest and concrete: conditional pulses on board 2 after a readout on board 1 appear with the expected ~1600 ns latency, and a 16-hour counter stability run is reported. The design choices are sensible too: matched-length clock cables, zero-delay PLLs, four single-lane Aurora cores instead of one multi-lane core, and the compiler/job-server modifications are described clearly.\n\nThe soft spots are real but not fatal. The central claim is time-aligned RF pulses across boards, but the evidence is per-board jitter (1.8 ps RMS on an individual output) plus a counter-offset test with no stated resolution. Neither directly measures the relative phase of two boards' DAC outputs. A constant, deterministic skew between boards would not show up in either measurement. The 450 ns data-communication latency is stated as a design estimate, not isolated empirically. And the open-source promise has no repository link or artifact listing in the paper itself.\n\nThe stress-test note is on target: the phrase \"perfectly phase-synchronized\" in Section III is stronger than the Section V data support. That said, the demo does exercise the data path end-to-end and the timing budget matches, so the system almost certainly works; it is just a matter of measuring the residual phase skew directly. For a control system aimed at superconducting qubits, that measurement matters.\n\nThe citation pattern is fair, and the \"first open-source solution\" claim is defensible in the narrow sense of a multi-board QubiC/RFSoC system with integrated data communication. I would send this to a serious referee. It is a solid systems paper that the quantum control community will find useful, and the gaps are fixable with straightforward additional measurements: direct cross-board phase comparison, counter resolution, isolated latency characterization, and a pointer to the code.\n\nFor a reading group, it is a maybe, mainly for people working on control hardware. I would not cite it in my own work in the next twelve months unless I were building an RFSoC control stack, but I do want it in the literature.","headline":"A credible, useful engineering report on multi-board RFSoC synchronization and data links for QubiC; the demo works, but the headline time-alignment claim is one direct cross-board measurement short of being fully nailed.","tokens_in":9383,"tokens_out":1702,"would_cite":false,"duration_ms":21093,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A multi-FPGA clock synchronization and fiber data link makes cross-board quantum feed-forward practical on open-source RFSoC control systems.","keywords":["multi-FPGA synchronization","RFSoC","quantum control","clock distribution","Precision Time Protocol","Aurora 64B/66B","mid-circuit measurement","feed-forward"],"falsifier":"Measure the phase of a continuous 6.5 GHz tone generated simultaneously on two boards against the same reference: if the residual inter-board phase skew exceeds the few-picosecond level implied by the jitter numbers, or drifts beyond the timing tolerance of the qubit controls over a 16-hour run, the central synchronization claim is refuted.","tokens_in":8399,"feed_emoji":"⚛️","tokens_out":6088,"duration_ms":59673,"temperature":0.7,"pith_summary":"Quantum processors with more than about ten qubits outgrow a single FPGA control board, and commercial multi-board control systems are expensive and proprietary. This paper claims to close that gap with an open-source method for synchronizing multiple RFSoC boards so their qubit-control pulses are time-aligned, and for moving readout results between boards over fiber quickly enough for mid-circuit measurement and feed-forward. The authors report 1.8 ps RMS jitter on a 6.50 GHz output, a 16-hour test with clock counters staying at zero offset across three boards, and a cross-board conditional pulse about 1600 ns after a 1 µs readout. If these bench results hold on real chips, academic labs could build large-scale quantum control systems from commodity evaluation boards.","feed_headline":"Multi-board clock sync sends quantum feedback in 1.6 microseconds","feed_subtitle":"Open-source system time-aligns RFSoC boards and transfers readout results over fiber, enabling mid-circuit measurement across boards.","key_machinery":"The load-bearing object is the clock-synchronization chain: a shared 10 MHz reference is distributed on matched-length cables into each board's LMK04828 clock chip, whose nested PLLs run in zero-delay mode with SYSREF as feedback, after which Xilinx multi-tile synchronization aligns DAC/ADC tiles on each board. A separate minimal PTP exchange over copper adjusts the counter offsets between neighboring boards in a ring. Data rides on Aurora 64B/66B at 10.3125 Gbps over SFP fiber, managed by readout and feed-forward finite-state machines that format quantum results into 64-bit frames.","core_discovery":"The paper's central claim is that a nested dual phase-locked loop configured in zero-delay mode, driven by a shared 10 MHz reference over matched-length cables and corrected by a minimal Precision Time Protocol exchange, makes the RF phase plane of separate boards common, while a 10.3125 Gbps Aurora fiber link carries measurement results between boards with about 450 ns latency. Together these enable time-aligned qubit drive pulses across boards and conditional pulses on one board based on a readout on another, demonstrated with a room-temperature readout emulator using a two-qubit mid-circuit measurement and feed-forward program.","pith_inferences":["The 16-hour zero-counter-offset result validates the counter-alignment loop, but it does not directly bound residual RF phase skew between two boards' outputs; a direct inter-board phase-noise measurement would be the next validation step.","The reported 450 ns communication latency likely includes protocol overhead and FIFO crossings; an optimized version might approach the hundreds-of-nanoseconds target needed for tighter feedback loops, such as real-time decoders.","Ring-topology offset corrections propagate node-to-node, so error growth with many boards is untested; a star-sync or tree-sync variant might scale better beyond a handful of boards.","The bench tests use a room-temperature readout emulator, so the next testable extension is the same mid-circuit measurement and feed-forward circuit on a real superconducting chip with multiple control boards."],"forward_implications":["Academic labs can assemble multi-board control systems from three ZCU216-class boards without proprietary backplanes or vendor licensing.","Mid-circuit measurement and feed-forward, including cross-board conditional operations, complete in about 1.6 µs, comfortably inside tens-of-microseconds qubit coherence times.","The ring topology with identical bitstreams per board means adding another board does not require redesigning the synchronization logic.","The 64-bit frame format supports results for up to 21 qubits per frame, with frame count and inter-frame delay customizable for larger chips.","Because the data link uses standard Aurora and AXI4-Stream, the communication module can interoperate with general-purpose high-speed networking equipment."],"supporting_citations":[{"why":"QubiC 2.0: the open-source control system into which the clock synchronization and data communication modules are integrated.","marker":"[13]"},{"why":"ZCU216 RFSoC evaluation board: the hardware platform on which all three boards in the experiment run.","marker":"[12]"},{"why":"LMK04828 clock chip: provides the nested dual PLL in zero-delay mode and SYSREF generation that distribute the deterministic clock.","marker":"[38]"},{"why":"Multi-Tile Synchronization: the Xilinx procedure that aligns DAC/ADC tiles on each board to a common SYSREF event.","marker":"[39]"},{"why":"Aurora 64B/66B: the serial protocol over fiber that carries measurement data between boards at 10.3125 Gbps.","marker":"[40]"},{"why":"IEEE 1588 Precision Time Protocol: the standard whose minimal implementation the paper uses for counter-offset correction between boards.","marker":"[27]"},{"why":"White Rabbit: prior synchronization scheme achieving sub-nanosecond sync, used here as the baseline that the copper-link minimal PTP competes with.","marker":"[26]"},{"why":"Presto: a clock-synchronized multi-board open-source system that lacks integrated data communication, the comparison that motivates this work's fiber link.","marker":"[14]"}],"fun_headline_variants":["Multi-FPGA sync and fiber link enable 450 ns quantum feedback","Open-source multi-board quantum control with 450 ns fiber feedback","Clock sync + Aurora fiber: multi-FPGA quantum feedback in 450 ns","Multi-board sync and fiber data link for real-time quantum feedback","RFSoC boards time-aligned, fiber feedback at 450 ns for quantum control"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The time-alignment claim assumes that matched-length reference clock cables plus the zero-delay PLL configuration make the 10 MHz clock arrive at every board with equal, deterministic phase, and that the software counter correction aligns the RF phase plane across boards.","fun_headline_variants_meta":{"raw":{"variants":["Multi-FPGA sync and fiber link enable 450 ns quantum feedback","Open-source multi-board quantum control with 450 ns fiber feedback","Clock sync + Aurora fiber: multi-FPGA quantum feedback in 450 ns","Multi-board sync and fiber data link for real-time quantum feedback","RFSoC boards time-aligned, fiber feedback at 450 ns for quantum control"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001172,"raw_usage":{"total_tokens":4808,"prompt_tokens":871,"completion_tokens":3937,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":487,"completion_tokens_details":{"reasoning_tokens":3840}},"tokens_in":487,"tokens_out":3937,"duration_ms":26569,"temperature":1.0,"reasoning_tokens":3840,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T04:38:49.147233+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the phase of a continuous 6.5 GHz tone generated simultaneously on two boards against the same reference: if the residual inter-board phase skew exceeds the few-picosecond level implied by the jitter numbers, or drifts beyond the timing tolerance of the qubit controls over a 16-hour run, the central synchronization claim is refuted.","supporting_citations":[{"cited_title":"RFSoC ZCU216,","cited_arxiv_id":null,"evidence_quote":"ZCU216 RFSoC evaluation board: the hardware platform on which all three boards in the experiment run."},{"cited_title":"LMK04828,","cited_arxiv_id":null,"evidence_quote":"LMK04828 clock chip: provides the nested dual PLL in zero-delay mode and SYSREF generation that distribute the deterministic clock."},{"cited_title":"Multi-Tile Synchronization,","cited_arxiv_id":null,"evidence_quote":"Multi-Tile Synchronization: the Xilinx procedure that aligns DAC/ADC tiles on each board to a common SYSREF event."},{"cited_title":"Aurora 64B/66B,","cited_arxiv_id":null,"evidence_quote":"Aurora 64B/66B: the serial protocol over fiber that carries measurement data between boards at 10.3125 Gbps."},{"cited_title":"1588-2019 - IEEE Approved Draft Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems,","cited_arxiv_id":null,"evidence_quote":"IEEE 1588 Precision Time Protocol: the standard whose minimal implementation the paper uses for counter-offset correction between boards."},{"cited_title":"White rabbit: Sub-nanosecond timing dis- tribution over ethernet,","cited_arxiv_id":null,"evidence_quote":"White Rabbit: prior synchronization scheme achieving sub-nanosecond sync, used here as the baseline that the copper-link minimal PTP competes with."}],"review_version":1}