{"id":"192536c4-3608-4636-8d2a-10015b00b6f3","arxiv_id":"2506.13440","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"SEED applies sparse recurrent learning to convolutional recurrent units, cutting synaptic operations by 2 to 6 times while keeping mAP on event-based object detection.","lead":"This paper presents a detector for event cameras that cuts most of the computation by keeping over 92% of its recurrent processing inactive. It reports equal or better accuracy than prior methods with far fewer operations, and simulates the energy and latency savings on a neuromorphic chip.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"SENECA latency simulation in Section V.A uses average test-set activation density for all timesteps, but event-driven latency is governed by instantaneous event counts, so the low-latency claim rests on an unvalidated averaging assumption.","rationale":"The reader's weakest_assumption correctly identified the SENECA simulator and the GSOp counting methodology as unvalidated premises. My stress-test narrows the hardware concern to a specific, checkable modeling assumption: the use of average activation density to estimate latency. This is more concrete than a general call for independent hardware validation, because it identifies exactly why the reported latency numbers could be optimistic and how to test them. I do not see an internal inconsistency that would justify rejecting the paper; the simulation methodology is plausible, but the average-density simplification is load-bearing for the low-latency claim. The GSOp comparison issue is also real, but the SENECA latency issue is more central to the 'hardware-aware design translates to low-latency' part of the headline and is directly testable. Since the reader already reached CONDITIONAL, my concern reinforces that verdict rather than changing it.","tokens_in":11851,"tokens_out":7220,"duration_ms":84428,"concrete_test":"Re-run the SENECA micro-kernel simulation for SEED-256, SEED-128, and the RED variant in Table V using per-timestep measured activation maps or event traces from the 1Mpx test set, and report p50/p90/max latency for each layer and core instead of the test-set average density. If the max or tail latency of SEED-256 is not lower than RED's by at least the same factor reported in Table V, or if the event-based Conv-Rec unit's attributed latency reduction drops below 80%, then the low-latency claim is not supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section V.A states that 'we determine the average required computation of a layer by the average activation density of its inputs over the test data of the 1Mpx dataset,' and then takes the busiest core's latency as the network latency. This is the weakest load-bearing point for the hardware half of the headline claim. In an event-driven depth-first processor, per-step latency depends on the instantaneous number and spatial distribution of active events, not on a test-set average. Using the mean density smooths away temporal burstiness and can substantially understate tail latency, especially for sparsely activated recurrent layers like SEED's. The paper reports no per-timestep latency distribution, no error bars, and no sensitivity analysis around the density assumption. Because Table V's reported 2x latency reduction for SEED relative to RED, and the claim that the event-based Conv-Rec unit contributes over 80% of the energy and latency reduction, are both derived from this average-density figure, the 'low-latency neuromorphic processing' conclusion is not yet independently validated. The simulation is calibrated on the authors' own prior chip measurements, which is reasonable, but the averaging step remains an unverified modeling choice that directly feeds the headline efficiency comparison.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes SEED, a fully convolutional event-based object detector that integrates sparse convolutional recurrent (Conv-Rec) layers inspired by EGRU, together with an activation sparsity loss on residual blocks. The method is evaluated on the Prophesee 1Mpx and Gen1 event-based object detection datasets. The main reported results are: (i) SEED-256 achieves 44.9 mAP on 1Mpx and 45.3 on Gen1 with GSOp of 3.83 and 1.32, respectively, outperforming RED and roughly matching RVT-S with lower GSOp; (ii) sparsity-aware training reduces GSOp by 29-43% without mAP loss; (iii) a SENECA hardware simulation reports energy and latency reductions relative to ablations and a RED variant. The paper frames SEED as a new benchmark in computational efficiency for event-based detection with long-term temporal learning, positioned for deployment on neuromorphic processors.","tokens_in":12082,"tokens_out":6089,"duration_ms":54990,"significance":"If the results hold, the paper makes a useful contribution by showing that convolutional recurrent units can be made highly sparse (over 92% activation sparsity) while retaining the temporal reasoning needed for event-based detection, and by demonstrating that the resulting network can be mapped to a digital neuromorphic processor. The extension of EGRU-style event-based recurrent processing to ConvGRU and its generalization to other recurrent units (MGU, MinimalRNN, LSTM) is a valuable algorithmic step. The authors provide open-source code and compare against several baselines. However, the hardware efficiency claims are not fully validated because the SENECA simulation relies on average activation density and on the authors' own micro-kernel measurements, and several statistical and internal-consistency issues remain. With these addressed, the paper could be a solid addition to the event-based vision and neuromorphic computing literature.","major_comments":[{"comment":"The authors state that 'we determine the average required computation of a layer by the average activation density of its inputs over the test data of the 1Mpx dataset.' This averaging is used for both mapping and benchmarking, but event-driven processing latency on SENECA depends on the instantaneous number and spatial distribution of active events per timestep, not the test-set average. Using the mean density removes temporal burstiness and can substantially understate tail latency, especially for recurrent layers whose inputs depend on the previous hidden state. Because Table V's latency and energy results (including the '2x latency reduction' and 'over 80% contribution of the Conv-Rec unit') are all derived from this average-density assumption, the low-latency conclusions are not yet supported. Please provide per-timestep latency distributions (e.g., mean, median, 90th percentile), report the sensitivity of the results to the density estimate, and justify the averaging assumption with evidence that per-timestep variation is small.","section":"Section V.A"},{"comment":"The simulated 'RED (w/o SE)' is described as a data-flow-friendly version of RED with Squeeze-and-Excitation blocks replaced by sparse residual blocks, yet its reported GSOp (26.1) is identical to the original RED in Table I. If the network is modified, its GSOp must be recomputed; reporting an unchanged value is internally inconsistent and undermines the comparison with SEED. Additionally, the comparison showing RED reaching 40.7 ms latency with 1446 cores versus SEED-256's 44.9 ms with 254 cores should be discussed in terms of the area-latency trade-off; the statement that SEED is 'significantly cheaper' needs to weigh the latency/cores ratio carefully.","section":"Section V.B / Table V"},{"comment":"The claim that SEED delivers 'higher or same-level mAP' relative to RVT-S is only partly supported by the data: on Gen1, SEED-256 achieves 45.3 mAP versus RVT-S's 46.5, a 1.2-point deficit. Since all mAP and GSOp values come from single runs with no error bars or significance testing, it is impossible to determine whether this difference is meaningful or whether the reported efficiency gains are stable across seeds. Please report mean and standard deviation over at least 3 runs (or a paired analysis) for the main comparisons, or at least specify the number of runs and seed sensitivity.","section":"Section IV.B / Table I"},{"comment":"The SENECA simulator is calibrated on the authors' own prior hardware measurements [29] and the paper does not validate the simulated energy/latency numbers against actual SENECA measurements for the specific networks considered. Given that the efficiency conclusions rest entirely on this simulation, the paper should either provide a validation experiment (e.g., run a small network on SENECA and compare to simulation) or explicitly state the simulation's limitations and an error model. Without this, the 'energy-efficient and low-latency' hardware claim is not independently established.","section":"Section V.A"}],"minor_comments":[{"comment":"The row entries such as '-1.86(-33%) +0 -0.68(-34%) +0.9' are ambiguous because they mix GSOp changes and mAP changes without clear column separators; please split into separate columns per dataset with headers.","section":"Table IV"},{"comment":"The sparsity loss is defined over all layers l=1..L, but the text says it applies only to selected activation maps in the first convolutional layer and sparse residual blocks; please clarify the exact set of layers included.","section":"Section III.C, Eq. (5)"},{"comment":"The phrase 'less than 7% event density generated by recurrent layers' should define 'event density' precisely (e.g., fraction of recurrent hidden units above threshold averaged over timesteps).","section":"Section IV.C"},{"comment":"The group-wise mAP plot would benefit from error bars (or at least number of ground-truth boxes per group) to support the claim of improved detection at low event counts.","section":"Figure 2"},{"comment":"The statement that a 'thorough hyperparameter search' for beta_sparse was performed is not backed by details; please report the search range, criterion, and why 0.04 was selected.","section":"Section IV.A"},{"comment":"The discussion of event encoding methods [12] is brief; clarifying the distinction between per-frame encoding and temporal recurrent processing would help motivate the design.","section":"Section II.A"}],"recommendation":"major_revision","confidential_remarks":"The paper's hardware simulation relies heavily on the SENECA processor, which is the authors' own prior design; this is not a conflict per se, but the lack of independent validation and the single-run statistics should be weighed in the review. The GSOp comparison methodology for baselines also deserves scrutiny by a hardware-oriented reviewer."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: SEED is a solid engineering contribution. The genuinely new piece is the generalization of EGRU-style sparse recurrent learning to convolutional recurrent units in a fully convolutional event-camera detector, plus the demonstration that the design cuts GSOp while staying near RVT-S accuracy. Credit where due: evaluation on both 1Mpx and Gen1, the recurrent-unit ablation, the group-wise mAP analysis for low-instant-event objects, and public code. Table I is readable and the GSOp counts for RED and RVT come from open-source implementations, which is the right approach. The sparsity numbers are internally consistent: recurrent layers below 7% event density, sparsity-aware fine-tuning reduces GSOp by roughly a third without hurting mAP. This is not a conceptual reordering of the field, but it is a useful, reproducible step toward recurrent detection on low-power neuromorphic processors.\n\nSoft spots, in proportion. First, the abstract says \"higher or same-level mAP\" relative to state-of-the-art. Looking at Table I, SEED-256 beats RED and roughly matches RVT-S on 1Mpx (+0.8) but is 1.2 points below RVT-S on Gen1 and clearly below RVT-B on both datasets. The honest phrasing is \"comparable to the small transformer baseline, cheaper than all of them,\" not \"higher or same-level.\" Second, and more important, the hardware latency numbers in Table V assume average activation density over test data for every timestep. On an event-driven depth-first processor, per-step latency depends on instantaneous event counts and their spatial distribution, so averaging smooths temporal bursts and can understate tail latency. The paper reports no per-timestep latency distribution or sensitivity analysis. That does not undermine the energy estimates, which are driven by total operations, but the 2x latency reduction claim is not yet independently validated. Third, all numbers are single-run, no error bars; with margins this close, \"same-level\" can overstate precision. The self-calibration of the simulator is reasonable, not a flaw.\n\nWho this is for: edge event-camera detection and neuromorphic system designers who want a non-SNN alternative. It deserves a serious referee pass. My recommendation: conditional accept, with revisions to (a) fix the mAP characterization, (b) add sensitivity analysis around the average-density assumption or explicitly frame the latency numbers as average-case, and (c) report multiple seeds for the main comparisons. I would cite this paper.","headline":"SEED is a worthwhile, honest extension of sparse recurrent learning to convolutional event-camera detection, with solid mAP and GSOp comparisons, but the hardware latency headline depends on an average-density simulator assumption that should be stress-tested before reviewers sign off.","tokens_in":12628,"tokens_out":2881,"would_cite":true,"duration_ms":27314,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Sparse convolutional recurrent learning lets event-based object detectors cut synaptic operations by 2x to 6x against state-of-the-art while keeping or improving mean average precision.","keywords":["event-based vision","object detection","sparse recurrent learning","activation sparsity","neuromorphic computing","event camera","SENECA","convolutional recurrent unit"],"falsifier":"Run SEED-128 and RED on a real SENECA chip (or a cycle-accurate RTL model) with identical 1Mpx event streams and measure per-inference energy and end-to-end latency; if SEED does not show a several-fold advantage over RED and does not land near the simulated 39.3 mJ and 21.6 ms, the hardware-efficiency claim is contradicted. Independently, recompute RED and RVT GSOp with SEED's zero-skipping methodology from the public implementations; if the ratios 26.1-to-3.83 and 8.69-to-2.75 do not reproduce, the algorithmic efficiency claim collapses.","tokens_in":11655,"feed_emoji":"⚡","tokens_out":9391,"duration_ms":80745,"temperature":0.7,"pith_summary":"SEED is a fully convolutional event-camera object detector whose recurrent layers are made sparse enough for low-power neuromorphic hardware. The paper claims that by extending EGRU-style thresholded recurrent processing to convolutional gated units and adding an L1 activation-sparsity loss, recurrent processing runs at over 92% activation sparsity. On the 1Mpx and Gen1 automotive event datasets, SEED reports higher or equal mean average precision than the RED and RVT baselines while needing only a fraction of the synaptic operations (e.g., 3.83 GSOp versus 26.1 for RED on 1Mpx, with mAP 44.9 versus 43.0). Simulated on the SENECA neuromorphic processor, the hardware-aware design translates the sparsity into large energy and latency reductions. If correct, this makes accurate event-camera detection viable on resource-constrained edge devices.","feed_headline":"Sparse recurrent learning cuts event-detector compute 2–6x","feed_subtitle":"A fully convolutional detector keeps or beats prior mAP on automotive event data while staying neuromorphic-friendly.","key_machinery":"The load-bearing mechanism is sparse convolutional recurrent (Conv-Rec) processing, a generalization of the EGRU's event-based gating to convolutional gated recurrent units. The update equation $h(t)=\\alpha(t)\\odot h(t-1)+(1-\\alpha(t))\\odot z(t)-s(t-1)\\odot V_{\\mathrm{th}}$ applies a soft reset inspired by spiking neurons, and the Heaviside event generation $s(t)=H(h(t)-V_{\\mathrm{th}})$ with sparse hidden output $y(t)=h(t)\\odot s(t)$ ensures that all gating convolutions see only sparse activations. A per-neuron learnable threshold $V_{\\mathrm{th}}$, trained with surrogate gradients, lets the network choose its own sparsity level; an L1 activation-sparsity loss on the residual blocks extends sparsity to the feedforward part. On SENECA, event-based depth-first convolution skips zero activations, so this sparsity is what converts algorithmic savings into measured reductions in synaptic operations, energy, and latency.","core_discovery":"The central claim is that convolutional recurrent units—normally the computational bottleneck in event-based detection—can be made event-driven without sacrificing the long-term temporal memory the task needs. In SEED, the hidden state updates as $h(t)=\\alpha(t)\\odot h(t-1)+(1-\\alpha(t))\\odot z(t)-s(t-1)\\odot V_{\\mathrm{th}}$, binary events are generated by $s(t)=H(h(t)-V_{\\mathrm{th}})$, and the sparse hidden output $y(t)=h(t)\\odot s(t)$ is the only recurrent input to the convolutions; the learnable per-neuron threshold $V_{\\mathrm{th}}$ is trained with surrogate gradients. A sparsity loss on the residual-block activations pushes feedforward sparsity as well. On Prophesee's 1Mpx and Gen1 benchmarks, SEED-256 reaches 44.9 and 45.3 mAP with 3.83 and 1.32 GSOp, respectively, improving on RED (43.0/40.0 mAP at 26.1/8.26 GSOp) and matching RVT-S while cutting its GSOp by more than half. The paper also shows that the recurrent module, not the feedforward backbone, is the main source of hardware savings: removing it and the sparsity loss increases simulated energy and latency about fivefold on SENECA.","pith_inferences":["Beyond the paper's benchmarks, the group-wise mAP result suggests SEED's advantage will grow as event time bins shrink; testing at sub-millisecond bin widths would directly probe this.","Because the sparse recurrent update is unit-agnostic, the same thresholding recipe could be transferred to other spatio-temporal architectures such as video transformers, making them candidates for neuromorphic data-flow execution.","The SENECA simulation is instruction-level; an independent silicon measurement would be a stronger test of whether the reported 39.3 mJ and 21.6 ms for SEED-128 hold on real hardware, including any memory or communication overhead the micro-kernels omit.","If the GSOp counting methodology were applied to SEED's SSD head and event preprocessing rather than only the recurrent backbone, the remaining dense operations could become the next target for sparsification."],"forward_implications":["Event-camera object detection can be moved from compute-heavy ConvLSTM or transformer backbones to fully convolutional sparse recurrent networks without a mAP penalty.","A single algorithmic recipe—thresholded recurrent hidden states plus an activation-sparsity loss—works across GRU, MGU, MinimalRNN, and LSTM designs, with all recurrent layers staying under about 7% event density.","Recurrent processing remains necessary: removing it drops group-wise mAP most sharply for objects with little instant event information, so future efficiency work should sparsify temporal memory rather than remove it.","On SENECA, shrinking the recurrent channel dimension (SEED-128 versus SEED-256) gives a 2x latency reduction, larger than the raw GSOp reduction, because lower memory pressure lets the mapper parallelize high-latency layers across more cores.","Sparsity-aware finetuning reduces synaptic operations by 29-43% with no loss in mAP, indicating accuracy and efficiency do not have to be traded off at this operating point."],"supporting_citations":[{"why":"Supplies the 1Mpx dataset, the RED ConvLSTM baseline, and the training/evaluation protocol (focal loss, box filtering, mAP reporting) that SEED benchmarks against.","marker":"[2]"},{"why":"Supplies the Gen1 automotive event-detection dataset used for the second benchmark.","marker":"[3]"},{"why":"Provides the RVT transformer-based state-of-the-art detectors whose GSOp and mAP SEED compares against.","marker":"[5]"},{"why":"Defines the SENECA digital neuromorphic processor that the hardware simulation targets.","marker":"[7]"},{"why":"Provides the spiking DenseNet+SSD SNN baseline that SEED outperforms with about half the synaptic operations.","marker":"[8]"},{"why":"Introduces EGRU sparse recurrent learning, from which SEED takes the thresholded hidden state, learnable thresholds, and surrogate-gradient training.","marker":"[9]"},{"why":"Supplies the L1 activation-sparsity loss and the pretrain-then-finetune recipe used to sparsify SEED's residual blocks.","marker":"[13]"},{"why":"Provides the actual hardware instruction energy measurements used to calibrate the SENECA micro-kernel simulation.","marker":"[29]"},{"why":"Supplies the depth-first event-based convolution and mapping methodology that lets the simulator exploit activation sparsity.","marker":"[30]"}],"fun_headline_variants":["SEED: 92% activation sparsity in recurrent event detection","Sparse recurrent learning halves event-detector ops vs RVT","Neuromorphic event detector: 92% sparse recurrence, 2–6x less compute","SEED detector: same mAP as RVT, half the GSOp","Sparse event detection: recurrent learning without the compute tax"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The efficiency claims rest on two linked assumptions: that the zero-skipping GSOp model counts synaptic operations consistently across SEED, RED, RVT, and the SNN baselines, and that the SENECA micro-kernel simulator, calibrated on earlier chip measurements, predicts real silicon energy and latency; if either assumption fails, the 2x-6x savings and the energy/latency conclusions would be overstated.","fun_headline_variants_meta":{"raw":{"variants":["SEED: 92% activation sparsity in recurrent event detection","Sparse recurrent learning halves event-detector ops vs RVT","Neuromorphic event detector: 92% sparse recurrence, 2–6x less compute","SEED detector: same mAP as RVT, half the GSOp","Sparse event detection: recurrent learning without the compute tax"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000482,"raw_usage":{"total_tokens":2420,"prompt_tokens":1019,"completion_tokens":1401,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":635,"completion_tokens_details":{"reasoning_tokens":1304}},"tokens_in":635,"tokens_out":1401,"duration_ms":11501,"temperature":1.0,"reasoning_tokens":1304,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T20:01:23.325640+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run SEED-128 and RED on a real SENECA chip (or a cycle-accurate RTL model) with identical 1Mpx event streams and measure per-inference energy and end-to-end latency; if SEED does not show a several-fold advantage over RED and does not land near the simulated 39.3 mJ and 21.6 ms, the hardware-efficiency claim is contradicted. Independently, recompute RED and RVT GSOp with SEED's zero-skipping methodology from the public implementations; if the ratios 26.1-to-3.83 and 8.69-to-2.75 do not reproduce, the algorithmic efficiency claim collapses.","supporting_citations":[{"cited_title":"Learning to detect objects with a 1 megapixel event camera,","cited_arxiv_id":null,"evidence_quote":"Supplies the 1Mpx dataset, the RED ConvLSTM baseline, and the training/evaluation protocol (focal loss, box filtering, mAP reporting) that SEED benchmarks against."},{"cited_title":"Seneca: building a fully digital neuromorphic processor, design trade-offs and challenges,","cited_arxiv_id":null,"evidence_quote":"Defines the SENECA digital neuromorphic processor that the hardware simulation targets."},{"cited_title":"Object detection with spiking neural networks on automotive event data,","cited_arxiv_id":null,"evidence_quote":"Provides the spiking DenseNet+SSD SNN baseline that SEED outperforms with about half the synaptic operations."},{"cited_title":"Ef- ficient recurrent architectures through activity sparsity and sparse back- propagation through time,","cited_arxiv_id":null,"evidence_quote":"Introduces EGRU sparse recurrent learning, from which SEED takes the thresholded hidden state, learnable thresholds, and surrogate-gradient training."},{"cited_title":"Accelerating convolutional neural networks via activa- tion map compression,","cited_arxiv_id":null,"evidence_quote":"Supplies the L1 activation-sparsity loss and the pretrain-then-finetune recipe used to sparsify SEED's residual blocks."},{"cited_title":"Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design,","cited_arxiv_id":null,"evidence_quote":"Provides the actual hardware instruction energy measurements used to calibrate the SENECA micro-kernel simulation."},{"cited_title":"Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration,","cited_arxiv_id":null,"evidence_quote":"Supplies the depth-first event-based convolution and mapping methodology that lets the simulator exploit activation sparsity."}],"review_version":2}