{"id":"330b8b3d-d1c4-45a0-9aa1-06b401ba1593","arxiv_id":"2506.14676","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A memristor-SMTJ Ising machine reaches global optima on a 24-node MAX-CUT and a 10-node graph coloring by using the read voltage itself as the annealing temperature.","lead":"A hybrid Ising machine combines a memristor crossbar for spin couplings with a stochastic magnetic tunnel junction for spin states, and controls annealing simply by adjusting one read voltage. The prototype solves a 24-node weighted MAX-CUT and a 10-node three-color graph-coloring problem at room temperature and zero magnetic field.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The annealing mechanism rests on an unverified mapping from Vread to a calibrated Gibbs/Boltzmann temperature; the Methods passage admits schedules are tuned empirically and low-Vread nonlinearity, so the headline claim is conditional.","rationale":"The paper is a credible proof-of-concept: it combines two CMOS-integrated nanotechnologies, reports reproducible convergence to verified optima on two small instances, and provides a plausible physical mechanism (Eq. 13). I do not see an internal inconsistency that would invalidate the mechanism. The soft spot is evidential: the quantitative claim that Vread acts as an inverse temperature rests on Eq. 13, but the supporting device relations are empirical fits, and the Methods passage explicitly acknowledges nonlinearity at low Vread and empirically tuned schedules. Without a distribution-level check or a no-annealing baseline, the experimental results are consistent with the mechanism but do not uniquely confirm it. This is exactly the kind of concern that warrants conditional acceptance rather than rejection: the architecture is sound and the prototype works, but the headline 'intrinsic annealing' needs direct quantitative validation. The proposed test—fitting β_eff from repeated fixed-Vread runs—would settle whether Eq. 13 holds. If it passes, the claim is strong; if it fails, the paper should be reframed as a demonstration of a hybrid stochastic optimizer with a heuristic voltage ramp rather than a calibrated annealing technique.","tokens_in":16650,"tokens_out":15468,"duration_ms":161846,"concrete_test":"Fix the MAX-CUT hardware at several constant Vread values (no ramp), collect many repeated final states, and compare the empirical distribution to P({s}) ∝ exp(-β_eff H({s})) by fitting β_eff (e.g., maximum likelihood or KL minimization). The intrinsic-annealing mechanism predicts β_eff ∝ Vread (Eq. 13) with a constant of proportionality set by K Vref R_alpha. If the fitted β_eff does not scale linearly with Vread, or if the empirical distribution deviates significantly from Boltzmann at any Vread, then the voltage ramp is not a calibrated temperature schedule and the central claim's quantitative form is unsupported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The most load-bearing assumption is that Eq. (13) is a faithful hardware implementation of Gibbs sampling throughout the anneal. Eq. (13) composes three relations that are only idealizations: the linear MAC law (Eq. 4), a fixed conversion constant R_alpha (Eq. 6), and a constant-slope sigmoid with fixed K and V0.5 (Eq. 5). The Methods section 'Annealing schedule' concedes that at the low Vread values used in the high-temperature phase 'memristor conductance can be partly nonlinear' and that 'Annealing schedules are tuned empirically' from 'prior simulations.' No measurement is reported of the sampled configuration distribution against the Boltzmann law implied by Eqs. (2)-(3), and no baseline compares the reported voltage ramp to fixed-temperature or inverted-schedule runs. Since the two benchmarks are small and the schedules are per-task tuned, consistent convergence to the global optimum does not by itself establish that the voltage ramp is performing controlled simulated annealing; it could be a tuned stochastic search that succeeds on these specific instances.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports a hybrid Ising machine in which a hafnium-oxide memristor crossbar implements the coupling matrix and stochastic magnetic tunnel junctions (SMTJs) implement probabilistic spins. The central claim is that, because the same read voltage that drives the crossbar also biases the SMTJs, raising Vread decreases the SMTJ switching probability and thereby implements an intrinsic simulated-annealing schedule with essentially no extra circuitry. The authors derive Eq. (13) to show that the hardware update matches Gibbs sampling with inverse temperature β = Vread/Vref, and they report that the prototype solves a 24-vertex weighted MAX-CUT and a 10-vertex three-color graph-coloring problem, with global optimality checked by exhaustive enumeration. A 30-day retention study of the memristor conductances is also presented.","tokens_in":16901,"tokens_out":3690,"duration_ms":36792,"significance":"If the intrinsic annealing mechanism is correct, the work is significant: it would be the first demonstration of annealing without an external controller in a hybrid nanodevice Ising machine, and both constituent technologies are CMOS-back-end compatible, suggesting a scalable path to 3D-integrated optimizers. The paper deserves credit for checking the final configurations against an exhaustive solver, for testing each benchmark with three different SMTJs, and for explicitly discussing the limitations of the low-voltage regime. However, the central mechanistic claim is not directly validated by the experiments, as detailed below.","major_comments":[{"comment":"The claim that the Vread ramp implements controlled annealing rests on Eq. (13), which assumes the SMTJ sigmoid of Eq. (5) has constant K and V0.5, the MAC of Eq. (4) is perfectly linear, and the voltage conversion of Eq. (6) holds with a fixed Rα. The Methods passage explicitly states that at low Vread 'memristor conductance can be partly nonlinear' and that schedules are 'tuned empirically.' No measurement is reported of the actual switching probability of the SMTJ as a function of the combined MAC current during the optimization runs, nor of the sampled distribution against the Boltzmann law of Eq. (2). Consequently, the experiments do not establish that the voltage ramp is a calibrated temperature schedule; they only show that this particular stochastic search finds the optimum on two small instances.","section":"Methods, 'Annealing schedule', Eq. (13)"},{"comment":"The paper does not report any control experiments, such as fixed-voltage operation, an inverted schedule, or a schedule with random voltage jumps. Without such controls, the observed convergence cannot be attributed to the gradual lowering of effective temperature rather than to the final, near-deterministic regime or to the particular stochastic dynamics. Since the schedules are per-task tuned from prior simulations, the success of the two benchmarks is also consistent with a tuned stochastic search that is not performing simulated annealing in the intended sense.","section":"Solving a weighted MAX-CUT instance; Solving a graph coloring instance with bias terms"},{"comment":"Only three independent runs are reported per benchmark, each with a different SMTJ. With n=3 the statement that the prototype 'consistently reaches the global optimum' is statistically weak, especially given the documented die-to-die SMTJ variability in Fig. 2d,e; a few additional trials or a success-probability estimate with confidence bounds would be needed to support the robustness claim.","section":"Figs. 3b and 4b"},{"comment":"The one-month rerun of the graph-coloring experiment used a software-emulated SMTJ sigmoid, not the physical SMTJ, because the probe station was unavailable. The text discloses this, but the sentence 'the solver still converges to the optimal coloring' could mislead readers into thinking the full hybrid machine was re-validated after one month. This experiment only demonstrates memristor conductance retention, so the claim should be scoped accordingly.","section":"Fig. 4f and main text"}],"minor_comments":[{"comment":"The word 'charasteristic' is a typo and should be 'characteristic'; similarly 'represesents' in Fig. 2b should be 'represents'.","section":"Fig. 2 caption"},{"comment":"The word 'Muli-layer' should be 'Multi-layer' in the description of the SAF structure.","section":"Methods, 'Fabrication of the stochastic magnetic tunnel junctions'"},{"comment":"The phrase 'it would possible to use differential memristor structures' is missing 'be'; it should read 'it would be possible'.","section":"Mapping graph coloring to the Ising Hamiltonian"},{"comment":"The pseudo-temperature T is introduced via β = 1/T without units or a precise definition of its scale; since the hardware maps β to Vread/Vref, a brief statement connecting the dimensionless units of T to the voltage ratio would improve interpretability.","section":"Eq. (2) and annealing schedule"}],"recommendation":"major_revision","confidential_remarks":"This is a well-executed proof-of-concept demo, but the headline claim of 'intrinsic annealing' is broader than the evidence supports. The major comments request control experiments and a direct check of the Gibbs/Boltzmann mapping; if the authors can provide those, the work would be a strong contribution. I would not recommend rejection because the underlying derivation is algebraically sound conditional on the device idealizations, and the experimental demonstrations are internally consistent."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The real news here is the combination: memristor crossbar for couplings, SMTJ as the stochastic spin, and a single global voltage ramp that is supposed to act as annealing. That triple has not been shown before in nanodevices, and the paper is honest about what it does and does not demonstrate. The prototype solves a 24-vertex weighted MAX-CUT and a 10-node 3-coloring, repeatedly, with three different SMTJs, and the final configurations are confirmed globally optimal by exhaustive software search. Those are real, reproducible results at the scale shown. The 30-day retention test is a nice extra, even though the spin was emulated in software for that rerun.\n\nThe soft spots are real but proportionate. The central claim—that raising Vread lowers the effective temperature—rests on Eq. (13), which composes the ideal linear MAC law, a fixed conversion constant, and a constant-slope sigmoid. The paper itself concedes in the Methods that at the low Vread values used in the high-temperature phase the memristor conductance can be partly nonlinear, and that the annealing schedules were chosen from prior simulations and tuned empirically. No measurement shows that the sampled distribution actually tracks the intended Boltzmann law as Vread changes, and there is no baseline with fixed temperature or an inverted schedule. So the headline \"intrinsic annealing\" is not fully isolated; at this scale, a tuned stochastic search that happens to work on these two instances is still on the table. Three trials per task is also thin, and the benchmarks are small and very sparse (85% and 82% zero couplings). The two devices sit on separate dies, so the 3D-integration story is a roadmap, not a demonstration.\n\nNone of that kills the paper. The architecture is novel, the device-level characterization is careful, and the experimental work is clearly described. The right referee will ask for a distribution check and a control baseline, and the authors should be able to provide at least one of those without a huge effort. If those come back clean, this becomes a solid contribution to the Ising-hardware literature. If they do not, the paper still stands as a proof-of-concept for the hybrid, but the annealing claim needs to be toned down.\n\nRecommendation: send it to peer review. The work deserves careful referee time, and the requested controls are tractable. I would not desk-reject this; I would send it out with those specific questions.","headline":"A credible first hybrid memristor-SMTJ Ising machine with a genuinely new intrinsic-annealing idea, but the annealing claim needs a baseline and a distribution check before it is fully secured.","tokens_in":17482,"tokens_out":1424,"would_cite":true,"duration_ms":16997,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A single voltage ramp anneals a hybrid nanodevice Ising machine","keywords":["Ising machine","memristor crossbar","stochastic magnetic tunnel junction","intrinsic annealing","simulated annealing","MAX-CUT","graph coloring","probabilistic computing"],"falsifier":"Hold $V_{\\mathrm{read}}$ constant during runs on a small coupling matrix and record the histogram of visited spin configurations; if the energy distribution does not match the Boltzmann law with a single temperature proportional to $1/V_{\\mathrm{read}}$, or if the measured switching probability deviates from the sigmoid of Eq. (5) at read voltages below roughly 40 mV, then the voltage ramp is not a controlled annealing schedule. A simpler device-level check is to fix all spins and measure whether the crossbar's MAC current remains linear in $V_{\\mathrm{read}}$ down to the voltages used for exploration.","tokens_in":16480,"feed_emoji":"🧲","tokens_out":6950,"duration_ms":64534,"temperature":0.7,"pith_summary":"The paper reports a hardware Ising machine that unites two nanotechnologies in one optimization loop: a memristor crossbar stores the spin-spin couplings, and a stochastic magnetic tunnel junction (SMTJ) supplies the noisy spin updates. Its central proposal is that annealing needs no separate controller, because the very read voltage that drives the crossbar also biases the SMTJs; raising this voltage makes the spin statistics more deterministic, which is equivalent to lowering the machine's temperature. On this basis the paper claims its prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT instance and a 10-vertex, three-color graph-coloring problem at room temperature and zero magnetic field. The reader should care because the approach removes the supervisory annealing circuitry that other Ising machines require and places both device types in CMOS back-end-of-line layers, pointing toward vertical integration.","feed_headline":"Voltage ramp alone anneals a hybrid nanodevice Ising machine","feed_subtitle":"Raising one voltage cools stochastic spins, letting a memristor-SMTJ prototype land on global optima.","key_machinery":"The load-bearing mechanism is the voltage-controlled sigmoid of an SMTJ (a magnetic tunnel junction whose free-layer magnetization fluctuates randomly under thermal noise) combined with the analog multiply-and-accumulate current of a memristor crossbar. Feeding the crossbar current into the SMTJ through the conversion $V_{\\mathrm{MTJ}} = V_{0.5} + I_{\\mathrm{MAC}} R_\\alpha$ turns each spin update into a physical Gibbs sample, and setting $V_{\\mathrm{read}} \\propto \\beta$ turns the same circuit into an annealer. The paper also relies on a RESET-based program-and-verify memristor programming scheme, whose month-scale conductance stability is what lets a programmed problem remain solvable without reprogramming.","core_discovery":"On the paper's own terms, the discovery is a device-level identity: when the crossbar's multiply-and-accumulate current is converted to an SMTJ voltage, the resulting switching probability takes exactly the Gibbs-sampling sigmoid form $P_{\\mathrm{AP}} = \\frac{1}{1+\\exp(-\\beta K V_{\\mathrm{ref}} R_\\alpha (\\sum_j J_{ij} s_j + h_i))}$. Because the read voltage is set as $V_{\\mathrm{read}} = \\beta V_{\\mathrm{ref}}$, a single monotonic ramp of the read voltage implements simulated annealing: low $V_{\\mathrm{read}}$ keeps the junction near its 50% switching point for broad exploration, and high $V_{\\mathrm{read}}$ pushes the switching probability toward a deterministic decision. The authors support the claim experimentally with two optimization benchmarks, each solved to its global optimum in repeated trials using different SMTJs.","pith_inferences":["If the voltage ramp is a faithful temperature schedule, the same hardware should also be a Boltzmann sampler: fixing $V_{\\mathrm{read}}$ and histogramming sampled spin configurations should give energies distributed as $e^{-\\beta H}$, a distributional check the paper does not report.","The intrinsic mechanism suggests a natural replica-exchange protocol: toggling $V_{\\mathrm{read}}$ per replica could emulate parallel tempering without any thermal control, which the paper mentions only as a future direction.","The equivalence in Eq. (13) depends on linear MAC currents, so pushing the same device stack toward a sampler rather than an optimizer — holding $V_{\\mathrm{read}}$ fixed and collecting samples — would be a direct test of how far the Gibbs-sampling analogy extends.","Replacing the single prototype SMTJ with one p-bit per row, as in the paper's projected circuit, should let chromatic or asynchronous parallel Gibbs sampling exploit the same voltage-controlled anneal."],"forward_implications":["Annealing reduces to a single global voltage ramp, so the machine needs only two shared DACs rather than per-spin schedule logic.","The MAC current feeds directly into the SMTJ without an analog-to-digital converter, removing a major energy and latency cost from the critical path.","Because both memristors and SMTJs sit in the CMOS back end of line, the paper's integration roadmap — interposer, hybrid bonding, monolithic 3-D — could shrink interconnect lengths toward the nanosecond SMTJ switching time.","The demonstrated 130 ns SMTJ sampling, combined with parallel Gibbs-sampling extensions, implies that a fully integrated machine could approach nanosecond-scale parallel spin updates.","A programmed coupling matrix retains usable conductance values for at least a month, so a solved problem can be rerun without reprogramming the array."],"supporting_citations":[{"why":"Establishes the SMTJ as a stochastic p-bit, the spin element this architecture adopts.","marker":"[13]"},{"why":"Defines simulated annealing as a gradual reduction of stochasticity, the schedule the voltage ramp implements.","marker":"[29]"},{"why":"Shows a memristor-based Ising machine using intrinsic device noise, providing the coupling-storage approach and benchmark lineage this work extends.","marker":"[23]"},{"why":"Provides the only earlier hybrid nanotechnology Ising demonstrator, which lacks an annealing path and therefore motivates the intrinsic anneal.","marker":"[28]"},{"why":"Introduces massively parallel probabilistic computing with sparse Ising machines, the parallel-Gibbs direction this architecture is designed to support.","marker":"[15]"},{"why":"Supplies a CMOS-plus-nanomagnet comparison point for p-bit overhead and digital annealing control.","marker":"[17]"},{"why":"Demonstrates annealing in an analog memristor crossbar, an alternative schedule mechanism this work replaces with the voltage ramp.","marker":"[25]"}],"fun_headline_variants":["Voltage ramp anneals memristor-SMTJ Ising machine","Intrinsic annealing via voltage sweep in hybrid Ising solver","Ramping one voltage cools spins, annealing Ising machine","Zero-field Ising machine anneals by single-voltage ramp","Hybrid memristor-SMTJ Ising anneals with read-voltage sweep"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"Everything rests on the device sigmoid and the crossbar's MAC current combining to reproduce the Gibbs-sampling update at every stage of the anneal — in particular, the SMTJ switching probability must keep its fixed sigmoid shape and the memristor current must stay linear in $V_{\\mathrm{read}}$ even at the low read voltages used in the high-temperature phase.","fun_headline_variants_meta":{"raw":{"variants":["Voltage ramp anneals memristor-SMTJ Ising machine","Intrinsic annealing via voltage sweep in hybrid Ising solver","Ramping one voltage cools spins, annealing Ising machine","Zero-field Ising machine anneals by single-voltage ramp","Hybrid memristor-SMTJ Ising anneals with read-voltage sweep"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000561,"raw_usage":{"total_tokens":2685,"prompt_tokens":985,"completion_tokens":1700,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":601,"completion_tokens_details":{"reasoning_tokens":1611}},"tokens_in":601,"tokens_out":1700,"duration_ms":13256,"temperature":1.0,"reasoning_tokens":1611,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T19:49:13.892087+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Hold $V_{\\mathrm{read}}$ constant during runs on a small coupling matrix and record the histogram of visited spin configurations; if the energy distribution does not match the Boltzmann law with a single temperature proportional to $1/V_{\\mathrm{read}}$, or if the measured switching probability deviates from the sigmoid of Eq. (5) at read voltages below roughly 40 mV, then the voltage ramp is not a controlled annealing schedule. A simpler device-level check is to fix all spins and measure whether the crossbar's MAC current remains linear in $V_{\\mathrm{read}}$ down to the voltages used for exploration.","supporting_citations":[{"cited_title":"A., Pervaiz, A","cited_arxiv_id":null,"evidence_quote":"Establishes the SMTJ as a stochastic p-bit, the spin element this architecture adopts."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines simulated annealing as a gradual reduction of stochasticity, the schedule the voltage ramp implements."},{"cited_title":"J., Beausoleil, R., Lu, W","cited_arxiv_id":null,"evidence_quote":"Shows a memristor-based Ising machine using intrinsic device noise, providing the coupling-storage approach and benchmark lineage this work extends."},{"cited_title":"H., Khanna, A., Ye, H., Niazi, S., Chakraborty, B., Weinstock, E., Babu, N., Mukhopadhyay, S., Datta, S., Camsari, K","cited_arxiv_id":null,"evidence_quote":"Provides the only earlier hybrid nanotechnology Ising demonstrator, which lacks an annealing path and therefore motivates the intrinsic anneal."},{"cited_title":"A., Grimaldi, A., Carpentieri, M., Theogarajan, L., Martinis, J","cited_arxiv_id":null,"evidence_quote":"Introduces massively parallel probabilistic computing with sparse Ising machines, the parallel-Gibbs direction this architecture is designed to support."},{"cited_title":"S., Kobayashi, K., Cao, Q., Selcuk, K., Hu, T., Niazi, S., Aadit, N","cited_arxiv_id":null,"evidence_quote":"Supplies a CMOS-plus-nanomagnet comparison point for p-bit overhead and digital annealing control."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Demonstrates annealing in an analog memristor crossbar, an alternative schedule mechanism this work replaces with the voltage ramp."}],"review_version":2}