{"id":"5ff20b41-1503-4da6-9355-953228ff514a","arxiv_id":"2506.15437","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A RISC-V accelerator card runs a 2D FFT slower than a 24-core Xeon CPU but uses about 3.6 times less energy in the authors' measurements.","lead":"This paper ports the standard Cooley-Tukey FFT algorithm to the Tenstorrent Wormhole, a RISC-V based accelerator card, and measures its speed and power against a 24-core server CPU. For a 2D Fourier transform, the accelerator is slower but draws far less power, making it about 3.6 times more energy efficient in these tests.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 3.6x energy-efficiency claim rests entirely on an uncharacterized CPU FFT baseline; Section 3 does not identify the FFT library or thread-pinning details, and the abstract's 2.8x vs Table 3's 3.6x energy ratio is unreconciled.","rationale":"The reader's strongest claim is the energy-efficiency result, and the reader's weakest assumption correctly targets the CPU baseline. I agree: the central quantitative claim depends on a fair, tuned CPU comparator, and Section 3 provides none of the details needed to establish one. The discrepancy between 2.8x in the abstract and 3.6x in Table 3 and the conclusion reinforces that the headline energy ratio was not carefully cross-checked; whichever number is intended, the comparison must be reproduced with a known optimized FFT library before it can be relied on. I do not see a more serious internal flaw in the Wormhole implementation: the data-reordering bottleneck analysis is plausible, the optimizations (ThCon, 128-bit copies, single-copy reordering) are concrete, and the reported power draw of the n300, while surprising, is not obviously impossible. But the absence of any numerical accuracy check is a secondary concern: energy efficiency only matters if both platforms are computing the correct transform. Therefore the right disposition is CONDITIONAL, unchanged from the reader, with the concrete FFTW/MKL comparison as the condition.","tokens_in":9317,"tokens_out":5644,"duration_ms":65257,"concrete_test":"Re-run the CPU baseline of Table 3 on the same Xeon Platinum 8260M using FFTW (or Intel MKL) in single precision with 24 OpenMP threads and explicit CPU pinning; measure wall-clock time and RAPL energy over at least 10 runs, and also verify both CPU and n300 FFT outputs against a reference transform (e.g., numpy.fft) to confirm they compute the same result. If the tuned CPU runtime drops below about 3 ms or the CPU energy drops below about 1 J, the n300's 3.6x energy-efficiency advantage is not robust; report the new energy ratio. This single check directly settles whether the claimed advantage is an artifact of the baseline.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim in the abstract and Section 5 is that for a 1024x1024 FP32 2D FFT, the Wormhole n300 is 3.6 times more energy efficient than a 24-core Xeon Platinum CPU. The condition that must hold for this claim to be meaningful is that the CPU implementation is a fair, high-performance baseline. Section 3 states only that CPU runs are 'multi threaded using OpenMP' and compiled at -O3; it never says whether FFTW, Intel MKL, or an equivalent tuned library was used, nor whether threads were pinned, nor whether AVX-512 code paths were enabled. If the CPU code is the paper's own naive radix-2 kernel sketched in Listing 1.1, the 10.24 ms runtime and 3.62 J energy could both be substantially inflated, and the claimed 3.6x energy advantage could partly be an artifact of comparing against an unoptimized implementation. The internal inconsistency between the abstract's 'around 2.8 times less energy' and Table 3's 3.6x ratio makes it especially important to pin down which number is correct and how it was obtained. This is the least secure pillar of the argument; the n300 side, single-core optimizations, and power ratios are otherwise internally consistent.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a port of the Cooley-Tukey FFT to the Tenstorrent Wormhole n300, a RISC-V-based PCIe accelerator. On a single Tensix core, the authors explore optimizations (chunking, ThCon data copies, 128-bit accesses, and reducing data reorderings) and report a best single-core runtime of 5.31 ms for 16384 elements, versus 1.85 ms on one Xeon Platinum core. Scaling to a 1024x1024 2D FFT on 64 Tensix cores, they report a runtime of 23.56 ms with 42 W average power and 0.99 J energy, compared with 10.24 ms, 353 W, and 3.62 J on a 24-core Xeon Platinum CPU, yielding a claimed 3.6x energy-efficiency advantage. The central claim is that the Wormhole is considerably more energy-efficient despite being slower.","tokens_in":9534,"tokens_out":4757,"duration_ms":47228,"significance":"If the energy-efficiency result is credible, it is a noteworthy data point for RISC-V accelerators in HPC and the first published study of an FFT on the Tenstorrent architecture. The paper's breakdown of data-movement overheads (Table 2) and the optimization pathway (Table 1) are useful engineering contributions. The measurement methodology is transparent about the tools used (RAPL and TT-SMI) and runs are averaged over five executions. However, the reported comparison hinges entirely on the CPU baseline, which is not characterized as a high-performance implementation, and the abstract contradicts the table reported in Section 5. These issues must be resolved before the claimed advantage can be accepted.","major_comments":[{"comment":"The CPU baseline is not adequately characterized. The manuscript states only that 'Multi-core runs on the CPU are multi threaded using OpenMP' and that all codes are compiled with GCC at -O3. It never states whether the CPU FFT is a vendor-tuned library (e.g., FFTW, Intel MKL, or equivalent) or the authors' own radix-2 kernel sketched in Listing 1.1. If it is the latter, the 10.24 ms runtime and 3.62 J energy are not representative of a high-performance 24-core Xeon Platinum, and the claimed 3.6x energy advantage would be overstated. Please specify the exact CPU implementation, library name and version, thread pinning/affinity settings, and whether AVX-512 or other SIMD code paths were enabled. If a tuned library is not used, the comparison should be rerun against one.","section":"Section 3 and Table 3"},{"comment":"The abstract claims the Wormhole 'consumes around 2.8 times less energy than the CPU', but Table 3 reports 0.99 J for the n300 versus 3.62 J for the CPU, a factor of 3.66. The number 2.8 appears in Section 6 only as the single-core runtime ratio (5.31 ms / 1.85 ms). This is an internal inconsistency in the paper's primary quantitative claim, and the abstract must be corrected to match the measured 3.6x energy ratio (or the discrepancy explained).","section":"Abstract vs. Section 5, Table 3"},{"comment":"No numerical accuracy or correctness check is reported. The paper does not compare the FFT output against a reference implementation (e.g., FFTW or a known analytic transform) on either the CPU or the Wormhole. Without a maximum absolute or relative error measurement, it is not possible to rule out that the energy-efficient result corresponds to incorrect arithmetic, especially given that the matrix unit 'relaxes IEEE compliance' as noted in Section 2.1. Please include a validation step for at least the 1024x1024 2D FFT.","section":"Section 4 and Section 5"},{"comment":"Results are reported as averages over five runs, but no standard deviations, confidence intervals, or individual run values are given. Since the energy claim rests on a 3.6x difference and power measurements via RAPL and TT-SMI can be noisy, it is important to show that the difference is outside measurement variability. Please report the variance or, at minimum, the min and max values for the runs.","section":"Section 3 and Table 3"}],"minor_comments":[{"comment":"References [4] and [6] are dated September 2025 and August 2025, respectively, while the arXiv submission is dated 18 June 2025. These future dates suggest a citation error or a manuscript revision issue; please verify and correct them.","section":"References"},{"comment":"The loop condition 'step <= num_steps' in Listing 1.1 appears off by one; a standard radix-2 FFT on N points requires log2(N) steps, so the loop should terminate at 'step < num_steps'.","section":"Listing 1.1"},{"comment":"The paper reports Tenstorrent runs on a host with a 26-core Skylake Xeon Platinum 8170, while the CPU comparison uses a 24-core Cascade Lake Xeon Platinum 8260M. The reason for using a different CPU for the comparison is not explained; if the host CPU was available, it would be more natural to compare against it.","section":"Section 3"},{"comment":"The last two rows of Table 2 both report 0.9 ms, but the paper does not comment on why disabling the external write path (and write reordering) has no effect when read reordering is also disabled. A brief explanation would improve interpretability.","section":"Table 2"},{"comment":"The paper states that compute-only performance was comparable for the SFPU and FPU, but no supporting data or table is provided for this claim. Adding a short comparison would be useful.","section":"Section 4"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the scope of the venue, and the engineering content is reasonable. The central risk is the CPU baseline: if the authors can demonstrate that they used a tuned FFT library (or if they rerun against one), the energy-efficiency claim may survive. The abstract/table inconsistency is a minor but embarrassing error that must be fixed. The future-dated references also need correction."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The thing to know: this is the first published FFT port to a Tenstorrent Wormhole, and the headline result — slower than a Xeon Platinum but roughly 3.6x more energy-efficient for a 1024x1024 FP32 2D FFT — is plausible but rests on a CPU baseline we don't know enough about. The n300 side of the measurements looks careful; the CPU side is the soft spot.\n\nWhat the paper does well: the architectural exposition is clear, the optimization path is sensible, and the breakdown in Table 2 is genuinely informative. Moving from two data reorderings per step to one, using ThCon for scalar copies, and widening to 128-bit accesses are concrete, architecture-specific contributions. The power measurement on the Wormhole via TT-SMI and the CPU via RAPL is the right approach. The paper is also honest about its limitations: it states that the per-core problem size is capped at 16384 FP32 elements, that the 2D case uses only 64 of 120 cores, and that external DRAM staging is future work. That openness counts for something.\n\nThe soft spots are real, though not fatal. First, the CPU baseline is uncharacterized. Section 3 says only that CPU runs are OpenMP, compiled at -O3, and run on 24 cores. It does not say whether FFTW, MKL, or a hand-written radix-2 kernel was used, whether threads were pinned, or whether AVX-512 was enabled. The 10.24 ms runtime and 3.62 J energy could be inflated relative to a tuned library, and the claimed 3.6x energy advantage could shrink. This is the load-bearing concern, and the stress-test note got it right. Second, the abstract says \"around 2.8 times less energy\" while Table 3 and the conclusion say 3.6x. That inconsistency should not survive revision. Third, there are no error bars or numerical accuracy checks. Five runs averaged is fine, but FFT output should be validated against a known transform, especially when the matrix unit relaxes IEEE compliance. Finally, no code is shipped, which makes the optimization claims harder to reproduce.\n\nThese are addressable issues. The core direction — RISC-V accelerator uses less power but is slower — is credible, and the single-core experiments are internally consistent. I would send this to a serious referee, not desk reject it. The right outcome is major revision: characterize the CPU baseline, reconcile the energy numbers, report accuracy, and ideally release the code.\n\nFor you: worth a reading-group slot to talk about benchmarking methodology. I'd cite it if I were writing about RISC-V accelerators or FFT energy efficiency, but I'd caveat the CPU baseline.","headline":"First FFT port to a Tenstorrent Wormhole with a plausible but under-supported energy-efficiency claim; the n300 measurements look careful, the CPU baseline does not.","tokens_in":10083,"tokens_out":1910,"would_cite":true,"duration_ms":22984,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"RISC-V accelerator cuts FFT energy 3.6x vs Xeon CPU","keywords":["Fast Fourier Transform","Cooley-Tukey algorithm","RISC-V accelerator","Tenstorrent Wormhole","Tensix architecture","data movement optimization","energy efficiency","2D FFT"],"falsifier":"Run the same 1024-by-1024 2D FFT on the 24-core Xeon using a mature tuned FFT library (for example FFTW with SIMD and OpenMP) and record energy with RAPL; if the energy ratio between the CPU and the n300 drops below about 3.6 or reverses, the claimed efficiency advantage is an artifact of an untuned baseline.","tokens_in":9077,"feed_emoji":"⚡","tokens_out":5779,"duration_ms":52355,"temperature":0.7,"pith_summary":"The paper ports the Cooley-Tukey Fast Fourier Transform to the Tenstorrent Wormhole, a PCIe RISC-V accelerator built around Tensix cores, and measures how it compares with a server CPU. For a 1024-by-1024 2D FFT, 64 Tensix cores run slower than a 24-core Xeon Platinum CPU but draw about eight times less power, consuming roughly 3.6 times less energy overall. The key obstacle is data reordering between FFT steps, not the arithmetic, and the paper shows that chunked processing, scalar-unit copies, and 128-bit memory accesses each cut runtime. If the result holds, RISC-V accelerators offer a low-power route to HPC mathematics without replacing the host ecosystem.","feed_headline":"RISC-V accelerator cuts FFT energy 3.6x vs Xeon CPU","feed_subtitle":"A 64-core Tenstorrent Wormhole runs 2D FFTs slower than a CPU but at an eighth of the power.","key_machinery":"The central object is the Tensix core, a tile containing five RISC-V 'baby' cores (one for moving data in, one for moving data out, three driving a compute engine), 1.3 MB of local SRAM, and circular buffers (FIFOs) that hold data pages and synchronize producer-consumer behaviour between cores. The FFT kernel works with real and imaginary components separately and uses the SFPU vector unit; the paper reduces data movement by reordering once per FFT step instead of twice, and offloads copies to the ThCon scalar unit using 128-bit loads where accesses are contiguous. These pieces together determine whether the accelerator's decoupling of data movement from compute can compensate for its raw speed disadvantage.","core_discovery":"On its own terms, the paper's central claim is that the Wormhole n300 with 64 Tensix cores computes a 1024-by-1024 single-precision 2D FFT in 23.56 ms at 42 W, while a 24-core Xeon Platinum Cascade Lake CPU takes 10.24 ms at 353 W, so the accelerator is about 3.6 times more energy efficient (0.99 J versus 3.62 J). The paper also claims this is the first study of an FFT on a RISC-V PCIe accelerator, and that the main performance bottleneck on Tensix is data reordering rather than compute. A series of optimizations, including chunking the domain, using the ThCon scalar unit for copies, and widening memory accesses to 128 bits, reduces a single-core FFT runtime from 14.39 ms to 5.31 ms for 16384 elements.","pith_inferences":["The same data-reordering bottleneck likely affects other transforms and stencil calculations on Tensix, so the optimization techniques reported here may transfer beyond FFTs.","If the Wormhole's energy efficiency holds at larger problem sizes, the cost per useful transform in a data-center context could favour RISC-V accelerators, especially where power is capped.","An obvious extension is to benchmark against a production FFT library on both CPU and Wormhole to see whether the efficiency margin persists when the CPU baseline is tuned to its practical peak."],"forward_implications":["If the energy-efficiency result replicates, RISC-V accelerator cards become an attractive option for power-constrained HPC systems, especially for FFT-heavy workloads.","The optimization path identified for single-core FFTs — chunking, ThCon copies, 128-bit accesses, and one reorder per step — provides a template for other data-movement-heavy kernels on Tensix.","Using all 120 Tensix cores on the n300 and a transpose that handles uneven row distributions would likely close much of the 2.3x performance gap with the CPU.","For multi-dimensional FFTs, the all-to-all communication during transpose is the main scaling bottleneck; connecting multiple n300 cards with a high-performance network is the paper's stated next step to address it."],"supporting_citations":[{"why":"Previous work showing the first-generation Grayskull accelerator comparable to a server CPU at five times less energy for stencils; motivates the energy-efficiency hypothesis tested here.","marker":"[1]"},{"why":"Cawley's Wormhole series supplies the Tensix architectural details and the ThCon data-load hypothesis on which the optimizations rest.","marker":"[4]"},{"why":"Strang's textbook is the reference for the Cooley-Tukey FFT algorithm, described as the most important numerical algorithm of our lifetime.","marker":"[5]"},{"why":"Tenstorrent's Wormhole Tensix Processor datasheet is cited for the n300 configuration of 120 Tensix cores and 24 GB of GDDR6 across 24 banks.","marker":"[6]"}],"fun_headline_variants":["RISC-V Wormhole FFT: 3.6x energy savings over Xeon","Tenstorrent FFT: 1/8 the power, 3.6x energy efficiency","First FFT on RISC-V PCIe accelerator: 3.6x energy gain","Wormhole n300 FFT: slower but 3.6x more energy efficient","FFT on Tenstorrent Wormhole: 8x less power, 3.6x less energy"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The Xeon CPU baseline is a fair high-performance implementation: if the OpenMP CPU code is not using a tuned FFT library, then the measured 3.6x energy advantage of the Wormhole would be inflated.","fun_headline_variants_meta":{"raw":{"variants":["RISC-V Wormhole FFT: 3.6x energy savings over Xeon","Tenstorrent FFT: 1/8 the power, 3.6x energy efficiency","First FFT on RISC-V PCIe accelerator: 3.6x energy gain","Wormhole n300 FFT: slower but 3.6x more energy efficient","FFT on Tenstorrent Wormhole: 8x less power, 3.6x less energy"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000887,"raw_usage":{"total_tokens":3820,"prompt_tokens":929,"completion_tokens":2891,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":545,"completion_tokens_details":{"reasoning_tokens":2767}},"tokens_in":545,"tokens_out":2891,"duration_ms":21626,"temperature":1.0,"reasoning_tokens":2767,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T23:55:14.116875+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same 1024-by-1024 2D FFT on the 24-core Xeon using a mature tuned FFT library (for example FFTW with SIMD and OpenMP) and record energy with RAPL; if the energy ratio between the CPU and the n300 drops below about 3.6 or reverses, the claimed efficiency advantage is an artifact of an untuned baseline.","supporting_citations":[{"cited_title":"In: SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis","cited_arxiv_id":null,"evidence_quote":"Previous work showing the first-generation Grayskull accelerator comparable to a server CPU at five times less energy for stencils; motivates the energy-efficiency hypothesis tested here."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Cawley's Wormhole series supplies the Tensix architectural details and the ThCon data-load hypothesis on which the optimizations rest."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Strang's textbook is the reference for the Cooley-Tukey FFT algorithm, described as the most important numerical algorithm of our lifetime."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Tenstorrent's Wormhole Tensix Processor datasheet is cited for the n300 configuration of 120 Tensix cores and 24 GB of GDDR6 across 24 banks."}],"review_version":1}