{"id":"d489a00c-b8c7-4e40-a439-2c2d61093d2c","arxiv_id":"2506.15613","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A CXL-attached SSD using Determinism and Bufferability annotations is simulated to be 10.9x faster than PCIe memory expansion and to approach DRAM-like latency under high locality.","lead":"This paper proposes using CXL, a newer high-speed interconnect, to attach solid state drives directly to a computer's memory system so their capacity acts like working memory. It reports a custom FPGA prototype and simulations showing this CXL-attached SSD can be much faster than a PCIe-attached SSD, especially with extra performance hints from the CPU.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The headline speedups (10.9x, 5.4x, and the 'DRAM-like' claim) are projections from a gem5/SimpleSSD model calibrated only with Apex-Map on a 2-core FPGA RISC-V prototype, then scaled to a 4-core 4 GHz target without workload-level validation.","rationale":"The reader's weakest assumption identifies simulator fidelity as the load-bearing premise, and my reading agrees. The paper's own methodology makes the concern concrete: the only hardware measurements presented are Apex-Map latency results on a dual-core FPGA RISC-V node, while the evaluation uses a 4-core, 4 GHz simulated CPU with different cache sizes and no validation that the calibrated cycles generalize to the 18 evaluated workloads. Because the claimed 10.9x speedup is primarily a cache-benefit claim, changes in core count and cache capacity can materially change hit rates and therefore the headline result. This is not an internal inconsistency, but it is a correctness risk for the quantitative central claim. The prototype and the architectural argument are valuable, so I would not reject the paper; the conditional verdict remains appropriate. The concrete test I propose would settle whether the simulator calibration transfers by comparing simulated and measured behavior for real workloads on the actual prototype, and by quantifying the sensitivity to the configuration change.","tokens_in":14144,"tokens_out":6585,"duration_ms":80056,"concrete_test":"Run a subset of the RV8 workloads (e.g., AES, SHA512) on the FPGA CXL-SSD prototype using the prototype's actual dual-core RISC-V configuration, and reproduce the same workloads in the modified gem5/SimpleSSD simulator using those exact core/cache/clock parameters. If the simulated execution times differ from the FPGA measurements by more than about 20%, or if the CXL-SSD-versus-PCIe-SSD speedup changes by more than a factor of two when moving from the FPGA configuration to the Table 1a target configuration, the calibration does not transfer and the headline speedups are not supported. The modified simulator and configuration files should also be released so this check is independently reproducible.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claims rest entirely on the full-system simulation described in the Evaluation Setup, which states that gem5 and SimpleSSD were 'modified with the actual cycles we observed in the Preliminary Performance Model of CXL-SSD section.' That section reports only Apex-Map measurements on the FPGA prototype, whose host node is an in-house dual-core RISC-V CPU with 128 KB L1 and 4 MB L2. The simulated target in Table 1a is a 4-core, 4 GHz CPU with 64 KB L1 and 2 MB L2, connected through CXL 3.1 / PCIe 6.0. The claimed 10.9x improvement over PCIe and the 'DRAM-like' behavior are driven largely by cache hit rates, which depend on exactly the parameters that change between the calibration platform and the simulated target: core count, cache capacity, and memory-level parallelism. The paper provides no calibration error, no comparison of simulated versus measured execution time for any real workload, and no released simulator configuration. The FPGA prototype is a real artifact, but it validates only that a dual-core RISC-V system can issue CXL.mem traffic to a storage endpoint; it does not validate the simulated 4-core/4 GHz speedups or the annotation gains on SPEC/RV8 workloads. Until the calibration transfer is demonstrated, the abstract's headline numbers should be treated as projections with unknown error, not as measured results.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper proposes using CXL Type 3 endpoints to transform PCIe-based block storage into byte-addressable, cacheable working memory (CXL-SSDs). The authors prototype a CXL-SSD on a custom FPGA platform and propose two instruction annotations, Determinism (DT) and Bufferability (BF), meant to improve latency and persistence behavior when CXL memory requests interact with SSD internals. The evaluation combines FPGA-prototype measurements (Apex-Map latency) with a gem5+SimpleSSD full-system simulator, reporting that CXL-SSD outperforms a PCIe-based memory expander by 10.9x and that the annotation-augmented CXL-ASSD improves performance over CXL-SSD by an additional 5.4x, with DRAM-like performance claimed for high-locality workloads.","tokens_in":14515,"tokens_out":6370,"duration_ms":72707,"significance":"If the quantitative claims are reliable, the paper makes a strong case for a practical storage-memory convergence path that reuses standard CXL infrastructure. The FPGA prototype is a concrete hardware artifact, and the proposed DT/BF annotations are a novel idea for letting host-aided hints control SSD-internal scheduling and persistence in a memory semantics. The paper also ships a useful system-integration and disaggregation discussion. However, all headline numbers come from a simulator calibrated only against narrow Apex-Map measurements on a dual-core RISC-V prototype and projected to a 4-core 4GHz target; no code, configuration files, or workload-level hardware validation are provided. The quantitative evidence therefore does not yet meet the standard needed to support the abstract's strongest claims.","major_comments":[{"comment":"The full-system simulation is calibrated only against Apex-Map latency measurements from the FPGA prototype (Fig. 4b), whose host is a dual-core RISC-V CPU with 128KB L1 and 4MB L2. The simulated target in Table 1a is a 4-core 4GHz CPU with 64KB L1 and 2MB L2, connected through CXL 3.1/PCIe 6.0. Because the reported speedups (10.9x vs. PCIe, 5.4x from annotations, and DRAM-like performance for high-locality workloads) are driven largely by cache hit rates, and because cache hit rates depend on core count, cache capacity, and memory-level parallelism, the transfer of calibration from the prototype to the simulated target is not self-evident. The paper provides no calibration error, no comparison of simulated versus measured execution time for any real workload, and no sensitivity analysis with respect to core count or cache capacity. The headline numbers are therefore projections of unknown accuracy.","section":"Evaluation Setup and Preliminary Performance Model of CXL-SSD"},{"comment":"The claimed 5.4x improvement of CXL-ASSD over CXL-SSD in Fig. 6b is not tied to a stated annotation coverage. The sensitivity test in Fig. 6d shows that execution time varies substantially with the fraction of annotated functions/instructions (e.g., annotating 25% of functions yields a 50.1% average reduction, but per-workload results vary widely). The DT policy is described qualitatively as applying when the proportion of load instructions in the instruction queue and reorder buffer 'exceeds a certain threshold,' and the STREAM evaluation in Fig. 6f uses a p75 setting. Without a precise specification of how the annotation coverage and the DT threshold are chosen, the 5.4x result is not reproducible and may depend on favorable tuning.","section":"Instruction Annotation and Performance Analysis"},{"comment":"The proposed Determinism and Bufferability annotations are carried in the 10-bit reserved fields of CXL.mem M2S Req and S2M NDR messages. The paper asserts that these fields 'can support' the annotations without additional transmission costs or data-payload modification, but it does not cite the relevant CXL 3.1 specification clauses or demonstrate compliance. If the CXL specification requires reserved bits to be transmitted as zero and to be ignored by the receiver, or if existing hosts/endpoints treat non-zero reserved bits as errors, the entire annotation mechanism cannot be deployed on standard CXL hardware. This assumption is load-bearing for the main contribution.","section":"Instruction Annotation, first paragraph"}],"minor_comments":[{"comment":"The workload description does not specify the benchmark versions (e.g., SPEC CPU 2006 vs. SPEC CPU 2017) or the exact set of RV8 benchmarks used; providing this information would improve reproducibility.","section":"Table 1b and Evaluation Setup"},{"comment":"The abstract's claim that CXL-SSD 'approaches DRAM-like performance' is not quantified; the STREAM results in Fig. 6f show CXL-ASSD is still 4.7x slower than CXL-DRAM, so the abstract would be more precise if it qualified the claim as applying only to latency-sensitive, high-locality workloads.","section":"Performance Analysis"},{"comment":"The statement that Intel and AMD ISAs enforce non-cacheability of PCIe-related memory requests is presented without a citation; a reference to an architectural manual would be helpful.","section":"Why CXL Memory for PCIe Storage?"},{"comment":"The sentence 'it does need careful network and storage designs' is grammatically awkward and should be rewritten for clarity.","section":"Disaggregation Discussion"}],"recommendation":"major_revision","confidential_remarks":"The principal risk is the calibration transfer from the FPGA prototype to the simulated 4-core/4GHz target. If the authors can add a limited validation (e.g., comparing simulator against measured execution time for a small set of workloads on the prototype, or releasing the simulator configuration and calibrations), the central claims would be much better supported. The reserved-field assumption in CXL.mem should also be verified against the CXL 3.1 specification before publication, since it underpins the annotation contribution."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Worth a read. The real contribution is the FPGA prototype that runs a PCIe SSD as a cacheable Type 3 CXL device, plus the Determinism and Bufferability annotations that tell the SSD when to suppress internal tasks or buffer writes. The cacheability rationale is not new to the CXL-storage community, but the annotation mechanism is a solid engineering idea, and the sensitivity analysis (25% annotation coverage still gives half the benefit) is a good addition.\n\nThe weak spot is the evaluation chain behind the headline numbers. The 10.9x and 5.4x figures come from a gem5/SimpleSSD model calibrated with Apex-Map on a dual-core RISC-V FPGA, then scaled to a 4-core 4 GHz target with different cache sizes and no workload-level validation. There are no error bars, no released simulator configuration, and the calibration transfer is not demonstrated. The 'DRAM-like' claim in the abstract is also stronger than the data: in the full workload results, the annotated CXL-SSD is still 4.7x slower than CXL-DRAM. The paper is transparent about some of this in the evaluation section, but the abstract overstates.\n\nThe annotation scheme itself presumes CPU and CXL RP modifications (threshold-based DT detection, new store instruction variants) that don't exist in current commercial hardware. That is acceptable for a proposal but makes the 'approaches DRAM-like' claim even more conditional.\n\nThe citation pattern is fine; the reliance on the authors' own simulator is reasonable given the area, but the missing release is a problem for reproducibility.\n\nOverall: the central direction is plausible, the prototype is real, and the simulation concerns are addressable. I would send this to peer review with a request for major revision: release the simulator configuration, add calibration error bars, and validate at least one full workload against the FPGA. Then the numbers can be trusted.\n\nReading group: maybe. It would spark a good discussion about simulator fidelity and what counts as a measured result.","headline":"A credible FPGA prototype and a genuinely useful annotation idea, but the headline speedups are simulator projections that need calibration evidence before they are quoted.","tokens_in":15009,"tokens_out":3039,"would_cite":true,"duration_ms":30675,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"CXL can turn PCIe block storage into cacheable working memory, with Type 3 CXL-SSDs outperforming PCIe memory expanders by 10.9x.","keywords":["CXL","CXL-SSD","PCIe SSD","memory expansion","cacheability","instruction annotation","full-system simulation","memory-storage convergence"],"falsifier":"Run the same workload mix on a real CXL Type 3 SSD built from commodity flash (or a fully released simulation configuration) and measure execution time versus a PCIe memory expander using the same media; the paper's claims are settled by whether the 10.9x improvement and the additional 5.4x gain from annotations reproduce outside the calibrated model.","tokens_in":13964,"feed_emoji":"💾","tokens_out":6862,"duration_ms":64514,"temperature":0.7,"pith_summary":"This paper aims to show that Compute Express Link (CXL) can convert ordinary PCIe-based block storage into a scalable, byte-addressable working memory. The key move is cacheability: where PCIe base address registers force non-cacheable accesses that bypass the CPU caches, CXL.mem places the storage's memory in a cacheable system address space. The authors advocate a Type 3 endpoint design, the CXL-SSD, and add two instruction annotations, Determinism and Bufferability, to control how the SSD schedules internal tasks and buffers writes. Based on an FPGA prototype and a full-system simulation calibrated to it, they report that a CXL-SSD outperforms a PCIe memory expander by 10.9x, that the annotations cut latency by another 5.4x, and that high-locality workloads approach DRAM-like performance. The broader claim is that block storage can join CXL's memory ecosystem with only modest changes to existing SSD hardware.","feed_headline":"CXL turns PCIe block storage into working memory","feed_subtitle":"Type 3 CXL-SSDs beat PCIe memory expanders 10.9x and approach DRAM on cacheable workloads.","key_machinery":"The load-bearing mechanism is the cacheable system mapping provided by CXL.mem for a Type 3 endpoint: once a device's HDM is mapped into the host's physical address space, loads and stores are coherent with CPU caches, so repeated accesses never reach the storage. The annotations, Determinism (DT/ND) and Bufferability (BF/NB), are placed in the reserved fields of CXL.mem request and response messages, letting the SSD controller decide whether to defer internal tasks and whether to cache data in its internal DRAM. The evaluation machinery is a full-system simulation built by coupling a CPU simulator with an SSD simulator and adjusting both with cycle counts observed on a custom FPGA prototype; the projected configuration is a 4 GHz, four-core CPU with a CXL 3.1 endpoint.","core_discovery":"The central claim is that cacheability, not raw bandwidth, is what lets block storage act as working memory, so the right CXL device type is a Type 3 endpoint. Under this design, the host maps the device's host-managed device memory (HDM) into system memory and issues ordinary load/store instructions; CPU cache hits then bypass the storage device entirely, eliminating the per-access latency of flash. The two annotations, Determinism and Bufferability, ride in reserved fields of CXL.mem request messages and tell the SSD controller whether to suppress background tasks and whether to buffer data in its internal DRAM or force it to flash. In the calibrated simulation, this combination reduces storage access frequency by 72.1% on average, improves execution time by 10.9x over a non-cacheable PCIe memory expander, and the annotations contribute an additional 5.4x, with bandwidth microbenchmarks showing up to 14.6x gains at low thread counts.","pith_inferences":["If the reserved annotation fields are adopted by the CXL specification, compilers and profilers could tag loads and stores automatically, removing the need for hand-annotating library code.","The paper does not address OS page placement: using CXL-SSD as working memory would require memory-tiering policies that decide which pages live on flash-backed CXL memory, so real-world gains depend on the OS policy as much as the hardware.","The DRAM-like results for high-locality workloads suggest CXL-SSD is best deployed as a large, slow tier below a small DRAM tier, rather than as an outright DRAM replacement.","A cheap way to test the sensitivity of the results is to vary the SSD's internal DRAM size and the flash program/read latencies in the calibrated simulator, since the annotation gains depend heavily on internal DRAM absorbing flash latency."],"forward_implications":["CXL-SSDs could supply NAND-class capacity as a lower-cost memory tier, with CPU caches absorbing most accesses in locality-heavy workloads.","The DT/ND and BF/NB annotations give software a way to enforce persistence without issuing a global flush, reducing the cost of transaction commit in databases.","Because the SSD-side changes are described as small (extending the PCIe endpoint logic and simplifying the NVMe controller), most current PCIe SSDs could be reworked into Type 3 CXL endpoints.","With CXL switches and logical device partitioning, CXL-SSDs can be disaggregated and shared across multiple hosts, allowing fine-grained memory pooling.","For latency-sensitive access patterns the annotations give the larger gains (up to 14.6x at one thread), while bandwidth-bound multi-threaded access still improves 4.2x, indicating the internal DRAM of the SSD is the key resource."],"supporting_citations":[{"why":"Defines the CXL.mem message layout with the reserved fields used to carry the annotations.","marker":"[4]"},{"why":"Supplies the global memory access benchmark used for the prototype latency study.","marker":"[6]"},{"why":"Supplies the CPU simulation model in the full-system evaluation.","marker":"[7]"},{"why":"Supplies the SSD simulation model for the full-system evaluation.","marker":"[8]"},{"why":"Provides the CPU workloads used in the evaluation.","marker":"[9]"},{"why":"Provides additional RISC-V benchmark workloads.","marker":"[10]"},{"why":"Provides the bandwidth microbenchmark used for thread-scaling analysis.","marker":"[11]"}],"fun_headline_variants":["CXL turns PCIe SSDs into byte-addressable working memory","Cacheability is key: CXL-SSDs outperform PCIe expanders 10.9x","Type 3 CXL-SSDs approach DRAM speed via cache-conscious annotations","CXL-SSD annotations cut latency 5.4x while keeping data persistent","Byte-addressable SSDs via CXL: 10.9x faster than PCIe expanders"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The performance results depend entirely on the fidelity of the calibrated full-system simulation; if the cycle counts observed on the FPGA prototype do not transfer to a real 4 GHz CXL 3.1 endpoint, the 10.9x, 5.4x, and DRAM-like claims are not supported.","fun_headline_variants_meta":{"raw":{"variants":["CXL turns PCIe SSDs into byte-addressable working memory","Cacheability is key: CXL-SSDs outperform PCIe expanders 10.9x","Type 3 CXL-SSDs approach DRAM speed via cache-conscious annotations","CXL-SSD annotations cut latency 5.4x while keeping data persistent","Byte-addressable SSDs via CXL: 10.9x faster than PCIe expanders"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000283,"raw_usage":{"total_tokens":1658,"prompt_tokens":916,"completion_tokens":742,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":532,"completion_tokens_details":{"reasoning_tokens":629}},"tokens_in":532,"tokens_out":742,"duration_ms":7065,"temperature":1.0,"reasoning_tokens":629,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T23:53:24.368009+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same workload mix on a real CXL Type 3 SSD built from commodity flash (or a fully released simulation configuration) and measure execution time versus a PCIe memory expander using the same media; the paper's claims are settled by whether the 10.9x improvement and the additional 5.4x gain from annotations reproduce outside the calibrated model.","supporting_citations":[{"cited_title":"Zhong, D","cited_arxiv_id":null,"evidence_quote":"Defines the CXL.mem message layout with the reserved fields used to carry the annotations."},{"cited_title":"UDON: A case for offloading to general purpose compute on CXL memory","cited_arxiv_id":"2404.02868","evidence_quote":"Supplies the global memory access benchmark used for the prototype latency study."},{"cited_title":"Strohmaier and H","cited_arxiv_id":null,"evidence_quote":"Supplies the CPU simulation model in the full-system evaluation."},{"cited_title":"Binkert, B","cited_arxiv_id":null,"evidence_quote":"Supplies the SSD simulation model for the full-system evaluation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the CPU workloads used in the evaluation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides additional RISC-V benchmark workloads."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the bandwidth microbenchmark used for thread-scaling analysis."}],"review_version":1}