{"id":"9915c18a-845d-4a96-bc5c-919022b9b5ee","arxiv_id":"2506.19067","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"MEDEA uses integer linear programming to pick per-kernel processor, voltage/frequency, and tiling decisions that minimize estimated energy under a deadline for DNN inference on heterogeneous ultra-low-power platforms, reporting up to 38% savings for a seizure-detection transformer.","lead":"MEDEA is a design-time tool that chooses which processor, voltage, frequency, and tiling mode to use for each kernel of a DNN on a heterogeneous ultra-low-power chip, minimizing energy while meeting a deadline. In a seizure-detection transformer case study on a RISC-V platform with two accelerators, it estimated up to 38% energy savings over baseline schedulers.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Efficiency crossovers may invalidate MEDEA's monotonicity assumption, yet a counterexample check and error-bound test can settle it.","rationale":"The reader correctly identifies the model-validation risk from FPGA/EDA estimation as the weakest assumption, but the more load-bearing issue is internal to the algorithm's justification: the paper's proof that minimizing active energy under the deadline is equivalent to minimizing total energy. This equivalence is asserted in Section 3.3 and is not derived; Figure 7 already demonstrates efficiency crossovers, which directly violate the monotonicity the proof requires. If the equivalence fails, the returned MCKP solution is not necessarily the energy-optimal schedule, undermining the strongest claim of 'consistently optimizes energy.' The concern can be settled analytically by a small counterexample or empirically by changing the objective to the true total energy. The FPGA/EDA limitation also matters and remains an independent concern, but the monotonicity issue is more fundamental to the central claim. I agree only partially with the reader's weakest_assumption because while the hardware-representativeness concern is valid, the internal-consistency issue is more severe and was not flagged in the reader's verdict. I would keep CONDITIONAL because the paper could be revised with a corrected proof, a re-optimization, or an explicit acknowledgment of the limitation; the presented evidence does not currently demonstrate the claimed optimality.","tokens_in":18493,"tokens_out":1909,"duration_ms":17301,"concrete_test":"Construct a small counterexample within the paper's own framework using two kernels and two PEs whose energy-time efficiency crossover is as shown in Figure 7. Let kernel A be fastest on CGRA at 0.9 V and kernel B be fastest on Carus at 0.9 V, while at 0.5 V Carus is more efficient for both. Apply the paper's ILP formulation (min active energy subject to deadline) and compare against an exhaustive search over all valid schedules, including those that finish before the deadline and idle. If any pre-deadline schedule has strictly lower total energy than the ILP optimum, the asserted equivalence in Section 3.3 is false. A second check: rerun the reported experiment with the true objective in Eq. 7 (adding idle energy proportional to slack) and compare energy numbers in Figure 5 and Table 5; if any reported energy value changes by more than 5%, the headline savings need revision.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claim is that MEDEA's optimization is exactly equivalent to minimizing active energy under a deadline, so its ILP solutions are globally energy-optimal on real hardware. The argument in Section 3.3 asserts that any schedule completing before the deadline can be slowed to the deadline without increasing total energy, because slower execution uses lower V-F and thus lower active energy, while idle energy only decreases. This monotonicity is load-bearing: it justifies replacing the true total-energy objective (Eq. 7) with the active-energy-only objective (Eq. 10), and it underlies the reported comparisons and the 'consistently meeting deadlines' conclusion. The paper itself provides evidence against the required monotonicity: Section 5.2 and Figure 7 show that the relative energy efficiency of CGRA versus Carus crosses over as a function of V-F. With such efficiency crossovers, a schedule that 'executes faster' by shifting a kernel from a low-voltage-efficient PE to a high-voltage-efficient PE can have lower active energy than a slower schedule, so finishing exactly at the deadline is not generally the energy-optimal strategy. The asserted equivalence is not proven; the optimization may return a feasible but non-optimal schedule, and reported savings versus baselines could be either overstated or understated. Additionally, the claim that 'any alternative schedule that executes faster would necessarily require higher V-F settings for some kernels, resulting in a higher active energy consumption' is only true if each kernel's active energy is strictly decreasing with execution time, which kernel-to-PE reassignment can violate. Because this unproven equivalence is the core of the optimality claim, it is a genuine correctness risk rather than a mere presentation issue.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces MEDEA, a design-time manager for energy-efficient DNN inference on heterogeneous ultra-low-power platforms. MEDEA selects, for each kernel of a sequential DNN workload, a processing element, a voltage/frequency operating point, and a tiling mode, subject to an application-level deadline, and solves the resulting multiple-choice knapsack problem with an ILP. The authors evaluate MEDEA on HEEPTimize, a 22 nm FPGA-prototyped platform with a RISC-V core, an NMC accelerator, and a CGRA, using a transformer-based seizure-detection model. They report energy reductions of up to 38% relative to adapted state-of-the-art baselines while claiming consistent deadline satisfaction, with a feature analysis attributing savings to kernel-level DVFS, kernel-level scheduling, and adaptive tiling.","tokens_in":18582,"tokens_out":8344,"duration_ms":90288,"significance":"If the results hold, the paper makes a useful practical contribution by showing how four previously separate mechanisms—kernel-level DVFS, kernel-level PE scheduling, memory-aware tiling, and deadline-constrained energy optimization—can be integrated into a single design-time flow for heterogeneous ULP platforms. The evaluation on a custom FPGA-prototyped, ASIC-characterized platform, together with the feature-ablation study, is a strength. However, the central claim that the proposed objective exactly minimizes total energy under a deadline is not established, and the deadline-compliance claim rests on a timing model rather than on end-to-end measurement. Because these issues affect the meaning of the reported 38% savings and the 'consistently meeting deadlines' statement, the paper needs revision before its central claims can be accepted.","major_comments":[{"comment":"The reduction of the total-energy objective to active-energy-only minimization is not valid in general and is contradicted by the paper's own observations. The argument in Section 3.3 assumes that any schedule that finishes earlier must use higher V-F settings and therefore has higher active energy. However, Section 5.2 and Figure 7 show that the relative energy efficiency of CGRA versus Carus crosses over across the V-F range, so a faster schedule can reassign kernels to the PE that is more efficient at the higher operating point and thereby achieve both shorter time and lower active energy. In addition, the true objective in Eq. (7) contains the term -P_slp * T_a for schedules finishing before the deadline; with P_slp = 129 uW and the 1000 ms case of Table 5 (T_a = 223 ms, sleep energy = 100 uJ), a slower schedule with slightly higher active energy but longer active time can have lower total energy. The ILP therefore minimizes E_a, not E_t, and the statement that MEDEA 'minimizes energy' under the deadline is not supported. The objective should be changed to E_a - P_slp * T_a (up to a constant) or to the exact E_t, or the paper should be reframed as a heuristic that minimizes active energy only.","section":"Section 3.3"},{"comment":"Pre-selecting the tiling mode that yields the minimum execution cycles for each (PE, V-F) pair discards configurations from Omega_i before the energy optimization. A single-buffer mode can have more cycles than double-buffering but lower energy because it uses fewer and larger data transfers, and it may be the energy-optimal choice when the deadline is slack. Since the pre-selection criterion is execution cycles rather than energy, the resulting configuration set may exclude the global energy optimum. The paper should either optimize over both tiling modes within the ILP or explicitly justify why cycle-minimal tiling is always energy-optimal for the considered platform.","section":"Section 3.3"},{"comment":"Deadline compliance is asserted from the timing model G_T, which combines FPGA-measured cycle counts for representative kernels with estimated data-movement cycles, but the paper does not report an end-to-end run of any MEDEA-generated schedule on the FPGA or a comparison between G_T estimates and measured total execution time for the full workload. Given the central claim that MEDEA 'consistently meets all timing requirements,' the paper should provide measured end-to-end validation on the prototype, or at least a quantified bound on G_T error. Without such validation, the deadline-compliance claim is not empirically established.","section":"Section 4.1.2"}],"minor_comments":[{"comment":"The 'w/o KerDVFS' configuration applies a single AppDVFS setting described as the lowest V-F point that allows the schedule to meet the deadline; it is not clear whether this setting is computed by re-solving the scheduling problem or by post-scaling the MEDEA schedule, which could bias the feature-impact comparison.","section":"Section 5.3"},{"comment":"Table 5 introduces P_slp = 129 uW as the platform sleep power, but the extraction of this value from the ASIC characterization flow is not described in Section 4.1.2; please clarify how this number was obtained.","section":"Section 4.1.2"},{"comment":"The assumption that power for a given kernel type on a PE and voltage is independent of kernel operational size is stated without validation; for memory-intensive kernels, dynamic power per cycle can vary with data activity. A brief justification or sensitivity check would strengthen the model.","section":"Section 3.1.3"},{"comment":"The platform name is written both as 'HEEPtimize' and 'HEEPTimize' in different places; please standardize the spelling.","section":"Throughout"},{"comment":"The conclusion contains a typo: 'this work has proposed a a robust and adaptive manager' should read 'a robust and adaptive manager.'","section":"Section 6"},{"comment":"The max(0, T_d - T_a) term in Eq. (7) is redundant given the timing constraint in Eq. (11), which already enforces T_a <= T_d; simplifying the expression would avoid confusion.","section":"Section 3.3"}],"recommendation":"major_revision","confidential_remarks":"The paper is a competent systems-integration study with a transparent experimental setup. The main issues are technical rather than presentational: the energy objective simplification is not justified under the paper's own efficiency-crossover evidence, and the deadline-satisfaction claim is not validated end-to-end. Both are fixable within the scope of the manuscript, so I recommend major revision rather than rejection. The authors should also consider whether the 'first to integrate' claim is appropriately scoped relative to the related-work table, since the novelty is primarily in the combination of known mechanisms."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: this is a credible design-time scheduler for heterogeneous ULP platforms, and the integration it does—kernel-level DVFS, per-kernel scheduling, adaptive tiling, deadline-aware energy minimization—is genuinely new relative to the cited literature. But the paper's optimality argument has a hole that the authors' own Figure 7 exposes. I'd still send it to reviewers, with a clear request to fix or reframe the claim.\n\nWhat's good: The problem is real. Most existing DNN deployment work either ignores DVFS, schedules at block-level, or doesn't handle tiling under tight memory. MEDEA solves an MCKP over per-kernel configurations on a concrete platform (HEEPTimize) with a plausible characterization pipeline. The evaluation uses a transformer-based seizure detection model, which is a good test case. The feature ablation (DVFS, scheduling, tiling) is a nice way to separate contributions. The paper is honest about the FPGA/EDA characterization.\n\nWhere it's soft: Section 3.3 claims that any faster schedule must use higher V-F and thus higher active energy, so the optimal policy is to minimize active energy while filling the deadline. That reasoning assumes execution time and active energy are monotonically related for each kernel. The paper's own Figure 7 shows the CGRA/Carus energy ratio crosses over as voltage changes. So a faster schedule could move a kernel to the other accelerator at a higher V-F and end up with lower active energy. The proof does not go through. This matters because Eq. (10) is not equivalent to Eq. (7) in general. The ILP solutions are feasible and probably good, but 'globally energy-optimal' is not established. The reported 14/38/7% savings may shift, though I don't think they're likely to reverse.\n\nSecond, the deadline compliance is model-estimated, not measured end-to-end. The active times in Table 5 sit exactly on the deadline in the tight cases, which is a clue that the timing model is the arbiter. FPGA cycle counts are real, but power from EDA at 22nm is still an estimate. I'd want the authors to say that plainly in the abstract and conclusions.\n\nThird, no code or data. That's a minor issue for a systems paper, but given the non-fabricated platform, artifacts would help reviewers check the characterization.\n\nBottom line: This paper deserves a serious referee. It's not a desk reject. The authors have a working manager and a transparent evaluation. They need to either prove (or add conditions for) the monotonicity assumption, or reframe the optimization as a heuristic for minimizing total energy. I'd recommend major revision.","headline":"Solid systems integration with a real hole in the optimality argument; worth reviewing, but the claim needs to be fixed or softened.","tokens_in":19308,"tokens_out":2592,"would_cite":false,"duration_ms":26478,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A design-time scheduler that chooses per-kernel processor, voltage-frequency, and tiling can reduce DNN inference energy by up to 38% on ultra-low-power heterogeneous chips while meeting deadlines.","keywords":["ultra-low power systems","DNN inference scheduling","heterogeneous processing elements","kernel-level DVFS","memory-aware tiling","design-time optimization","transformer seizure detection","multiple-choice knapsack problem"],"falsifier":"Fabricate the HEEPTimize chip, run the TSD workload at the 200 ms deadline using MEDEA's schedule, and compare measured end-to-end latency and total energy against the predicted 200.0 ms and 395 µJ; a deadline miss or an energy total above the prediction by more than the model's margin would contradict the central claim.","tokens_in":18131,"feed_emoji":"⚡","tokens_out":9284,"duration_ms":87894,"temperature":0.7,"pith_summary":"The paper proposes MEDEA, a design-time manager that decides for each kernel of a DNN which processing element should run it, at which voltage-frequency point, and with which memory tiling mode. The aim is to minimize total energy for one inference window while respecting an application deadline. Using a heterogeneous ultra-low-power platform with a RISC-V core plus two accelerators, the authors show that per-kernel choices outperform baselines that pick one accelerator or one voltage for the whole workload, with energy savings up to 38 percent and all timing constraints met. A reader should care because these are the decisions a wearable or implantable device must make to run AI within milliwatt power budgets, and the paper gives a concrete recipe for computing them ahead of time.","feed_headline":"Per-kernel DVFS and tiling cut DNN energy by up to 38 percent","feed_subtitle":"A design-time scheduler chooses processor, voltage, and buffering per kernel while staying inside hard deadlines.","key_machinery":"The load-bearing object is the per-kernel execution configuration $\\omega_{ij} = (p_{ij}, v_{ij}, c_{ij})$: a processor, a voltage/frequency operating point from the platform's discrete V-F set, and a tiling mode (single- or double-buffered). A timing model $G_T(\\cdot)$ converts profiled cycle counts and data-movement cycles into execution time, and power profiles supply active and idle power; together they give each configuration an energy cost and a time weight. MEDEA pre-selects the faster tiling mode for each processor/V-F pair, then solves a multiple-choice knapsack problem with the deadline as capacity and total active energy as the objective, using an ILP solver to pick exactly one configuration per kernel. This mechanism makes the scheduling problem a finite combinatorial optimization that can be solved at design time.","core_discovery":"MEDEA's central claim is that the energy-optimal execution of a DNN on a heterogeneous ULP platform is found by co-optimizing three kernel-level knobs: processor assignment, voltage/frequency setting, and single- versus double-buffered tiling, all under a hard deadline. The paper models each kernel as an item group whose configurations have an energy cost and a time weight, casts the whole workload as a multiple-choice knapsack problem, and solves it with integer linear programming. Evaluated on the HEEPTimize platform running a Transformer seizure-detection model, this yields 14%, 38%, and 7% energy reductions over the strongest baseline at 50 ms, 200 ms, and 1000 ms deadlines, while always completing within the deadline. The paper further claims that the relative energy efficiency of the two accelerators crosses over as voltage changes, so the best processor for a kernel can depend on the deadline.","pith_inferences":["The paper's formulation does not depend on transformers; any DNN expressible as a sequence of supported kernels could be scheduled the same way once profiles exist, so the method should extend to CNNs, GNNs, and other workloads without changing the optimizer.","The measured efficiency crossover between the two accelerators suggests that PE rankings are voltage-dependent; if that pattern holds generally, hardware selection for ULP systems should be characterized per V-F point rather than per PE.","Because the search is done at design time, the method's practical cost is offline; one extension would be to precompute schedules for a library of DNNs and deadlines, then load the appropriate schedule at runtime.","The paper stops short of validating on fabricated silicon; a natural follow-up is to measure the same schedules on the real chip and compare energy and latency against the model predictions."],"forward_implications":["Under MEDEA's model, finishing earlier than the deadline is never beneficial when idle power is positive, because any faster schedule costs more active energy and leaves a longer sleep interval.","Kernel-level DVFS contributes the largest share of the savings: 31.3% at the 200 ms deadline, while contributing nothing at 1000 ms because all kernels already run at the lowest V-F point.","Adaptive tiling, choosing single- versus double-buffering per kernel, yields 4.8% to 8.5% energy savings across the tested deadlines.","The optimal processor for a kernel can switch with the deadline; as voltage drops, the CGRA becomes relatively more energy-efficient than the NMC, so PE selection and V-F selection must be co-optimized.","A schedule that meets the deadline and minimizes active energy can be extracted directly from the ILP solution and applied at runtime without further search."],"supporting_citations":[{"why":"Supplies the open-source X-HEEP microcontroller and accelerator interface that the evaluation platform HEEPTimize is built on.","marker":"[30]"},{"why":"Describes the Carus near-memory-computing accelerator, one of the two specialized PEs MEDEA schedules kernels onto.","marker":"[4]"},{"why":"Describes the OpenEdgeCGRA coarse-grained reconfigurable array, the other specialized PE in the evaluation.","marker":"[27]"},{"why":"Provides the Transformer for Seizure Detection model and the TUSZ EEG dataset used in the case study.","marker":"[1, 21]"},{"why":"Supplies the low-cost softmax approximation that makes the transformer's softmax kernels practical on the ULP platform.","marker":"[18]"},{"why":"Grounds the idle/sleep power term in the energy objective and the frequency-selection reasoning for deadline-aware operation.","marker":"[33]"},{"why":"Serves as the coarse-grained scheduling baseline whose grouping strategy MEDEA's energy savings are measured against.","marker":"[2]"},{"why":"Represents application-level DVFS scheduling against which kernel-level DVFS is compared.","marker":"[13]"}],"fun_headline_variants":["Co-optimizing DVFS, processor choice, and tiling cuts DNN energy by 38%","Per-kernel scheduling under deadline: up to 38% energy savings on ULP","Design-time manager co-optimizes voltage, processor, and buffering for DNNs","Voltage-aware cross-over: best DNN accelerator depends on deadline","MEDEA: energy-aware DNN scheduling on heterogeneous ULP with hard deadlines"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central results assume that cycle counts measured on an FPGA and power numbers estimated by an ASIC design flow reflect real fabricated silicon closely enough that MEDEA's predicted energies and deadlines are accurate; if either estimate is wrong, the claimed energy savings and deadline guarantees would not hold on physical hardware.","fun_headline_variants_meta":{"raw":{"variants":["Co-optimizing DVFS, processor choice, and tiling cuts DNN energy by 38%","Per-kernel scheduling under deadline: up to 38% energy savings on ULP","Design-time manager co-optimizes voltage, processor, and buffering for DNNs","Voltage-aware cross-over: best DNN accelerator depends on deadline","MEDEA: energy-aware DNN scheduling on heterogeneous ULP with hard deadlines"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00091,"raw_usage":{"total_tokens":3958,"prompt_tokens":1042,"completion_tokens":2916,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":658,"completion_tokens_details":{"reasoning_tokens":2806}},"tokens_in":658,"tokens_out":2916,"duration_ms":20820,"temperature":1.0,"reasoning_tokens":2806,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T18:38:14.428849+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate the HEEPTimize chip, run the TSD workload at the 200 ms deadline using MEDEA's schedule, and compare measured end-to-end latency and total energy against the predicted 200.0 ms and 395 µJ; a deadline miss or an energy total above the prediction by more than the model's margin would contradict the central claim.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the open-source X-HEEP microcontroller and accelerator interface that the evaluation platform HEEPTimize is built on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Describes the Carus near-memory-computing accelerator, one of the two specialized PEs MEDEA schedules kernels onto."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Describes the OpenEdgeCGRA coarse-grained reconfigurable array, the other specialized PE in the evaluation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the low-cost softmax approximation that makes the transformer's softmax kernels practical on the ULP platform."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Grounds the idle/sleep power term in the energy objective and the frequency-selection reasoning for deadline-aware operation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Serves as the coarse-grained scheduling baseline whose grouping strategy MEDEA's energy savings are measured against."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Represents application-level DVFS scheduling against which kernel-level DVFS is compared."}],"review_version":2}