{"id":"b90d004c-9102-48e0-ab7b-fe1c183e935e","arxiv_id":"2507.04773","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A Josephson field-effect transistor with a ferroelectric HfO2 gate operates as a non-volatile cryogenic single-bit memory cell at 50 mK, retaining data for over 24 hours and through thermal cycling above the superconducting critical temperature.","lead":"Researchers built a superconducting transistor with a ferroelectric gate that remembers its state, and used it as a cryogenic memory cell that holds data for at least 24 hours. The device keeps its memory even when warmed above the temperature where its metal contacts stop superconducting, which could make future quantum control electronics more robust.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Ferroelectric mechanism is asserted from transfer-curve hysteresis alone; the paper's own text invokes charge trapping, and no P-E or control experiment rules out trapping or ion motion.","rationale":"The reader's weakest assumption identifies exactly the load-bearing point: ferroelectricity is claimed from hysteresis direction without direct polarization or structural evidence, and the authors themselves admit that unintentional doping and trapping cannot be excluded. My stress-test confirms this and adds a specific internal inconsistency in the Results section, where the observed hysteresis is described as due to 'charge trapping' in the same paragraph that introduces the ferroelectric explanation. This strengthens the need for the reader's conditional verdict rather than moving it to another category: the memory-cell operation is supported by the presented device data, but the central mechanistic claim of ferroelectricity is not. A PUND measurement on the same gate stack, or a matched control device with a non-ferroelectric gate electrode, would settle whether the term 'ferroelectric' is warranted. Until such data are supplied, the paper should remain conditionally accepted, not fully accepted as a demonstration of ferroelectricity in a Josephson FET.","tokens_in":15085,"tokens_out":5043,"duration_ms":60626,"concrete_test":"Fabricate a co-processed metal-insulator-metal capacitor using the same 30-nm ALD HfO2 recipe and the same pristine Al top-gate metal, and measure a positive-up/negative-down (PUND) or quasi-static polarization-voltage loop at cryogenic temperatures. If no remanent polarization hysteresis is observed, the ferroelectric interpretation fails. In parallel, measure a control JoFET from the same ALD batch with an Au or Ti/Al top gate: if the same hysteresis direction appears, the observed transfer hysteresis is not attributable to ferroelectricity and should be reassigned to charge trapping or mobile ions.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that the hysteresis in IS(VGS) and RN(VGS) originates from ferroelectric polarization of the ALD-grown HfO2 layer, making the device a ferroelectric Josephson FET. The evidence for this mechanism is only the orientation of the transfer-characteristic hysteresis: the paper states that charge trapping would give the opposite trend (Fig. S1b). No direct polarization-voltage loop, no structural phase identification (e.g., GIXRD or PFM), and no matched control device with an identical gate stack but a non-ferroelectric top gate are presented in this work. More troubling, the manuscript itself contains an internal inconsistency: after ruling out electron trapping as the mechanism, the next paragraph describes the observed behavior as 'thanks to the charge trapping activated by positive VGS values, the depletion of electrons from the InAs epilayer into interfacial traps...' (Results, Figure 2 discussion). That sentence describes the charge-trapping mechanism the authors otherwise exclude. The authors also concede that 'unintentional doping during the ALD process cannot be completely ruled out.' Because the retention, reset, and thermal-cycling demonstrations are equally consistent with trapped charge or mobile ions, the memory functionality does not by itself validate the ferroelectric interpretation. The key mechanistic assertion is therefore under-supported as presented.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a Josephson FET fabricated on the InAsOI platform with a 30-nm ALD-grown HfO2 gate insulator. The device exhibits hysteresis in the switching current IS and normal-state resistance RN as a function of gate voltage VGS, which the authors attribute to ferroelectric polarization of the HfO2 layer. They demonstrate that the hysteresis can be controlled by the VGS range and that the device can be reset to a pristine state by an ambipolar gating protocol. They then operate the device as a cryogenic superconducting single memory cell, with two states defined by write pulses at ±3 V and read at 0 V, showing reproducible readouts over 10 cycles, retention for 24 h, and survival of a warm-up to 1.5 K (above Al Tc). They also propose a fully non-dissipative readout scheme based on the difference in Josephson inductance between the two states.","tokens_in":15335,"tokens_out":5124,"duration_ms":50563,"significance":"The manuscript addresses an important gap: cryogenic non-volatile memories compatible with superconducting circuits. The memory demonstrations are well-executed: clear hysteresis, reproducibility, 24-h retention, and thermal cycling are all presented with quantitative state values and variation estimates. The device concept (ferroelectric gate on a Josephson FET) is novel if the ferroelectric interpretation holds. However, the central mechanistic claim rests on indirect evidence, and the manuscript contains an internal inconsistency in which charge trapping is invoked in the same section that argues for ferroelectricity. If the authors can provide direct structural or electrical evidence of ferroelectricity (P-E loops, PFM, GIXRD) or a matched control experiment, this would be a significant contribution. The paper is clearly written and the experimental methods are described in sufficient detail to be reproduced.","major_comments":[{"comment":"The text states 'thanks to the charge trapping activated by positive VGS values, the depletion of electrons from the InAs epilayer into interfacial traps results in a reduced switching current and increased normal-state resistance during the downward VGS scan.' This sentence explicitly describes charge trapping as the operative mechanism, directly contradicting the ferroelectric interpretation given elsewhere in the same paragraph and in the abstract. This internal inconsistency is load-bearing: if charge trapping controls the hysteresis, the ferroelectric claim is unsupported. Please resolve whether the mechanism is ferroelectric polarization or trapped charge, or provide evidence distinguishing the two.","section":"Results and Discussion, Figure 2 discussion"},{"comment":"The identification of ferroelectricity is based solely on the orientation of hysteresis in IS(VGS) and RN(VGS) compared to a schematic (Figure S1b). No direct polarization–electric field measurement, structural phase analysis (e.g., GIXRD or PFM), or matched control device without a ferroelectric gate stack is presented. The statement that ALD-grown HfO2 in this chamber is ferroelectric without intentional doping when capped with Al is an assertion; the comparison with Au or Ti/Al gates refers to previous work (refs [26,29]), not to control devices in this study. Because charge trapping or mobile ions can produce the same hysteresis, retention, and thermal cycling behavior, the central mechanistic claim is under-supported as presented.","section":"Results and Discussion, Figures 1 and S1"},{"comment":"The paper concedes that 'unintentional doping during the ALD process cannot be completely ruled out.' This admission, combined with the lack of direct structural evidence, means the reproducibility and generality of the ferroelectric phase in this stack are not established. At minimum, the text should either present evidence that the observed behavior is ferroelectric or temper the abstract and conclusions accordingly (e.g., 'hysteresis consistent with ferroelectric-like behavior').","section":"Results and Discussion, Figure 2 discussion"}],"minor_comments":[{"comment":"In the caption, 'block dots' should be 'black dots'.","section":"Figure 1d caption"},{"comment":"The phrase 'we observed ferroelectricity' is used in the abstract and introduction; given that the evidence is indirect and contested in the text, this should be rephrased to 'hysteresis consistent with ferroelectric behavior' unless direct evidence is added.","section":"Abstract and Introduction"},{"comment":"In the memory operation, state 1 is dissipative because the read current IREAD is chosen between IS,0 and IS,1 (IREAD = (IS,0 + IS,1)/2), not because the device itself is dissipative in that state. The text should clarify that the dissipative/non-dissipative distinction is a readout choice, and that both states can be non-dissipative if IREAD < IS,1.","section":"Results and Discussion, Figure 4"},{"comment":"The Josephson inductance calculation assumes IREAD << IS,1, but the earlier readout uses IREAD = (IS,0 + IS,1)/2, which is not small compared to IS,1. The relationship between the two operating regimes should be stated to avoid confusion about the validity of the inductance formula.","section":"Conclusions, inductive readout proposal"}],"recommendation":"major_revision","confidential_remarks":"The paper's central novelty is the claim of ferroelectricity in a superconducting FET. The reviewer is not convinced that the current evidence excludes charge trapping or ion migration. I recommend requesting direct evidence (e.g., P-E loops on the same ALD HfO2 film, PFM, or a control device with a known non-ferroelectric gate). If the authors cannot provide such evidence, the claims should be scaled back to 'hysteresis' rather than 'ferroelectricity.' The paper otherwise merits consideration for publication in a strong applied physics journal, given the quality of the electrical characterization and the potential interest of a cryogenic superconducting memory cell."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThe memory cell is probably real; the ferroelectric mechanism is not yet proven. If you work on cryogenic memory or hybrid superconducting electronics, pay attention to the device demonstration. If you are reading for hafnium ferroelectricity, this paper won't convince you.\n\nWhat is actually new: first Josephson FET with a ferroelectric gate insulator. The authors show hysteresis in switching current and normal-state resistance as the gate range grows, two stable states at VGS=0 over 10 write/read cycles (CV ~12%), 24 h retention, and state survival through a thermal cycle above Al Tc. The ambipolar reset protocol is a useful practical addition. The inductive readout is a standard LJ = hbar/(2e IS) estimate, no back-fitting; IREAD is just a chosen bias.\n\nThe soft spot is load-bearing and the manuscript itself flags it. The ferroelectric claim rests on the orientation of the hysteresis loop. There is no P-V loop, no structural phase identification, and no matched control device with a non-ferroelectric gate stack. The text says trapping would give the opposite trend, then two paragraphs later says 'thanks to the charge trapping activated by positive VGS values...' while describing the observed depletion. That is the trapping mechanism they just excluded. They also concede unintentional ALD doping cannot be ruled out. The prior observation that Al gates are needed for ferroelectricity in their ALD HfO2 is referenced, not shown here. So the memory function and thermal stability stand, but they are equally consistent with trapped charge or ion motion. Add single-device data, and the mechanism is under-supported, not disproved. The citation pattern is fine; the self-citations to the InAsOI platform and prior JoFET work are appropriate.\n\nWho this is for: groups working on cryogenic memory architectures and gate-programmable superconducting electronics. It deserves a serious referee, with a clear request for direct polarization or structural evidence, a control device, and reproducibility across devices. Conditional acceptance is the right call; the engineering is solid, the physics claim needs one more round of experiments.","headline":"A credible cryogenic memory cell with a ferroelectric label that the data do not yet prove.","tokens_in":15851,"tokens_out":3399,"would_cite":true,"duration_ms":36859,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["74.50.+r","85.25.Cp"],"model":"deepseek-v4-flash","headline":"A Josephson field-effect transistor with a hafnium-oxide gate shows ferroelectric hysteresis at 50 mK and acts as a non-volatile superconducting memory cell that keeps a bit for 24 hours and survives warming above the aluminum critical…","keywords":["ferroelectricity","Josephson field-effect transistor","hafnium oxide","InAs on insulator","cryogenic memory","non-volatile memory","hysteresis","superconducting electronics"],"falsifier":"Measure polarization versus voltage on the same Al/HfO2/InAs gate stack at cryogenic temperature, or run an identical device with a gate metal that does not stabilize the ferroelectric phase; if no ferroelectric P-V hysteresis appears while the transfer hysteresis persists, the central mechanism is not supported.","tokens_in":14891,"feed_emoji":"❄️","tokens_out":9285,"duration_ms":89518,"temperature":0.7,"pith_summary":"This paper reports a ferroelectric Josephson field-effect transistor made on an InAs-on-insulator platform, with a 30 nm hafnium-oxide gate insulator, measured at 50 mK. Its central claim is that the HfO2 layer acts as a ferroelectric at cryogenic temperatures, so the transistor's switching current and normal-state resistance depend on the history of the gate voltage and remain different at zero gate voltage. The authors use the two resulting states as a non-volatile superconducting single memory cell: one state is a zero-voltage supercurrent-carrying conductor, the other is dissipative. They report state retention for 24 hours and persistence after warming above the critical temperature of the aluminum electrodes. The device also returns to a pristine state when swept with an alternating-sign ambipolar gate routine, and the memory effect only appears once the gate-voltage range exceeds about ±2 V.","feed_headline":"This superconducting transistor remembers a bit for 24 hours","feed_subtitle":"Its HfO2 gate stays polarized below 1 K, so a memory state survives even a warm-up past the superconducting transition.","key_machinery":"The central mechanism is the remanent polarization of the ALD-grown HfO2 layer, roughly 31 nm thick, placed between the aluminum gate and the InAs channel. According to the paper, a negative remanent polarization at zero gate voltage accumulates electrons in the InAs epilayer, raising the supercurrent and lowering the normal-state resistance; a positive remanent polarization depletes electrons, with the opposite effect. The sign of the remanent polarization is set by the direction from which the gate voltage is swept, and the authors argue that the aluminum gate electrode plays an active role in stabilizing the ferroelectric phase of nominally undoped HfO2, with unintentional doping during ALD not completely ruled out. The ambipolar gating protocol, in which the sign alternates while the magnitude first increases then decreases, erases the polarization history and resets the device.","core_discovery":"On the paper's own terms, the discovery is that ferroelectricity appears in a superconducting Josephson FET below 1 K: the ALD-grown HfO2 gate insulator on the InAsOI platform shows hysteretic transfer characteristics in both the switching current IS(VGS) and the normal-state resistance RN(VGS), with the hysteresis loop orientation matching n-type ferroelectric behavior rather than charge trapping. Because the hysteresis opens only for gate voltage ranges of at least [-2,2] V, the authors treat the polarization state as programmable: writing at ±3 V and reading at 0 V yields two reproducible states, with IS,0 = 536 ± 8 nA and RN,0 = 41.0 ± 0.3 Ω for state 0, and IS,1 = 33 ± 4 nA and RN,1 = 110.1 ± 1.2 Ω for state 1. The state is non-volatile over 24 hours and survives a thermal cycle to 1.5 K, above the aluminum critical temperature of 1.2 K, because the ferroelectric polarization acts on the carrier density of the InAs channel independently of whether the electrodes are superconducting. The authors further show that an alternating-sign ambipolar gate sweep restores the device to a pristine, non-polarized condition, erasing prior history.","pith_inferences":["A direct polarization-voltage measurement on the same HfO2 stack at 50 mK would be the natural next step; until that is shown, trapped charge at the InAs/HfO2 interface remains a possible alternative explanation for the observed hysteresis loop orientation.","If the ferroelectric assignment holds, engineering the HfO2 with silicon or zirconium doping, which the authors mention as future work, could increase the remanent polarization and make the write voltages lower and the hysteresis window wider.","The write-read voltage asymmetry suggests a memory array design where the write word-line voltage is higher than the read voltage, but the paper does not demonstrate array-level operation or cross-talk behavior."],"forward_implications":["A read current chosen between IS,1 and IS,0 makes state 0 a zero-voltage non-dissipative path and state 1 a resistive dissipative path, so the stored bit can be sensed directly as a voltage.","Since the hysteresis peak sits near 0 V, the device can be written at ±3 V and read at 0 V, cutting the read voltage in half and lowering read energy.","The state survives continuous readout for 24 hours and a warm-up to 1.5 K, so the memory cell tolerates temperature oscillations and cryostat failures without losing data.","If the read current is kept below IS,1, both encoded states are non-dissipative and differ in Josephson inductance, 0.6 nH versus 10.0 nH, allowing an AC inductive readout with zero active power under the paper's linear inductance model."],"supporting_citations":[{"why":"Provides the InAs-on-insulator platform with the semi-insulating buffer that isolates the InAs channel and hosts the Josephson junction.","marker":"[25]"},{"why":"Supplies the charge-trapping transfer characteristic with the opposite hysteresis direction, which the authors use as the control comparison to distinguish ferroelectric behavior.","marker":"[29]"},{"why":"Gives the cryogenic ALD HfO2 deposition details, relative permittivity, and dielectric strength used for the gate stack.","marker":"[26]"},{"why":"Establishes the material premise that hafnium oxide thin films can be ferroelectric.","marker":"[3]"},{"why":"Provides the expected n-type ferroelectric FeFET transfer hysteresis behavior that the measured loop orientation is compared against.","marker":"[28]"},{"why":"Documents doped hafnium oxide as a ferroelectric system, supporting the claim that the Al gate or unintentional doping stabilizes the ferroelectric phase and the proposed doped-HfO2 integration route.","marker":"[31]"}],"fun_headline_variants":["Superconducting FET with ferroelectric gate stores bits","Ferroelectricity meets superconductivity in a cryogenic transistor","Memory survives warm-up: superconducting FET stays ferroelectric","HfO2 gate yields non-volatile memory in superconducting transistor","Cryogenic memory cell endures temperature faults"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the hysteresis loop direction observed in IS(VGS) and RN(VGS) is caused by ferroelectric polarization of the HfO2 layer and not by charge trapping, since the paper does not show a direct polarization-voltage loop or a non-ferroelectric control stack.","fun_headline_variants_meta":{"raw":{"variants":["Superconducting FET with ferroelectric gate stores bits","Ferroelectricity meets superconductivity in a cryogenic transistor","Memory survives warm-up: superconducting FET stays ferroelectric","HfO2 gate yields non-volatile memory in superconducting transistor","Cryogenic memory cell endures temperature faults"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000327,"raw_usage":{"total_tokens":1910,"prompt_tokens":1105,"completion_tokens":805,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":721,"completion_tokens_details":{"reasoning_tokens":723}},"tokens_in":721,"tokens_out":805,"duration_ms":8587,"temperature":1.0,"reasoning_tokens":723,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T19:39:46.438392+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure polarization versus voltage on the same Al/HfO2/InAs gate stack at cryogenic temperature, or run an identical device with a gate metal that does not stabilize the ferroelectric phase; if no ferroelectric P-V hysteresis appears while the transfer hysteresis persists, the central mechanism is not supported.","supporting_citations":[{"cited_title":"Paghi, S","cited_arxiv_id":null,"evidence_quote":"Establishes the material premise that hafnium oxide thin films can be ferroelectric."}],"review_version":1}