{"id":"f2f558e1-87d0-49ae-b527-4af7355907ed","arxiv_id":"2507.10912","paper_version":1,"verdict":"REJECT","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"high","formal_verification":"none","parameter_count":4,"one_line_summary":"Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.","lead":"This paper adds an ASIC-style standard-cell mapping step before FPGA LUT mapping and uses a reinforcement-learning bandit to pick a subset of library cells for each design. It reports reducing LUT count by about 9% on average across common benchmark circuits.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Claimed RL advantage is not isolated: reported results are best-of-search over 25 iterations x 5 sample sizes with no equal-budget random-sampling baseline, so the 8-9% average improvement may reflect search effort rather than learned cell selection.","rationale":"The paper's contribution is twofold: the idea of fusing ASIC mapping before LUT mapping, and the RL-based library tuning to make design-specific cell selections. The first part is supported by the motivating case study, but the second part is the novel contribution that justifies the FuseMap framework. The evaluation protocol directly undermines this contribution by reporting best-of-search outcomes across 25 iterations and five sample sizes without comparing to random sampling under the same budget. Since the paper's own Figure 1 shows that random sampling can find large improvements on individual designs, the reported average improvements are exactly what one would expect from a random search with many trials, unless the MAB is shown to steer selections more effectively. The absence of an equal-budget random baseline is therefore the load-bearing weakness: if that test fails, the central claim that RL-driven design-specific cell selection improves mapping quality is unsupported. The reward normalization inconsistency between Section IV (full-library ASIC mapping as baseline) and Section V (vanilla LUT mapping as comparison baseline) compounds the problem by making it unclear what objective the MAB actually optimizes. The reader's weakest_assumption identified the same core issue, and my independent reading agrees: the claim of RL-specific benefit is not isolated from search effort. A single decisive experiment - random sampling at equal budget - would settle whether the concern lands.","tokens_in":12322,"tokens_out":4475,"duration_ms":51221,"concrete_test":"Run a random library sampler with the same search budget on the 24-design ASAP7 benchmark set: for each design, evaluate 25 iterations x 5 sample sizes {30,40,50,60,70} x batch size 10, sampling each subset uniformly at random, and take the best #LUT and ADP per design as FuseMap does. If the random best-of-budget results match or beat FuseMap's reported averages, then the RL guidance is not the source of the improvement. Also recompute the reported averages using the median over runs rather than the best to quantify selection bias.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that FuseMap's RL-guided cell selection improves LUT mapping quality. Section V states: 'We evaluate the mapped results with different sampling sizes in FuseMap, which searches for the best achievable results.' For each design, FuseMap runs 25 iterations over sample sizes {30,40,50,60,70} (with batch size 10, i.e. many map calls per design) and Figure 3 reports the best outcome. No comparison is made to random library sampling with the same number of mapping calls. The motivating case study (Figure 1) already shows that random sampling of 80/161 ASAP7 cells can reduce #LUT by up to 30% on some designs, though average results are worse. Thus the reported 'consistent improvements' and average 9% ADP reduction could be the best-of-many-random-subsets artifact rather than the MAB policy's learned preferences. There is no ablation, no mean/median/error bars, and no equal-budget random baseline. If random sampling at equal budget matches or beats FuseMap, the RL-specific contribution collapses, leaving only the fused-mapping observation. Additionally, the reward definition in Section IV uses DBase and ABase from full-library ASIC mapping, while Section V compares against vanilla LUT mapping; this mismatch means the optimand and reported metric are not aligned, further obscuring what is being measured.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes FuseMap, a framework that inserts an ASIC standard-cell technology mapping step before FPGA LUT mapping and uses a multi-armed bandit (MAB) approach—specifically epsilon-greedy and UCB agents—to select a per-design subset of the ASIC library. The reported results claim average improvements of 8% in LUT count and 9% in area-delay product (ADP) over vanilla ABC LUT mapping, evaluated on benchmarks from ISCAS85/89, ITC/ISCAS99, VTR, and EPFL, with convergence plots and a comparison across two technology libraries. The central claim is that RL-guided cell selection makes fused ASIC-then-LUT mapping consistently better than vanilla LUT mapping.","tokens_in":12610,"tokens_out":5668,"duration_ms":65736,"significance":"If the claims are validated, the fused-mapping observation is genuinely interesting: it suggests that a partial standard-cell library can act as a pre-packing restructuring step that benefits LUT mapping, without changing the FPGA architecture. The paper makes source code available and uses standard benchmarks and libraries, which is a concrete strength. However, the current evidence does not isolate the RL contribution. The reported results are explicitly best-of-search values over 25 iterations and five sample sizes, and no equal-compute random-sampling baseline is provided. The motivating case study itself shows that random sampling can already produce up to 30% LUT reduction on some designs, so the claimed 8-9% averages may reflect search effort rather than learned cell-selection policy. The RL-specific contribution is therefore unproven, although the fused-mapping direction may still be worth pursuing.","major_comments":[{"comment":"The reported FuseMap results are selected as the best over 25 iterations and sample sizes {30,40,50,60,70} with batch size 10, as stated in Section V: 'we evaluate the mapped results with different sampling sizes in FuseMap, which searches for the best achievable results.' No random-sampling baseline is reported with the same number of mapping calls or the same best-of-search protocol. Figure 1 already demonstrates that random sampling of 80/161 ASAP7 cells can reduce #LUT by up to 30% on s832a, while average results are worse. Thus the average 8-9% improvements over vanilla LUT mapping could be an artifact of the number of random trials rather than evidence that the MAB policy learns design-specific cell selections. Please add an equal-budget random subset baseline and report mean, median, and dispersion over independent runs.","section":"Section V (Results)"},{"comment":"The reward function is defined as RS = -(DS/DBase) * (AS/ABase), where DBase and ABase are 'established using all the cells in the original library for technology mapping' (i.e., full-library ASIC mapping). Section V, however, reports all improvements relative to vanilla LUT mapping. This is a mismatch between the objective being optimized and the metric being reported. A subset that maximizes reward relative to full-library ASIC mapping is not necessarily better than vanilla LUT mapping, so the reported gains may not correspond to the intended optimization target. Please either redefine the reward baseline as vanilla LUT mapping or report results against the same baseline used in the reward.","section":"Section IV (Approach, Reward update)"},{"comment":"The claim of 'consistent improvements' is supported only by Figure 3, which shows normalized area, delay, and ADP per design with no error bars, no mean or median over independent runs, and no per-design table. The abstract and Section VI state an average 8% LUT improvement, while Section V states approximately 9%; these numbers must be reconciled. In addition, the statement that the full ISCAS89/EPFL/VTR suites (161 designs) confirm 9% ADP improvement is not backed by any figure, table, or detailed data in the manuscript.","section":"Section V (RQ1)"},{"comment":"The probability update equation is malformed as printed: pai(t+1) = pai(t)nai(t) + RS(t)na(t) is dimensionally inconsistent, and the denominator is missing or ambiguous. Given that this equation is the core learning update for both FuseMap-epsilon and FuseMap-UCB, it must be corrected and the notation for n_a(t) defined precisely. Without a correct update, the algorithm cannot be reproduced from the description.","section":"Section IV-B, Eq. (2)"}],"minor_comments":[{"comment":"There are typos in Section V: 'libary' should be 'library' and 'invovles' should be 'involves'.","section":"Section V (Results)"},{"comment":"The abstract and conclusions give 8% average LUT improvement, while Section V RQ1 states approximately 9%; please make the reported numbers consistent.","section":"Abstract and Section V"},{"comment":"Figure 3 does not specify whether each point is the best-of-search result, the final iteration result, or an average over runs, nor does it distinguish FuseMap-epsilon from FuseMap-UCB. Please state this clearly in the caption or text.","section":"Figure 3"},{"comment":"The notation p_ai and a_i is typeset inconsistently; please use a consistent subscript style and define all symbols in Table I.","section":"Table I and Section IV"}],"recommendation":"major_revision","confidential_remarks":"The manuscript relies heavily on the authors' prior MapTune work; the novelty is the application of the same MAB machinery to the fused ASIC-then-LUT mapping problem. This is acceptable if properly contextualized, but the paper should clearly distinguish what is new. The main risk is methodological: without an equal-budget random baseline and with a reward-metric mismatch, the central claim about RL-guided selection is not yet supported. These issues are fixable with additional experiments and analysis."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read the paper as a piece of empirical synthesis work with a genuinely new observation. The new thing is not the bandit. It's the demonstration that running ABC's ASIC mapper ('map -a') with a partial standard-cell library before 'if -K 6' can reduce LUT count or ADP, while using the full library tends to hurt. Figure 1 makes this believable: random 80-cell subsets of ASAP7 already find up to 30% LUT reduction on one design, though average behavior is mixed. That observation alone is worth having, and I don't know of earlier work doing exactly this fusion.\n\nWhat the paper does well: it is clearly written, uses standard ABC flows and public benchmarks (ISCAS/VTR/EPFL), reports runtime upper bounds, and links source code. Reusing the MapTune MAB machinery is fine; the formulation is concise.\n\nThe soft spot is exactly what the stress-test note says, and it is load-bearing. The reported numbers are best-of-search over 25 iterations and five sample sizes, with no random library sampling at the same compute budget. Their own motivating case study shows random sampling can produce large wins, so the 8-9% average improvement could be an artifact of how many arbitrary subsets were tried rather than evidence that the MAB learned something design-specific. There are no error bars or ablations. This needs an equal-budget random baseline before the central claim can be assessed.\n\nThere is also a metric mismatch: the reward normalizes against full-library ASIC mapping (DBase, ABase), while the reported baseline is vanilla LUT mapping. The paper never reconciles those two. Hyperparameters epsilon and c are never given, and the 'searches for best achievable results' protocol makes it hard to know what a user should actually run.\n\nThat said, this is not a desk reject. The application is new, the observation is concrete, and the paper is short enough that a serious referee could guide a focused revision. I would send it out, with instructions to demand the random baseline and a fixed protocol.","headline":"The fused-mapping observation is new and worth taking seriously, but the RL-specific 8-9% claim is not supported by the experiments as reported.","tokens_in":13142,"tokens_out":2650,"would_cite":false,"duration_ms":32941,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"FuseMap claims ASIC cell mapping run before FPGA LUT mapping cuts LUT count by 8% and area-delay product by 9%.","keywords":["FPGA technology mapping","LUT minimization","ASIC standard-cell mapping","fused mapping flow","multi-armed bandit","reinforcement learning","area-delay product","logic synthesis"],"falsifier":"On the same benchmarks, run the fused mapping with the same 25-iteration budget and subset sizes but replace FuseMap's bandit with a sampler that draws cell subsets uniformly at random each round (or keeps only the best random subset found so far). If random sampling reproduces the average 8% LUT reduction and 9% ADP improvement, the reinforcement-learning component is not carrying the result. A weaker check: compare the full-library baseline against the average reward across all 25 iterations per design, not just the best iteration; an average that fails to beat the baseline would show the reported gain comes from cherry-picking the best round.","tokens_in":12082,"feed_emoji":"⚙️","tokens_out":15398,"duration_ms":148380,"temperature":0.7,"pith_summary":"FPGA designers turn a Boolean network into LUTs — configurable blocks that each compute any function of K inputs, typically 4 to 6 — and the count and delay of those LUTs set the chip's area and speed. This paper claims that running an ASIC-style standard-cell mapper before LUT mapping, and feeding the resulting netlist into the FPGA mapper, consistently improves the FPGA result — but only if the ASIC cell library is a partial, design-specific subset, since the full library makes things worse. FuseMap finds that subset with a lightweight reinforcement learning loop: two multi-armed bandit agents repeatedly sample subsets of the library, run the fused mapping, and update cell-selection probabilities from the resulting LUT count, delay, or their product. Across ISCAS 85/89/99, VTR 8.0, and EPFL benchmark suites, the paper reports average gains of about 8% in LUT count and 9% in area-delay product, at the cost of at most 15 minutes of tuning per design. If correct, the result adds a new lever to FPGA logic synthesis that changes only the design recipe, not the FPGA architecture.","feed_headline":"FuseMap cuts FPGA LUT count 8% by borrowing ASIC cell mapping","feed_subtitle":"A bandit-tuned partial ASIC library, inserted before LUT mapping, improves FPGA results without changing the architecture.","key_machinery":"The load-bearing mechanism is a fused two-stage mapping flow: ASIC-style technology mapping (the area-driven map -a command in the synthesis framework ABC) applied to the optimized And-Inverter Graph (a Boolean network of two-input AND gates with inverters on edges), followed by LUT mapping (if -K 6 with mfs2 post-optimization). Around this flow, FuseMap wraps a multi-armed bandit (MAB) library tuner, a lightweight reinforcement learning scheme with two agents: $\\epsilon$-greedy, which chooses the currently best-scoring cell with probability $1-\\epsilon$ and a random cell otherwise, and UCB, which adds an exploration bonus $c\\sqrt{\\log(t)/n_{a_i}}$ to each cell's score. Each agent keeps a probability vector $p$ over the $N$ cells of the standard-cell library, samples a subset of $n$ cells per iteration, and updates $p_{a_i}(t+1) = (p_{a_i}(t)n_{a_i}(t) + R_S(t))/n_a(t)$, where $R_S$ is the negative of the normalized reward — LUT count, delay, or their product, ADP, each scaled by the full-library baseline. The reward is pluggable, so the same tuner could target predicted post-routing timing or congestion. Reported per-design tuning runs finish within 15 minutes and typically converge in 10-12 iterations.","core_discovery":"The paper's central discovery is a fusion effect: ASIC standard-cell mapping can serve as a pre-packing phase that improves FPGA LUT mapping, but only when the standard-cell library is deliberately narrowed to a design-specific subset. The motivating experiments show three things: fusing in the full-library ASIC mapper raises LUT count by 7-24% compared with plain LUT mapping; randomly sampled partial libraries can beat both the vanilla fused flow and the plain mapper, by up to 30% on individual designs; yet the same random samples typically worsen average results, so the right subset must be found per design. FuseMap automates that search with two bandit agents ($\\epsilon$-greedy and UCB) that keep a probability vector over the library's $N$ cells, sample a subset of $n$ cells, run the fused mapping, and update probabilities from a normalized reward based on LUT count, delay, or their product (ADP). The paper reports about 9% average LUT-count reduction, 3% delay reduction, and 9% ADP improvement across 24 designs with a 7nm library (the conclusions round the LUT gain to 8%), with the 9% ADP gain reproduced over a larger 161-design sweep; switching to a 45nm library changes the pre-LUT netlist structure and the results, showing the library choice itself matters.","pith_inferences":["The headline numbers are best-of-search: for each design the paper keeps the best outcome over 25 iterations and sample sizes {30, 40, 50, 60, 70}. A uniform-random library sampler given the same budget would test whether the bandit's learned selection — rather than search effort — is what produces the gains; that comparison is not in the paper.","If the fusion effect holds, LUT mapping could adopt standard-cell-like structures as an intermediate representation without an explicit ASIC mapper, for instance by synthesizing a synthetic cell library tuned to produce LUT-friendly netlists — a direction the paper notes but does not build.","A natural next experiment is transfer: whether the tuned library for one design helps similar designs, which would spread the per-design search cost across a benchmark suite or design family.","The delay metric here is LUT depth on the mapped network; carrying the fused flow through placement and routing would test whether the LUT-count and depth gains survive into wire delay and congestion."],"forward_implications":["A partial standard-cell library can outperform the full library as a pre-LUT mapping stage, so shrinking the ASIC library — normally expected to hurt mapping quality — can improve the downstream FPGA result for a specific design.","The gain is not tied to one technology: the same fused flow improves results with both 7nm and 45nm standard-cell libraries, suggesting the effect transfers across process design kits.","Per-design tuning is cheap — runs finish within 15 minutes and converge in about 10-12 iterations — so the search can be part of a normal synthesis run rather than a one-off offline optimization.","Because the reward is a configurable formula (LUT count, delay, or the product of LUT count and delay), the same bandit machinery extends to other objectives such as predicted post-routing timing or congestion."],"supporting_citations":[{"why":"The MAB-based library-tuning scheme that FuseMap adapts; supplies the probability-update and agent setup.","marker":"[29]"},{"why":"The ABC synthesis framework in which both ASIC and LUT mapping flows run; supplies the map, if, and mfs2 commands used.","marker":"[39]"},{"why":"Describes ABC's LUT mapping capabilities and serves as the state-of-the-art open-source mapper baseline that FuseMap must beat.","marker":"[40]"},{"why":"The epsilon-greedy exploration-exploitation strategy behind the FuseMap-eps agent.","marker":"[44]"},{"why":"The upper-confidence-bound strategy behind the FuseMap-UCB agent.","marker":"[45]"},{"why":"The ASAP7 7nm predictive process design kit used as the main standard-cell library in the experiments.","marker":"[46]"},{"why":"The FreePDK45 45nm library used to test whether the initial library choice changes fused-mapping results.","marker":"[47]"},{"why":"Supplies the ISCAS 85/89/99 benchmark circuits used in the evaluation.","marker":"[8]"},{"why":"Supplies the VTR 8.0 benchmark circuits used in the evaluation.","marker":"[9]"},{"why":"Supplies the EPFL benchmark circuits used in the evaluation.","marker":"[10]"}],"fun_headline_variants":["Bandit-picked ASIC cells trim FPGA LUTs","FuseMap bandit RL picks ASIC cells to cut LUTs","Design-specific ASIC cells cut FPGA LUTs by 9%","ASIC pre-mapping fuses into FPGA flow to cut LUTs"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The paper reports the best result each design reached during up to 25 rounds of tuning; its case depends on that best number showing the learning algorithm's skill, not just the luck of trying many random cell subsets.","fun_headline_variants_meta":{"raw":{"variants":["Bandit-picked ASIC cells trim FPGA LUTs","FuseMap bandit RL picks ASIC cells to cut LUTs","Design-specific ASIC cells cut FPGA LUTs by 9%","ASIC pre-mapping fuses into FPGA flow to cut LUTs"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001867,"raw_usage":{"total_tokens":7404,"prompt_tokens":1099,"completion_tokens":6305,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":715,"completion_tokens_details":{"reasoning_tokens":6226}},"tokens_in":715,"tokens_out":6305,"duration_ms":45885,"temperature":1.0,"reasoning_tokens":6226,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T17:22:01.094274+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On the same benchmarks, run the fused mapping with the same 25-iteration budget and subset sizes but replace FuseMap's bandit with a sampler that draws cell subsets uniformly at random each round (or keeps only the best random subset found so far). If random sampling reproduces the average 8% LUT reduction and 9% ADP improvement, the reinforcement-learning component is not carrying the result. A weaker check: compare the full-library baseline against the average reward across all 25 iterations per design, not just the best iteration; an average that fails to beat the baseline would show the reported gain comes from cherry-picking the best round.","supporting_citations":[{"cited_title":"Maptune: Advancing asic technology mapping via reinforcement learning guided library tuning","cited_arxiv_id":null,"evidence_quote":"The MAB-based library-tuning scheme that FuseMap adapts; supplies the probability-update and agent setup."},{"cited_title":"Abc: A system for sequential synthesis and verification","cited_arxiv_id":null,"evidence_quote":"The ABC synthesis framework in which both ASIC and LUT mapping flows run; supplies the map, if, and mfs2 commands used."},{"cited_title":"ABC: An Academic Industrial- strength Verification tool","cited_arxiv_id":null,"evidence_quote":"Describes ABC's LUT mapping capabilities and serves as the state-of-the-art open-source mapper baseline that FuseMap must beat."},{"cited_title":"Upper confidence bound based decision making strategies and dynamic spectrum access","cited_arxiv_id":null,"evidence_quote":"The upper-confidence-bound strategy behind the FuseMap-UCB agent."},{"cited_title":"Asap7: A 7-nm finfet predictive process design kit","cited_arxiv_id":null,"evidence_quote":"The ASAP7 7nm predictive process design kit used as the main standard-cell library in the experiments."},{"cited_title":"URL https://eda.ncsu.edu/freepdk/freepdk45/","cited_arxiv_id":null,"evidence_quote":"The FreePDK45 45nm library used to test whether the initial library choice changes fused-mapping results."},{"cited_title":"Combinational profiles of sequential benchmark circuits","cited_arxiv_id":null,"evidence_quote":"Supplies the ISCAS 85/89/99 benchmark circuits used in the evaluation."},{"cited_title":"VTR 8.0: Next generation architecture and CAD system for FPGAs","cited_arxiv_id":null,"evidence_quote":"Supplies the VTR 8.0 benchmark circuits used in the evaluation."}],"review_version":1}