{"id":"6a34979e-0f10-40ed-9131-b231177b5853","arxiv_id":"2507.20412","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"RoCE BALBOA is an open-source, 100G-capable RoCE v2 RDMA stack for FPGAs that interoperates with standard switches and NICs and supports line-rate service offloads with direct GPU memory access.","lead":"The authors present RoCE BALBOA, an open-source FPGA implementation of a 100G RoCE v2 RDMA network stack that runs on commodity switches and talks to commercial NICs. It adds on-the-fly encryption, machine-learning packet inspection, and GPU-direct data preprocessing to the network datapath.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 'fully RoCE-v2 compatible' claim is load-bearing and rests only on one-sided WRITE/READ tests; two-sided SEND/RECV and error recovery are untested, so the compatibility scope should be narrowed or demonstrated.","rationale":"The reader's weakest assumption identifies the same load-bearing concern: full RoCE-v2 conformance is inferred from a narrow one-sided test set. The abstract and Section 1 make an unconditional 'fully RoCE-v2 compatible' claim, while Section 2 narrows the implementation to one-sided operations and Section 6.1 evaluates only RDMA WRITE and RDMA READ against Mellanox NICs. This gap directly affects the strongest claim, because a researcher who builds on BALBOA expecting complete RoCE-v2 interoperation must know whether SEND/RECV, NAK-based error recovery, and out-of-order-PSN handling actually work. The paper's performance results, open-source availability, and switched-network measurements are genuine strengths, and I do not see an internal inconsistency that invalidates the reported throughput or latency. The missing conformance evidence does not require rejecting the paper; it requires either adding the tests or qualifying the compatibility claim. Since the reader already returned a CONDITIONAL verdict and my concern matches that condition, the verdict remains unchanged.","tokens_in":22252,"tokens_out":3851,"duration_ms":43793,"concrete_test":"Run the InfiniBand perftest suite between a Mellanox ConnectX-5 and BALBOA on the same switched 100G testbed, specifically ib_send_bw and ib_send_lat to exercise two-sided SEND/RECV in RC mode, and then force a single packet drop mid-transfer (e.g., via a switch ACL or a programmable switch) to verify NAK generation and retransmission recovery. If SEND/RECV and the forced-drop recovery pass, the 'fully RoCE-v2 compatible' label is justified; if either fails, the paper must state that compatibility is limited to one-sided RC operations.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that BALBOA is 'fully RoCE-v2 compatible' (Abstract; Section 1) is broader than what Sections 2 and 6.1 actually establish. Section 2 explicitly says 'BALBOA concentrates on one-sided operations', and Section 6.1 measures only RDMA WRITE and RDMA READ between BALBOA and Mellanox NICs through a Cisco switch. No SEND/RECV, no ATOMIC, no NAK generation for invalid or out-of-order PSNs, no retransmission recovery after forced packet loss, and no multi-QP error behavior is reported. Because the abstract and contribution list use 'fully RoCE-v2 compatible' without a one-sided-only qualifier, the headline interoperability claim depends on an untested subset of the RC service. This is not a performance issue; it is a scope-of-claim issue. Compatibility with commercial NICs in the tested subset is well supported, but the unconditional 'fully compatible' wording is insufficiently supported. The open-source repository and the switched-network performance measurements are real evidence, but they do not close this protocol-conformance gap.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents RoCE BALBOA, an open-source FPGA-based RDMA stack targeting 100G data centers. The stack implements the RoCE v2 protocol in Reliable Connection mode, focusing on one-sided operations (RDMA WRITE and RDMA READ), and includes retransmission buffering, flow control, and an ICRC pipeline. The authors deploy BALBOA on AMD Alveo U55C FPGAs in a switched cluster and report throughput and latency results for FPGA-to-FPGA, FPGA-to-Mellanox, and Mellanox-to-Mellanox configurations. They also demonstrate protocol enhancements (AES encryption and ML-based deep packet inspection) and an offloaded DLRM preprocessing pipeline with direct-to-GPU DMA, and report resource utilization. The central claim is that BALBOA is a fully RoCE-v2-compatible, 100G-capable, open-source stack with performance comparable to commercial NICs.","tokens_in":22427,"tokens_out":5323,"duration_ms":58175,"significance":"The open-source release, the real-cluster switched-network evaluation, and the direct comparison against Mellanox ConnectX-5 NICs are concrete strengths. The tested one-sided RDMA WRITE and READ operations achieve line rate and interoperate with a commercial NIC through a Cisco switch, which is a meaningful step for FPGA-based RDMA research. The on-datapath service slots and the DLRM preprocessing use case demonstrate a useful design pattern for SmartNICs. The main caveat is that the unconditional 'fully RoCE-v2 compatible' claim is broader than the tested subset; if the claim is properly scoped or the missing conformance tests are added, this would be a valuable open platform for SmartNIC and in-network computing research.","major_comments":[{"comment":"The abstract and the contribution list in Section 1 describe RoCE BALBOA as 'fully RoCE-v2 compatible' without qualification, but Section 2 states that 'BALBOA concentrates on one-sided operations,' and Section 6.1 evaluates only RDMA WRITE and RDMA READ against a Mellanox NIC through a switch. No tests are reported for two-sided SEND/RECV, ATOMIC operations, NAK generation for invalid or out-of-order PSNs, retransmission recovery under forced packet loss, or multi-QP error behavior. Because the headline interoperability claim is load-bearing, this scope gap must be addressed: either add conformance tests for these RC service behaviors, or explicitly re-scope the claim to 'one-sided RC operations' in the abstract and contribution list.","section":"Abstract, Section 1, Section 2, Section 6.1"},{"comment":"The DPI use case reports detection rates of 97.83% for whole packets and 89.35% for partially embedded executables, but does not report the false positive rate, the dataset size, or the decision threshold. Without these numbers, the claim that the service offers a 'highly effective and fine-grained differentiation policy' is not fully supported. Please provide a confusion matrix or at minimum the false positive rate and the composition of the test set.","section":"Section 6.4.2"},{"comment":"The abstract claims BALBOA is 'scalable up to hundreds of queue-pairs' and Section 4.1 states that the default tables support 500 QPs, but Section 6.3 does not report the number of QPs used in the multi-QP scaling experiment or the QP count at which fairness degrades. Please state the number of concurrent QPs tested and, if possible, show scaling up to at least 100 QPs to substantiate the abstract's claim.","section":"Section 6.3 and Section 4.1"}],"minor_comments":[{"comment":"In Figure 4a and 4c, the Mellanox-to-Mellanox throughput curves are plotted without the P5/P95 percentiles shown for the other curves; please clarify whether this is intentional or add the variability information.","section":"Section 6.1"},{"comment":"The text states the local PCIe path is limited to approximately 70 Gbps (8500 MB/s), but 8500 MB/s equals approximately 68 Gbps; please correct the rounding for consistency.","section":"Section 8.2"},{"comment":"The sentence referring to 'the native false positive rate of flagging acceptable payloads' is incomplete because the actual false positive rate is never reported; please provide the number or remove the reference.","section":"Section 6.4.2"},{"comment":"The 44 ns inference latency for the DPI module is given, but the FPGA clock frequency is not stated; please specify the clock frequency to make the latency number reproducible.","section":"Section 5.1.2"},{"comment":"Some references have formatting issues, notably reference [22] which contains a stray backtick in the author name; a careful proofread of the reference list is needed.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The paper fits the scope of the venue well and the open-source release is a strong point. The main risk is the overbroad 'fully RoCE-v2 compatible' claim, which the authors can address by either adding conformance tests or carefully re-scoping the claim. The performance evaluation methodology is generally solid, and the use cases are compelling."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's my take on RoCE BALBOA. The thing to know is that this is a real, open, 100G FPGA RDMA stack that interoperates with commercial Mellanox NICs through a Cisco switch, and the authors have measured it properly. The second thing is that the headline 'fully RoCE-v2 compatible' claim is broader than what the evaluation supports. Section 2 says the stack concentrates on one-sided operations, and Section 6.1 only exercises RDMA WRITE and READ between BALBOA and a ConnectX-5. No SEND/RECV, no ATOMIC, no NAK generation for bad PSNs, no recovery after forced packet loss. So if you read 'fully compatible' as protocol conformance, that part isn't demonstrated. The fix is either to qualify the claim or to run those tests.\n\nWhat's genuinely new here is the integrated package: an open-source, extendable RoCE v2 stack that does DMA to GPUs, works in a switched network, and provides exchangeable service slots on the datapath. No single piece is novel — the DPI comes from the authors' own EuroMLSys paper, the AES core from their repo, and the ICRC approach from Schelten et al. — but the combination, plus the pinned open-source repo, gives the community a much-needed platform for experimenting with protocol enhancements and offloads. That is a real contribution.\n\nThe performance evaluation is solid for what it covers: measurements on a public cluster, FPGA-to-FPGA and FPGA-to-Mellanox, plus a fat-tree topology check. The multi-QP fairness result and the resource table are useful. The DLRM preprocessing use case is a nice demonstration of the direct-to-GPU path at ~8.5 GB/s, and the comparison against a CPU implementation is fair enough.\n\nSoft spots beyond the compatibility overreach: Table 1's legend is garbled — it lists the same symbol as both 'satisfied' and 'not satisfied' — so the comparison table is currently unreadable. The BlueField 3 encryption comparison is not a direct measurement; it's a citation and 'initial research.' Fine as context, but don't present it as a head-to-head. And the DPI evaluation gives detection rates for malicious payloads but omits the false positive rate, which is exactly the number you need to judge the security claim.\n\nMy bottom line: this paper deserves a serious referee. The artifact and the measurements are worth having in the literature. I'd send it to review with the expectation that the authors narrow the compatibility claim or add the missing protocol tests, fix the table, and report the DPI false positive rate.","headline":"An open, genuinely useful FPGA RoCE stack with real switched-network measurements; just don't take 'fully RoCE-v2 compatible' literally — it's tested only for one-sided WRITE/READ.","tokens_in":23027,"tokens_out":3175,"would_cite":true,"duration_ms":32148,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"RoCE BALBOA is an open-source FPGA RDMA stack that claims full RoCE v2 compatibility at 100G with performance comparable to commercial NICs, and uses its openness to put protocol enhancements and application offloads directly on the…","keywords":["RDMA","RoCE v2","FPGA","SmartNIC","network stack","datapath offload","GPU DMA","deep packet inspection"],"falsifier":"Run a standards-level RoCE v2 interoperability test in which BALBOA exchanges two-sided SEND/RECV messages with a commercial NIC, forces duplicate, out-of-order, and lost packets to check NAK and retransmission behavior, and stresses multiple QPs under congestion; if any of those exchanges fails or the link no longer stays at line rate, the full-compatibility claim falls.","tokens_in":22025,"feed_emoji":"🖧","tokens_out":6593,"duration_ms":72471,"temperature":0.7,"pith_summary":"The paper sets out to show that a fully open, customizable RDMA endpoint for FPGAs can be built to the RoCE v2 standard and can hold its own against commercial NICs in a switched 100G data center network. If true, it would give researchers a line-rate platform for building SmartNICs and in-network accelerators without being locked into closed silicon. The paper demonstrates the payoff with two kinds of extension: protocol-level services (AES encryption and machine-learning deep packet inspection) and application-level compute (recommender-system preprocessing) executed as data streams through the NIC, including direct DMA to a GPU. The central claim is that performance comparable to commercial NICs does not require giving up openness and extensibility.","feed_headline":"FPGA RDMA stack saturates 100G and talks to commercial NICs","feed_subtitle":"An open-source RoCE v2 endpoint lets researchers add encryption, packet inspection, and preprocessing on the datapath.","key_machinery":"The load-bearing mechanism is a 512-bit-wide AXI-stream packet processing pipeline clocked at 250 MHz, giving 128 Gbps of internal bandwidth against the 100G line rate, with per-queue-pair tables (connection, PSN state, and MSN sequence control) that let the stack track, accept, drop, or retransmit packets in hardware. Around that pipeline sit an HBM-backed retransmission buffer, an ACK-clocked flow-control and crediting mechanism, a specialized ICRC checksum block that handles full, partial, and 32-bit AXI beats in parallel, and defined slots for exchangeable on-datapath and parallel-path services. These slots are what carry the paper's extensions: AES-ECB encryption on the datapath, an ML-based deep packet inspection module on a parallel path, and user logic that can forward or transform payloads before DMA to host or GPU memory.","core_discovery":"In the paper's own terms, RoCE BALBOA is a fully RoCE-v2 compatible, 100G-capable RDMA network stack for data center FPGAs that interoperates with commercial NICs through switched networks and offers latency and throughput comparable to those NICs. It is built as a customizable packet-processing pipeline with exchangeable on-datapath and parallel-path service slots, allowing protocol enhancements to be inserted without breaking line rate. Using this design, the paper shows RDMA WRITE and RDMA READ both saturate a 100G link in FPGA-to-FPGA and FPGA-to-commercial-NIC flows, and demonstrates on-datapath AES encryption that adds only 25 ns of latency, an ML deep-packet-inspection service whose inference time is hidden by the pipeline, and a recommender preprocessing pipeline that streams data straight to GPU memory at up to 8500 MB/s versus roughly 700 MB/s for a CPU implementation.","pith_inferences":["The paper's compatibility evidence is limited to one-sided RDMA WRITE and READ in a narrow test matrix; if two-sided SEND/RECV, NAK generation, and out-of-order or duplicate PSN recovery are also conformant, the stack becomes a credible alternative to commercial NICs for a much wider class of systems research.","Because the stack is open and the service slots are AXI-stream based, the same architecture could host other line-rate functions the paper does not implement, such as data compression, parsing, or transparent traffic monitoring, with the DPI and encryption modules as templates.","A testable extension is to benchmark the DPI model against a live attack replay or against NVMe-over-RDMA traffic carrying real malware, rather than the CSV/PNG/TXT versus executable training distributions used here.","If adopted as a platform, the open stack could make congestion-control and load-balancing proposals comparable across labs, since every group would run the same hardware datapath rather than vendor-specific emulation."],"forward_implications":["If the compatibility claim holds, researchers can use an open FPGA stack as a drop-in RDMA endpoint for data center experiments, including mixed deployments with commercial NICs and switches.","Protocol security gaps in RoCE v2, such as missing encryption and weak access control, can be patched at the NIC datapath while preserving CPU and OS bypass.","Data preprocessing for GPU workloads can move out of the CPU entirely: the paper's recommender pipeline runs at line rate on the NIC and writes directly to GPU memory.","New congestion control and network services, such as DCQCN or TIMELY-style schemes, can be implemented and evaluated in hardware without waiting for vendor NIC firmware.","The small resource footprint (roughly 4% of FPGA LUTs in the report) leaves room for multiple user offloads alongside the stack in a single accelerator."],"supporting_citations":[{"why":"Supplies the baseline RoCEv2 FPGA implementation and the ICRC checksum technique that BALBOA reimplements in its parallel beat pipelines.","marker":"[60]"},{"why":"Prior open-source FPGA RDMA stack that BALBOA builds on and extends with switch/NIC interoperability and GPU DMA.","marker":"[62]"},{"why":"Commercial NIC baseline for interoperation and performance comparison in the evaluation.","marker":"[68]"},{"why":"Alternative FPGA shell used to show the stack can be ported beyond its primary evaluation environment.","marker":"[80]"},{"why":"FPGA shell and abstractions that form the deployment environment for the evaluated prototype.","marker":"[56]"},{"why":"Source of the tabular preprocessing operators used in the recommender-system on-datapath use case.","marker":"[82]"},{"why":"Prior design of ML-based deep packet inspection that BALBOA integrates as a parallel-path service.","marker":"[31]"},{"why":"Public research cluster used for the switched 100G network evaluation with FPGAs and commercial NICs.","marker":"[53]"}],"fun_headline_variants":["Open-source RDMA stack brings line-rate services to FPGAs","Open-source FPGA RDMA stack hits 100G with commercial NICs","Reconfigurable RDMA pipeline: line-rate encryption, ML, and preprocessing on FPGAs","BALBOA: An open RDMA stack for smartNIC services at 100G","FPGA RDMA with on-path services: encryption, DPI, and preprocessing at line rate"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"Full RoCE-v2 conformance is assumed from a narrow test set: only one-sided RDMA WRITE and RDMA READ were measured between BALBOA and one brand of commercial NIC through a switch, leaving two-sided SEND and RECV, NAK generation, and duplicate or out-of-order PSN recovery untested.","fun_headline_variants_meta":{"raw":{"variants":["Open-source RDMA stack brings line-rate services to FPGAs","Open-source FPGA RDMA stack hits 100G with commercial NICs","Reconfigurable RDMA pipeline: line-rate encryption, ML, and preprocessing on FPGAs","BALBOA: An open RDMA stack for smartNIC services at 100G","FPGA RDMA with on-path services: encryption, DPI, and preprocessing at line rate"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000553,"raw_usage":{"total_tokens":2682,"prompt_tokens":1035,"completion_tokens":1647,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":651,"completion_tokens_details":{"reasoning_tokens":1537}},"tokens_in":651,"tokens_out":1647,"duration_ms":13263,"temperature":1.0,"reasoning_tokens":1537,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T13:33:29.690645+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a standards-level RoCE v2 interoperability test in which BALBOA exchanges two-sided SEND/RECV messages with a commercial NIC, forces duplicate, out-of-order, and lost packets to check NAK and retransmission behavior, and stresses multiple QPs under congestion; if any of those exchanges fails or the link no longer stays at line rate, the full-compatibility claim falls.","supporting_citations":[{"cited_title":"A high-throughput, resource-efficient implementa- tion of the rocev2 remote dma protocol and its application","cited_arxiv_id":null,"evidence_quote":"Supplies the baseline RoCEv2 FPGA implementation and the ICRC checksum technique that BALBOA reimplements in its parallel beat pipelines."},{"cited_title":"Strom: smart remote memory","cited_arxiv_id":null,"evidence_quote":"Prior open-source FPGA RDMA stack that BALBOA builds on and extends with switch/NIC interoperability and GPU DMA."},{"cited_title":"Mellanox connectx ®-5 ex ether- net single and dual qsfp28 port adapter cards user man- ual, 2018","cited_arxiv_id":null,"evidence_quote":"Commercial NIC baseline for interoperation and performance comparison in the evaluation."},{"cited_title":"A primer on reconic: Rdma-enabled compute offloading on smartnic, 2023","cited_arxiv_id":null,"evidence_quote":"Alternative FPGA shell used to show the stack can be ported beyond its primary evaluation environment."},{"cited_title":"J., AND ALONSO , G","cited_arxiv_id":null,"evidence_quote":"FPGA shell and abstractions that form the deployment environment for the evaluated prototype."},{"cited_title":"Efficient Tabular Data Preprocessing of ML Pipelines","cited_arxiv_id":"2409.14912","evidence_quote":"Source of the tabular preprocessing operators used in the recommender-system on-datapath use case."},{"cited_title":"J., R AMHORST , B., AND ALONSO , G","cited_arxiv_id":null,"evidence_quote":"Prior design of ML-based deep packet inspection that BALBOA integrates as a parallel-path service."},{"cited_title":"fpgasys- tems/hacc: Ethz-hacc","cited_arxiv_id":null,"evidence_quote":"Public research cluster used for the switched 100G network evaluation with FPGAs and commercial NICs."}],"review_version":1}