{"id":"42e5fc9e-aa3a-464b-a554-50b8379b8ea9","arxiv_id":"2507.21306","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A 22-nm FDSOI CMOS chip with 384 p-type silicon quantum dots and on-chip electronics is characterized at deep cryogenic temperatures, linking device dimensions to yield and charge noise.","lead":"This paper reports the monolithic integration of 384 p-type silicon quantum dots with on-chip electronics in a 22-nm FDSOI CMOS chip at deep cryogenic temperatures, and uses automated analysis to link device dimensions to quantum dot yield and charge noise. The significance is a step toward scalable silicon spin qubit processors that integrate control electronics with the qubit array.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Yield percentages rest on an unvalidated n-to-p transfer of the Diamondsky classifier; without p-type validation the headline 30% at PCL=28 nm is not yet established.","rationale":"The engineering claim—a 384-device p-type farm with integrated multiplexing measured near 600 mK—is plausible and independently supported by the classical transistor characterization in Section II, the on-chip thermometry citation, and the prior n-type farm work in ref. [10]. I do not see an internal inconsistency in the classical data. The load-bearing step is Section III's use of Diamondsky to label p-type Coulomb diamonds. Ref. [10] describes training on n-type devices; the present manuscript reports no p-type validation. Because hole and electron quantum dots differ in confinement and charging-energy scales, a CNN decision boundary trained on n-type maps may not transfer, and if it does not, the 30% vs <10% yield comparison collapses. This is a correctness risk, not a stylistic concern. The abstract's wording '384 p-type quantum dots' is also stronger than the body's '384 devices' with ~30% yield at the best geometry; that should be qualified. The reader's CONDITIONAL verdict already captures the necessary condition—classifier validation and statistical detail—so no verdict change is needed.","tokens_in":7169,"tokens_out":5510,"duration_ms":68355,"concrete_test":"Take a stratified random sample of Coulomb maps, at least ~50 per (PCL, RXW) cell in Fig. 3 (or all 384 if practical); have at least two independent experts, blinded to Diamondsky labels, classify them as QD/No QD using the same rubric. Compute expert-expert agreement and expert-vs-Diamondsky agreement. If per-cell agreement falls below ~90%, or if retraining the classifier on a p-type-labeled subset changes the PCL=28 nm yield by more than ~5 percentage points, the yield claim is not supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative conclusions—'QD' yield ~30% at PCL=28 nm vs <10% at 40 nm (Section III, Fig. 3)—are produced by the Diamondsky CNN classifier trained in ref. [10] on n-type Coulomb diamond maps. The text gives no evidence that the decision boundary transfers to p-type devices: no retraining, no p-type validation subset, no confusion matrix, no confidence-score audit. Hole dots differ from electron dots in charging energy, lever arm, and visibility of excited states, so a classifier tuned to n-type contrast could systematically over- or under-count QDs. Since these yields are the basis for recommending PCL <= 28 nm in future runs, the unvalidated transfer is load-bearing. Secondary: even accepting the classifier, the abstract's phrase '384 p-type quantum dots' overstates the body's claim of 384 devices with ~30% yield at the best geometry. Charge-noise medians (Table I) also lack n and error bars, but the yield/dimension conclusion is the main quantitative result.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports cryogenic characterization of 384 p-type single-hole transistors fabricated in a commercial 22-nm FDSOI CMOS process and integrated in a multiplexed farm with on-chip electronics. The authors measure classical DC parameters (threshold voltage, DIBL, subthreshold swing) as a function of gate length, apply an automated CNN classifier (Diamondsky) from prior work to label Coulomb diamond maps as 'QD' or 'No QD', and report quantum dot yield versus device dimensions, with about 30% good dots at PCL=28 nm versus below 10% at PCL=40 nm. They also report charge noise from peak-tracking measurements, with median S0 around 6.5 micro-eV per root hertz and gamma around 1.25. The paper concludes that future fabrication runs should focus on PCL at or below 28 nm and that the results demonstrate a path to monolithic integration of quantum and classical electronics at scale.","tokens_in":7399,"tokens_out":6433,"duration_ms":70752,"significance":"If the findings are robust, the paper is a valuable scaling study: it shows that a commercial FDSOI process can host hundreds of hole-based quantum dot devices with integrated multiplexing at deep cryogenic temperatures, and it identifies a geometry-dependent yield trend that can inform future process runs. The use of automated machine-learning classification for high-throughput cryogenic characterization is a useful methodological contribution. However, the central yield result currently rests on an unvalidated transfer of a classifier from n-type to p-type devices, and the statistical basis for the headline percentages is incomplete. The abstract also overstates the number of demonstrated quantum dots. These issues need to be addressed before the quantitative claims can be fully accepted.","major_comments":[{"comment":"The yield percentages in the bottom panels of Fig. 3 are generated by the 'Diamondsky' CNN from ref. [10], which was trained on n-type Coulomb diamond maps using domain-expert labels. The manuscript gives no evidence that the decision boundary transfers to p-type devices: there is no retraining on p-type data, no p-type validation subset with expert labels, no confusion matrix, and no confidence-score audit. Because hole and electron dots differ in charging energy, lever arm, and excited-state visibility, misclassification could systematically bias the central yield comparison (about 30% at PCL=28 nm versus below 10% at PCL=40 nm) and therefore the recommendation to focus future runs on PCL at or below 28 nm. Please provide p-type validation statistics, for example agreement, sensitivity, and specificity on an expert-labeled subset of p-type Coulomb maps, or explicitly re-present the yields as classifier outputs pending such validation.","section":"Section III, Fig. 3"},{"comment":"The abstract states that the work demonstrates 'the monolithic integration of 384 p-type quantum dots', but the body reports a farm of 384 p-type transistors of which only a fraction are classified as quantum dots (about 30% for the best geometry). This overstates the number of demonstrated quantum dots and should be corrected, for example to '384 single-hole transistors' with the yield statistics reported in Section III. The phrase 'quantum dot yield' already makes clear that not all devices form dots, so the abstract should be consistent with that.","section":"Abstract and Section III"},{"comment":"The yield percentages for each PCL and RX W combination are reported without sample sizes, error bars, or confidence intervals. The reader cannot determine how many devices underpin the 'about 30%' versus 'below 10%' comparison, whether the difference is statistically significant, or whether the yield varies across device instances within a cell. Reporting the number of devices per cell and confidence intervals for binomial proportions (e.g., Wilson intervals) is necessary to support the conclusion that PCL at or below 28 nm is the promising dimension for future runs. Without these, the headline yield comparison is not quantitatively established.","section":"Section III, Fig. 3 (bottom panels)"}],"minor_comments":[{"comment":"The number of devices used to compute the median S0 and IQR values is not stated; Fig. 4 shows only two devices, so it is unclear whether the table is based on two or many devices and whether the two example devices are representative. Please state the number of devices and their geometry.","section":"Section IV, Table I"},{"comment":"The caption reads 'two different device over 100 seconds'; this should be 'two different devices over 100 seconds'.","section":"Fig. 4 caption"},{"comment":"The text says all measurements are taken at base temperature (about 20 mK) with on-chip power dissipation raising the sample temperature to around 600 mK; it should be clarified whether the DC transistor data in Fig. 1 were recorded at 20 mK or at 600 mK, since this affects the comparison of subthreshold swing with theory.","section":"Section II"},{"comment":"The text states that the first-hole voltage V1h and the gate lever arm alpha are extracted, but the paper does not present these quantities or their statistics; either include the data or remove the claim from the description.","section":"Section III"},{"comment":"The box-and-whisker plots would benefit from a statement of the number of devices per gate length and the definition of outliers used in the whisker construction.","section":"Section II, Fig. 1"}],"recommendation":"major_revision","confidential_remarks":"The authors are from Quantum Motion, and the Diamondsky classifier is their own tool from ref. [10]; the lack of p-type validation is therefore a notable internal-method gap, and the abstract's overstatement about 384 quantum dots is likely to draw criticism. The paper fits the journal's scope and the underlying experimental effort is substantial. If the authors supply p-type validation, per-cell sample sizes with confidence intervals, and a corrected abstract, the paper could be acceptable. I would not recommend rejection if these issues are addressed in revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read it. The genuinely new thing is the dataset: 384 p-type transistors in a commercial 22-nm FDSOI process, characterized at ~600 mK with on-chip multiplexing, plus deep-cryogenic classical transistor metrics (Vth, DIBL, SS) across the farm and charge-noise statistics. That is a useful contribution for people trying to scale hole spin qubits in CMOS. The spatial uniformity plot for Vth and the observation that DIBL rises while |Vth| falls for shorter PCL are sane and match short-channel physics. The qualitative dimension-yield trend — PCL=28 nm clearly better than PCL=40 nm — is probably real, and the recommendation to focus future runs on PCL <= 28 nm is reasonable given the caveat about variability.\n\nSoft spots, in rough order of importance. First, the classifier transfer. Section III says the Diamondsky CNN trained on expert-labeled data in ref [10] was used for p-type devices, but there is no p-type validation subset, confusion matrix, or confidence audit. Hole dots have different lever arms, charging energies, and excited-state visibility, so the decision boundary could shift. Because the 30% vs <10% yield claim rests on this classifier, the missing validation genuinely weakens the quantitative conclusion. I would not call it fatal — the figures show examples that look like clear QDs vs noise, and the difference is large — but it needs to be addressed. Second, sample sizes. I could not find how many devices of each geometry were measured. The 30% and <10% are quoted without n or confidence intervals. Table I gives median S0 = 6.5 µeV/√Hz with IQR 17.5 and gamma 1.25, but no n; only two example traces are shown. This is fixable with a supplement table. Third, the abstract says '384 p-type quantum dots'; the body supports 384 fabricated p-type devices, with ~30% yielding good dots at the best geometry. That wording overstates the result.\n\nThe reader's take and the stress-test note land on the right issue. I don't think the concern is manufactured: it is a load-bearing missing validation, but it is also a common one in this area, and the underlying data look valuable enough that the paper deserves a serious referee rather than a desk reject. If the authors add per-geometry n, error bars, and at least a small p-type validation of the classifier, the central claims will probably hold. Who is this for: experimental groups working on CMOS spin qubits, cryo-CMOS, device variability, and anyone planning a large QD-farm run. I would bring it to our reading group and would probably cite it for the p-type FDSOI dataset. Recommendation: send to peer review, but flag the classifier validation and missing statistics as requirements for acceptance.","headline":"A real 384-device p-type FDSOI quantum-dot dataset, but the headline yield percentages need sample sizes and a p-type check of the classifier before they carry weight.","tokens_in":7964,"tokens_out":1751,"would_cite":true,"duration_ms":20124,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["85.35.Gv"],"model":"deepseek-v4-flash","headline":"A commercial 22-nm CMOS process can host 384 hole-based quantum dots, each in its own transistor, with on-chip control electronics operating at deep cryogenic temperatures.","keywords":["quantum dots","hole spin qubits","single-hole transistors","FDSOI CMOS","cryogenic electronics","charge noise","machine learning classification","Coulomb diamonds"],"falsifier":"Re-analyze the same farm's Coulomb-diamond maps with an expert human label set (or with a classifier retrained on p-type data) and compare the fraction labeled 'QD'. If the disagreement changes the reported ordering—30% at 28 nm versus under 10% at 40 nm—then the yield claim is an artifact of classifier transfer rather than a property of the devices.","tokens_in":6987,"feed_emoji":"⚛️","tokens_out":7426,"duration_ms":80872,"temperature":0.7,"pith_summary":"This paper attempts to show that a commercial 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS process can be turned into a platform for hole-based spin qubits by embedding hundreds of quantum dots in ordinary transistors. The authors fabricate a 'farm' of 384 p-type single-hole transistors with on-chip multiplexed digital and analog electronics, run it at deep cryogenic temperatures, and use a machine-learning classifier to sort Coulomb-diamond maps into 'QD' and 'No QD'. They find that the shortest available gate length, 28 nm, forms well-defined quantum dots about 30% of the time, while 40 nm gates succeed less than 10% of the time, and they report a median charge noise of roughly 6.5 micro-electron-volts per root hertz with a 1/f-like spectrum. If correct, this establishes both a scalability path—hundreds of quantum dots addressable with few lines—and a specific process target (gates at or below 28 nm) for future work.","feed_headline":"384 hole quantum dots run on a 22-nm CMOS chip","feed_subtitle":"Shortest gates give 30% dot yield and a path to integrating qubit control electronics at scale.","key_machinery":"The argument rests on three linked elements. The 'farm' is a multiplexed array of 384 p-type transistors in the 22-nm FDSOI process, each with a front gate length from 28 to 80 nm, and on-chip digital and analog electronics that allow one device to be addressed at a time with few lines—this is what makes large-scale characterization possible. The 'Diamondsky' analysis package, a convolutional-neural-network classifier trained in earlier work on expert-labeled maps, sorts Coulomb-diamond maps into 'QD' and 'No QD', turning raw transport data into yield statistics. The charge-noise arm uses an LC resonator to track a Coulomb peak position over 100 seconds, then fits the power spectral density to $S(f) = S_0 / f^\\gamma$ using Welch's method, producing the noise numbers that quantify the device environment.","core_discovery":"On the paper's own terms, the central discovery is that p-type quantum dots can be formed in 22-nm FDSOI transistors at scale: 384 devices, each a single-hole transistor, are measured in one cool-down through on-chip multiplexing, and their behavior is classified automatically. The key quantitative results are a strong gate-length dependence of dot yield—about 30% for PCL = 28 nm versus below 10% for PCL = 40 nm—and charge-noise parameters with median S0 of 6.5 micro-electron-volts per root hertz and gamma near 1.25, close to 1/f. The paper also reports classical cryogenic transistor behavior consistent with short-channel effects: threshold voltage magnitude decreases and drain-induced barrier lowering increases as gate length shrinks, while the spread in threshold voltage grows, and subthreshold swing averages about 16 mV/dec at an estimated chip temperature of roughly 600 mK. Together these results are taken as evidence that monolithic quantum-classical integration in a manufacturing process is realistic, with device dimensions serving as the dominant tuning knob.","pith_inferences":["If the yield ordering holds, the natural next step is to push below 28 nm or adjust the process at 28 nm to recover yield while controlling threshold-voltage variability, since the paper already shows variability grows at short gate lengths.","The median charge noise of 6.5 micro-electron-volts per root hertz is higher than values quoted for other platforms; this points to charge-noise reduction—through dielectric improvement or isotopic purification—as a prerequisite before these dots can act as qubits, a consequence the paper states qualitatively but does not translate into qubit-error rates.","A testable extension is to co-fabricate a second farm with gate lengths closely spaced around 28 nm (for example 24, 26, 28, 30 nm) to map the yield-versus-length curve and see whether the 30% figure is a plateau or a sharp maximum.","The same fast-readout plus classifier pipeline could be applied to n-type and p-type devices on the same chip to compare yield and charge-noise statistics between carrier types, separating process effects from hole-specific physics."],"forward_implications":["If the 28-nm result is representative, future 22-nm FDSOI fabrication runs should concentrate on gate lengths at or below 28 nm to maximize the number of usable quantum dots per chip.","A farm of 384 p-type dots with on-chip multiplexed access shows that hundreds of quantum devices can be addressed with a small number of cryogenic lines, directly addressing the I/O scaling bottleneck for spin qubits.","The measured median charge noise near 6.5 micro-electron-volts per root hertz at 1 Hz implies that charge noise, rather than device yield, may be the first limit on qubit coherence in these p-type devices, so noise reduction must accompany further process development.","The cryogenic classical parameters (threshold voltage, drain-induced barrier lowering, subthreshold swing) provide a rapid screening signature, and their observed short-channel trends mean device variability will grow as gates shrink toward the process minimum."],"supporting_citations":[{"why":"Supplies the 'Diamondsky' analysis package, the previously built farm design, and the convolutional-neural-network classifier used to label Coulomb-diamond maps as QD or No QD; the paper's yield statistics rest directly on this classifier.","marker":"[10]"},{"why":"Provides Welch's method, the spectral estimation technique used to compute power spectral densities from the 100-second peak-tracking traces, from which S0 and gamma are extracted.","marker":"[16]"},{"why":"Provides the on-chip diode thermometry used to determine that the sample temperature is around 600 mK during measurements, supporting the claim of deep-cryogenic operation.","marker":"[11]"},{"why":"Gives the deep-cryogenic quantum transport results for 40-nm MOSFETs used to compare the measured average subthreshold swing of 16.1 mV/dec against literature values.","marker":"[14]"},{"why":"Demonstrates multiplexed quantum transport using commercial CMOS at sub-kelvin temperatures, providing the basis for the on-chip multiplexing approach that the farm exploits.","marker":"[8]"}],"fun_headline_variants":["384 single-hole transistors measured at once on 22-nm chip","Gate length decides quantum dot yield in 22-nm CMOS","22-nm FDSOI hosts 384 p-type quantum dots","Quantum-classical integration at scale on 22-nm CMOS","Short gates triple quantum dot yield in 22-nm transistors"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the convolutional-neural-network classifier trained on n-type Coulomb maps in earlier work also correctly identifies p-type Coulomb maps, because the paper uses it without retraining or p-type-specific validation; if that transfer fails, the reported 30% and <10% yield figures would not be reliable.","fun_headline_variants_meta":{"raw":{"variants":["384 single-hole transistors measured at once on 22-nm chip","Gate length decides quantum dot yield in 22-nm CMOS","22-nm FDSOI hosts 384 p-type quantum dots","Quantum-classical integration at scale on 22-nm CMOS","Short gates triple quantum dot yield in 22-nm transistors"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000469,"raw_usage":{"total_tokens":2335,"prompt_tokens":947,"completion_tokens":1388,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":563,"completion_tokens_details":{"reasoning_tokens":1300}},"tokens_in":563,"tokens_out":1388,"duration_ms":11382,"temperature":1.0,"reasoning_tokens":1300,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T12:54:07.339410+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-analyze the same farm's Coulomb-diamond maps with an expert human label set (or with a classifier retrained on p-type data) and compare the fraction labeled 'QD'. If the disagreement changes the reported ordering—30% at 28 nm versus under 10% at 40 nm—then the yield claim is an artifact of classifier transfer rather than a property of the devices.","supporting_citations":[{"cited_title":"The use of fast Fourier transform for the estimation of power spectra: A method based on time averaging over short, modified periodograms,","cited_arxiv_id":null,"evidence_quote":"Provides Welch's method, the spectral estimation technique used to compute power spectral densities from the 100-second peak-tracking traces, from which S0 and gamma are extracted."},{"cited_title":"CMOS on-chip thermometry at deep cryogenic temperatures,","cited_arxiv_id":null,"evidence_quote":"Provides the on-chip diode thermometry used to determine that the sample temperature is around 600 mK during measurements, supporting the claim of deep-cryogenic operation."},{"cited_title":"Quantum Transport in 40-nm MOSFETs at Deep- Cryogenic Temperatures,","cited_arxiv_id":null,"evidence_quote":"Gives the deep-cryogenic quantum transport results for 40-nm MOSFETs used to compare the measured average subthreshold swing of 16.1 mV/dec against literature values."},{"cited_title":"Multiplexed quantum transport using commercial off- the-shelf cmos at sub-kelvin temperatures,","cited_arxiv_id":null,"evidence_quote":"Demonstrates multiplexed quantum transport using commercial CMOS at sub-kelvin temperatures, providing the basis for the on-chip multiplexing approach that the farm exploits."}],"review_version":1}