{"id":"37c2cf4b-279d-4239-8b4b-24edb0236a8b","arxiv_id":"2508.07523","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A 64-channel CARFAC cochlea accelerator on an AMD Kria KV260 FPGA processes 256 kHz audio in real time at 13.5% hardware utilization and 3.11 W board power.","lead":"This paper reports an FPGA implementation of a 64-channel CARFAC cochlea model on an AMD Kria KV260 board that processes 256 kHz underwater audio in real time using 13.5% of board resources and 3.11 W. A smart generalist might read it because it shows a low-power, bio-inspired front end for autonomous underwater acoustic sensing.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"DIHC replacement (Eqs. 4–6) imposes a hard 0.75 ceiling vs. the reference nonlinearity's limit of 1; with no output-level fidelity test, the 'CARFAC for underwater sensing' claim is unproven.","rationale":"The reader's weakest assumption was that the simplified fixed-point nonlinearities may not faithfully reproduce CARFAC's compression. My analysis sharpens that concern with a concrete, numerically checkable discrepancy: Eq. 4 saturates at 0.75 rather than the original limit 1, and intermediate-level errors are around 14–24%—not just a small-amplitude caveat. This is load-bearing because the DIHC output is part of the AGC feedback path, so the adaptive gain/compression that distinguishes CARFAC from a fixed filter bank is altered exactly in the high-level regime most relevant to underwater impulsive and close-range sources. The paper explicitly acknowledges the saturation but does not quantify its acoustic consequences, and no baseline output comparison or source artifacts are provided. The hardware claims (utilization, power, real-time throughput) are plausible and independently useful, but the central motivation—that this is a faithful CARFAC front end—remains conditional on a fidelity test that is currently absent. The reader's CONDITIONAL verdict is therefore the right call; no change is needed. A single straightforward reference-vs-FPGA comparison would settle whether the condition is met.","tokens_in":5492,"tokens_out":8603,"duration_ms":103034,"concrete_test":"Run the reference floating-point CARFAC v2 (Lyon et al.) and the FPGA/HDL implementation on identical inputs: a 256 kHz sine sweep at increasing amplitudes calibrated to drive BM_hpf to approximately 0, 0.5, 1, and 5, plus a high-amplitude impulsive transient. Record the DIHC vmem, AGC undamping u, and BM output traces from both. If the mean absolute DIHC error exceeds 10% of the reference at any level above the small-displacement range, or if the FPGA vmem saturates at 0.75 while the reference exceeds 0.8, then the approximations do not preserve CARFAC's fast-acting compression and the acoustic-fidelity claim should be revised.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that the FPGA is a faithful CARFAC front end for underwater sensing rests on the division-free nonlinearity replacements. The DIHC replacement is not merely a close fit that 'saturates more rapidly' as the authors note in Section II-A: it has a different saturation value. In the original Eq. 1, vmem = p^3/(p^3+p^2+0.1), so as BM_hpf → ∞, vmem → 1. In Eq. 4, vmem = 0.75(1−p)^2 with p → 0 as BM_hpf grows, so vmem → 0.75, a hard 25% ceiling. At intermediate levels the deviation is already substantial: for BM_hpf = 0.5 (p = 0.675), the original gives ≈0.356 while Eq. 4 gives ≈0.407 (~14% error); at BM_hpf = 1.0, the original gives ≈0.523 while Eq. 4 gives ≈0.648 (~24% error). Because the DIHC output feeds the AGC loop (Fig. 4), this distortion changes compression and adaptation dynamics precisely in the high-level regime—impulsive noise, close-range sources—that motivates CARFAC over a linear filter bank. The paper provides no comparison of the fixed-point FPGA outputs against the reference floating-point CARFAC, no high-SPL test, and no signal-fidelity metric. The hardware resource and power numbers can stand, but the claim that this is a CARFAC cochlea model for underwater sensing is not yet supported without demonstrating that the approximated nonlinearities preserve the reference model's compression behavior.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a fixed-point, division-free FPGA implementation of the CARFAC cochlear model on the AMD Kria KV260, with a Rust software layer for hydrophone input. The hardware uses time-multiplexing and pipelining to emulate 64 channels at 256 kHz, replacing three divisions by polynomial/max approximations. Reported metrics are 13.5% peak resource utilization, 3.11 W whole-board power, <7% ARM load, and headroom for about seven parallel instances. The central claim is that this constitutes a real-time, low-power CARFAC front end for underwater acoustic sensing.","tokens_in":6017,"tokens_out":8576,"duration_ms":98313,"significance":"If the hardware metrics are reproducible, the contribution is useful: it is a concrete embedded CARFAC accelerator with measured power and resource figures, improving scalability over the authors' earlier FPGA CARFAC work, and the g-polynomial approximation has apparently been adopted in CARFAC v2 (with R. Lyon's involvement), lending credibility. The paper's main gap is validation: no quantitative comparison of the approximated fixed-point CARFAC against reference floating-point CARFAC is provided, so the 'faithful CARFAC' part of the claim is not yet established. The hardware efficiency claim, however, is independent and likely valid, assuming the missing Table I is supplied.","major_comments":[{"comment":"The DIHC replacement is not a small-error approximation across the operating range. The reference vmem in Eq. (1) tends to 1 as BM_hpf grows, whereas Eq. (4) tends to 0.75 because p->0. At BM_hpf=0.5, Eq. (1) gives approximately 0.356 and Eq. (4) gives 0.418 (~17% error); at BM_hpf=1.0, approximately 0.523 vs 0.648 (~24% error). The authors acknowledge the approximation 'saturates more rapidly' and 'could limit the ability to represent amplitude at high levels,' but no quantitative consequence for the AGC loop (which is driven by vmem, Fig. 4) is given. The paper needs a reference comparison (floating-point CARFAC vs the fixed-point model) across input levels, including high SPL, before the system can be called a CARFAC model for underwater sensing; the hardware metrics alone do not establish this.","section":"Section II-A, Eqs. (4)–(6)"},{"comment":"The manuscript reports no verification that the time-multiplexed single AGC temporal-spatial filter (Fig. 4) reproduces the multi-time-scale AGC loop, nor any bit-true/fixed-point error analysis ('numerical accuracy carefully monitored' is not quantified). Because fast-acting compression is the defining feature that distinguishes CARFAC from a linear filter bank, the authors should add: level-sweep compression curves, an impulse/transient test, and a representative underwater recording processed by both the approximated fixed-point system and CARFAC v2, with a quantitative error metric (e.g., RMS/PSD error or downstream localization accuracy).","section":"Section II-B/II-C (AGC time-multiplexing and fixed-point quantization)"},{"comment":"Table I is not populated in the submitted manuscript, so the abstract's '13.5% hardware utilization' cannot be checked against per-resource numbers. Please provide the full post-implementation utilization (logic, FF, BRAM, DSP, URAM) and define what 'hardware utilization' means. Also describe the power measurement methodology (whole-board vs SoM, wall vs PMBus, idle baseline, input signal, duration) so the 3.11 W figure is reproducible.","section":"Section III, Table I and power measurement"}],"minor_comments":[{"comment":"'A, B and C are parameters that are pre-calculated lookup tables indexed by u' is ambiguous; if the coefficients are LUTs indexed by u, the expression is not a polynomial with fixed coefficients. Please clarify the implementation (one set of coefficients per channel, or a LUT over u).","section":"Eq. (12)"},{"comment":"Give the fixed-point formats (integer/fractional widths) chosen for the signal path and state the resulting SQNR or worst-case error for the internal variables.","section":"Section II-C"},{"comment":"The claim 'up to seven parallel CARFAC instances' assumes the 13.5% figure is the dominant resource; with mixed resource types, the actual parallelism limit should be stated for each resource.","section":"Section III"},{"comment":"Minor typographical/notation issues: 'zc0r' in Eq. (3) should be 'z c0 r' or 'c0 r z'; 'p8int' in Eq. (5) should read 'p_int^8'; Fig. 2 lacks axis labels for the two NLFs.","section":"Notation"}],"recommendation":"major_revision","confidential_remarks":"The hardware/power metrics appear promising and the authors' prior CARFAC FPGA line is relevant. The main editorial risk is that the title and abstract claim a 'CARFAC cochlea model' for underwater sensing; if the authors cannot supply a fidelity benchmark, the paper should be repositioned as a hardware implementation with preliminary resource results. I would not reject solely on the approximation issue, since it is addressable in revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague, short version: this is a plausible engineering paper with concrete resource and power numbers, but it overclaims what the approximations preserve. The DIHC replacement in Eqs. 4–6 really does change the saturation behavior, and there is no comparison to reference CARFAC outputs, so the “faithful cochlea model for underwater sensing” claim is not yet supported. The hardware work itself is real and worth engaging.\n\nWhat is actually new: the paper ships a division-free, time-multiplexed, pipelined CARFAC on the Kria KV260 with 13.5% utilization and 3.11 W for a 256 kHz input, with a Rust driver and AXI4-Stream DMA. That is a specific, reproducible implementation, not just a restatement of prior FPGA CARFAC work. The single-AGC time-multiplexing scheme and the polynomial approximation for g (Eq. 12) with 0.6% error are legitimate engineering contributions.\n\nThe load-bearing weakness is the nonlinearity approximations. The DIHC replacement has a hard 0.75 ceiling versus the original’s 1, and at BM_hpf = 1.0 the error is about 24%. The authors note the saturation issue themselves (Sec. II-A), but they do not quantify what that does to the AGC loop or to the actual outputs. There is no comparison of the fixed-point FPGA outputs to floating-point CARFAC in software, no high-SPL test, no fidelity metric. Without that, the system is a fast filter bank that resembles CARFAC at low levels; the underwater motivation—handling explosive sounds and ship noise—hinges on high-level compression. That is the gap.\n\nThe resource and power numbers come from synthesis and a 15-minute measurement, which is fine for the hardware claim. The improvement over prior work is incremental; the novelty is moderate, not paradigm-shifting. But the implementation claim is specific and checkable, and the fidelity gap is fixable with a validation section.\n\nThis paper deserves a serious referee. It is not ready as-is, but it is a legitimate engineering contribution, and the missing piece—a comparison to reference CARFAC, even a few plots, plus a discussion of the high-level saturation effect—is exactly what a revision should add. Send it to review; expect revision.","headline":"Solid FPGA engineering with real power/resource numbers, but the cochlea-fidelity claim rests on an approximation with a 25% saturation ceiling and no output-level validation.","tokens_in":6415,"tokens_out":1633,"would_cite":true,"duration_ms":18299,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper shows that a 64-channel CARFAC cochlea model can run in real time on an FPGA at 256 kHz while drawing 3.11 W for the whole board, using only 13.5% of the available hardware resources.","keywords":["CARFAC","cochlea model","FPGA","hardware acceleration","underwater acoustics","real-time processing","time-multiplexing","fixed-point arithmetic"],"falsifier":"Measure the input-output level-compression curves of the FPGA implementation versus the original full-precision CARFAC software across the full dynamic range at 256 kHz. If the output envelope diverges substantially from the software model at high input levels, or if the level-dependent frequency tuning (bandwidth change with input level) fails to reproduce CARFAC's behavior, then the system is a fast filter bank but not a faithful cochlea model, collapsing the acoustic motivation even if the hardware metrics stand.","tokens_in":5450,"feed_emoji":"🐋","tokens_out":3667,"duration_ms":40567,"temperature":0.7,"pith_summary":"The paper is trying to establish that a bio-inspired cochlea model, CARFAC, can be made fast, small, and power-efficient enough to run on an embedded FPGA for underwater acoustic sensing. It claims that by replacing division operations with polynomial approximations, time-multiplexing a single AGC filter, and using pipelined fixed-point arithmetic, a 64-channel CARFAC instance fits in 13.5% of an AMD Kria KV260 SoM and processes a 256 kHz hydrophone input in real time at 3.11 W total board power. If true, this opens the door to multi-hydrophone arrays with adaptive, level-dependent front-end processing on battery-powered underwater vehicles. A sympathetic reader would care because CARFAC preserves temporal fine structure and fast compression that conventional short-time Fourier front ends lack, which could make beamforming and sound classification more robust in noisy, reverberant underwater environments.","feed_headline":"Cochlea model runs 64 channels in real time on 3 watts","feed_subtitle":"FPGA accelerator uses 13.5% of the board, leaving room for seven hydrophone front ends.","key_machinery":"The load-bearing mechanism is the set of division-free nonlinearity approximations combined with a time-multiplexed, pipelined architecture. The DIHC membrane conductance is approximated as $v_{\\mathrm{mem}} = 0.75(1-p)^2$ with a clamped and scaled rectified input $p$, the DOHC compression as $\\mathrm{NLF} = \\max(0, 1 - \\mathrm{sqr}/8)^8$, and the DC gain as a quadratic $g = Au^2 + Bu + C$ with lookup-table coefficients indexed by the undamping factor $u$. These replacements eliminate hardware division, reduce the gain-computation cycle count to one, and use only two DSP slices. The architecture then reuses a single AGC temporal-spatial filter for all channels via time-multiplexing, and uses","core_discovery":"The central claim is that the CARFAC cochlea model can be accelerated on an FPGA without the usual cost centers of division circuits and deep floating-point pipelines. The paper replaces the three division operations with: a squared-polynomial approximation for the DIHC membrane conductance (Eqs 4-6), an eighth-power approximation for the DOHC nonlinearity (Eq 9), and a second-degree polynomial for the DC gain (Eq 12), the last having a maximum error of 0.6%. It then time-multiplexes a single AGC temporal-spatial filter across all channels and distributes the feedback loop across roughly 100 pipeline stages. The result, measured after synthesis on a Kria KV260, is a design that uses at most","pith_inferences":["If the nonlinearity approximations hold up in high-amplitude underwater conditions, the same hardware pattern could replace the short-time Fourier transform front end in MVDR or MUSIC beamformers, since CARFAC provides level-dependent tuning while keeping phase coherence across channels.","The time-multiplexing strategy is not specific to CARFAC: any cascade filter bank whose coefficients and feedback can be stored in BlockRAM and scheduled across channels could benefit from the same single-AGC-filter reuse and division-free polynomial fitting.","A direct A/B validation against the full-precision CARFAC software model on real hydrophone recordings would be the natural test of whether the 0.6% gain error and the early DIHC saturation actually degrade source localization or classification performance in practice, rather than just in isolation.","The reported 13.5% utilization suggests that even higher sampling rates or more channels per instance could be accommodated on the same device, potentially reaching multi-rate or sub-band processing without moving to a larger FPGA."],"forward_implications":["Up to seven 64-channel CARFAC instances can run in parallel on the same KV260 FPGA, providing headroom for a multi-hydrophone array with each hydrophone having its own adaptive cochlea front end.","The whole-board power of 3.11 W is low enough for battery-powered autonomous underwater vehicles, making real-time bio-inspired preprocessing feasible on energy-constrained platforms.","The AXI4-Stream compatible accelerator with DMA transfer and a 100 MHz clock can sustain 256 kHz input in real time with minimal latency, suitable for closed-loop sensing.","The division-free approximations and time-multiplexed AGC design reduce resource usage relative to prior FPGA CARFAC implementations, enabling scaling to higher channel counts or more parallel instances.","Because CARFAC output retains instantaneous phase and fine temporal structure, the accelerator could feed downstream beamforming or learning-based classifiers without a frame-based Fourier transform."],"supporting_citations":[{"why":"Prior FPGA CARFAC implementation whose time-multiplexing design this work builds on and optimizes; the baseline for the claimed scalability improvement.","marker":"[4]"},{"why":"Defines the CARFAC cochlea model that the hardware approximates; supplies the biological mechanism and the original nonlinear functions being replaced.","marker":"[5]"},{"why":"Earlier FPGA CARFAC implementation by the same group, representing the previous resource usage and processing speed that the new design compares against.","marker":"[9]"},{"why":"CARFAC v2 model implementation that adopted the polynomial approximation for the DC gain, providing legitimacy and co-development for the division-free approach.","marker":"[11]"}],"fun_headline_variants":["FPGA cochlea model: 64 channels on 3 watts","Cochlea on FPGA: division-free design cuts power to 3 W","Real-time underwater audio: FPGA cochlea sips 3 W for 64 channels","CARFAC on a chip: AMD FPGA runs 64 cochlea channels at 3 W"],"cache_read_input_tokens":2816,"weakest_assumption_plain":"The load-bearing premise is that the simplified fixed-point approximations still behave like the real CARFAC cochlea model at the high sound levels that matter underwater, since the DIHC and DOHC nonlinearities are only accurate for small basilar-membrane displacement and the DIHC saturates more quickly at high amplitudes.","fun_headline_variants_meta":{"raw":{"variants":["FPGA cochlea model: 64 channels on 3 watts","Cochlea on FPGA: division-free design cuts power to 3 W","Real-time underwater audio: FPGA cochlea sips 3 W for 64 channels","CARFAC on a chip: AMD FPGA runs 64 cochlea channels at 3 W"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000938,"raw_usage":{"total_tokens":3834,"prompt_tokens":717,"completion_tokens":3117,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":461,"completion_tokens_details":{"reasoning_tokens":3030}},"tokens_in":461,"tokens_out":3117,"duration_ms":24575,"temperature":1.0,"reasoning_tokens":3030,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T22:03:00.028459+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the input-output level-compression curves of the FPGA implementation versus the original full-precision CARFAC software across the full dynamic range at 256 kHz. If the output envelope diverges substantially from the software model at high input levels, or if the level-dependent frequency tuning (bandwidth change with input level) fails to reproduce CARFAC's behavior, then the system is a fast filter bank but not a faithful cochlea model, collapsing the acoustic motivation even if the hardware metrics stand.","supporting_citations":[{"cited_title":"A FPGA implementation of the CAR-FAC cochlear model,","cited_arxiv_id":null,"evidence_quote":"Prior FPGA CARFAC implementation whose time-multiplexing design this work builds on and optimizes; the baseline for the claimed scalability improvement."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the CARFAC cochlea model that the hardware approximates; supplies the biological mechanism and the original nonlinear functions being replaced."},{"cited_title":"Electronic cochlea: CAR-FAC model on FPGA,","cited_arxiv_id":null,"evidence_quote":"Earlier FPGA CARFAC implementation by the same group, representing the previous resource usage and processing speed that the new design compares against."},{"cited_title":"The CARFAC v2 cochlear model in Matlab, NumPy, and JAX,","cited_arxiv_id":null,"evidence_quote":"CARFAC v2 model implementation that adopted the polynomial approximation for the DC gain, providing legitimacy and co-development for the division-free approach."}],"review_version":1}