{"id":"80b43a15-a625-40f2-96ab-6eb2bc5134ce","arxiv_id":"2508.13298","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A simulation framework using triple-product error cancellation plus Tikhonov denoising claims to make low-precision RRAMs match high-precision ones on matrix-vector multiplication.","lead":"This paper describes MELISO+, a simulation framework that adds two-stage error correction and MPI-based tiling to RRAM in-memory computing, and claims it cuts arithmetic errors by over 90% while enabling matrices larger than 65,000 by 65,000. If accurate, it would let cheaper, lower-precision RRAM devices reach the accuracy of premium devices, which matters for energy-hungry AI workloads.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"First-order correction as implemented computes A^T x~, not A x~, so the cancellation in Eq. (7) only holds for symmetric matrices; the general-MVM claim is unsubstantiated.","rationale":"The paper's headline claim - that MELISO+ reduces first- and second-order errors by >90% and lets low-precision RRAMs beat EpiRAM for general MVM - depends entirely on the three-product cancellation of Eqs. (4)-(7). The circuit described in Section 2.1 for computing A x~ is not equivalent to the operation in Eq. (4): storing X^T (rows equal to x~^T) and inputting columns of A produces A^T x~, not A x~. For symmetric test matrices (bcsstk02, Iperturb) the distinction vanishes, which is why Table 1 looks plausible. But the framework is advertised as general and is applied in strong scaling to non-symmetric matrices (e.g., add32 with 30.5% numeric symmetry, wang2 with 80.8%); for those, the first-order errors do not cancel and the claimed accuracy cannot be achieved by the specified hardware. The paper also asserts the second-order denoising attenuates residual errors, yet uses lambda=1e-12; since y=(I+lambda*L^T*L)^-1 p is approximately p - 1e-12 * L^T*L*p, that step changes the result by ~1e-12 and cannot attenuate second-order errors of size ~1e-2. Even if the symmetry issue were resolved, the 'two-tier' description overstates the second tier. These are internal correctness risks, not consensus disagreements, and both are testable. I therefore keep a conditional verdict, with the explicit condition that the authors either demonstrate a hardware-realizable A*x~ for non-symmetric matrices (or restrict all claims to symmetric matrices) and re-examine the denoising parameter. Agreement with the reader is partial: the reader flagged ideal reuse of the exact A, and this concern identifies the concrete mechanism by which that idealization breaks outside the symmetric case.","tokens_in":17142,"tokens_out":19696,"duration_ms":197988,"concrete_test":"Implement the Section 2.1 X^T procedure for a random 3x3 non-symmetric A (e.g., [[1,2,3],[4,5,6],[7,8,9]]) and x=[1,2,3], with per-cell multiplicative errors (e.g., 1% Gaussian) on encoded A~ and x~. Compute u from the X^T stage, v = A~x, y = A~x~ (using recorded x~ as input), then p = v + u - y. Compare the relative L2 error of p against the uncorrected A~x. If p's error stays at ~1% (first-order) instead of dropping to ~0.01% (second-order), the described circuit does not cancel first-order errors for non-symmetric A. As a control, repeat with a symmetric A; the cancellation should hold. Also inspect Algorithm 6 line 5: if u = A x~ is computed as an ideal value without simulating the X^T stage, the simulation is not faithful to the proposed hardware.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"Section 2.1 says the A x~ term is obtained by writing X^T (each row = x~^T) into the crossbar and feeding each column a_j of A as an input vector. For a crossbar MVM, output = M * v. With M = X^T and v = a_j, every output row equals x~^T a_j, a single scalar repeated n times; collecting the outputs over j gives the vector A^T x~, not A x~. Equations (4)-(7) instead require the true A multiplied by the noisy x~. For non-symmetric matrices (e.g., add32 with 30.5% numeric symmetry and wang2 with 80.8% in Table 2), the three-term combination becomes A~x + A^T x~ - A~x~; the first-order error (A^T - A)x~ remains, so Eq. (7)'s cancellation does not occur. The only hardware way to get exact A * x~ is to store x~ as a single column and sequentially input rows of A (m dot products), which is not the described X^T construction and is not accounted for in the energy/latency metrics. Thus the claimed >90% error reduction and the strong-scaling results on non-symmetric matrices rest on an ideal, non-realizable A*x~ term or on an unstated symmetry restriction.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces MELISO+, a full-stack simulation and benchmarking framework for RRAM-based in-memory computing. Its two main contributions are a two-tier error-correction scheme (a first-order cancellation that combines three matrix-vector products, followed by a regularized least-squares denoising step) and a distributed/virtualized execution backend that reportedly scales to matrices over 65,000x65,000. The manuscript claims over 90% reduction of arithmetic errors, three-to-five orders of magnitude energy improvement, and a 100-fold latency reduction, and that lower-precision RRAM devices (e.g., TaOx-HfOx) can thus outperform higher-precision devices such as EpiRAM. These claims are evaluated through simulations on four device types and several SuiteSparse matrices.","tokens_in":17461,"tokens_out":7091,"duration_ms":68371,"significance":"If the central claims are correct, MELISO+ would be a significant contribution: the first-order cancellation is parameter-free under the stated multiplicative error model, the distributed/virtualized MVM approach addresses a real scalability bottleneck, and the comparison of multiple RRAM device types with a public benchmark pipeline could be broadly useful. The manuscript also ships a complete simulator with MPI support, which is a concrete strength. However, the error-cancellation claim is load-bearing and is not established for general matrices under the described circuit-level implementation, and the energy/latency comparisons omit significant overheads; these issues currently prevent the paper from fully supporting its headline claims.","major_comments":[{"comment":"The energy and latency metrics Ew and Lw are write-only metrics, but the error-correction procedure requires three MVM passes (A tilde{x}, tilde{A} x, tilde{A} tilde{x}), the construction and row-wise readout of the n x n matrix X^T, and an additional denoising MVM with (I + lambda L^T L)^{-1}. None of these overheads, nor read/ADC costs, appear to be included in the reported Ew and Lw. As a result, the claimed three-to-five orders of magnitude energy reduction and 100-fold latency reduction relative to EpiRAM are not justified by the data presented. The comparison should be end-to-end, including all extra writes, reads, and arithmetic operations introduced by the correction scheme.","section":"Sections 2.2 and 4.2"}],"minor_comments":[{"comment":"The normalization factor for virtualization (the dashed lines in Fig. 5) is described only qualitatively. Please provide the exact formula used for the normalization and state it in the caption or Methods.","section":"Section 2.3.2 / Fig. 5"}],"recommendation":"major_revision","confidential_remarks":"The paper is likely from a cross-disciplinary group, and the central algebraic idea is appealing under the stated multiplicative error model. However, the circuit-level mapping issue in Section 2.1 is fundamental: if the described X^T construction is indeed what is simulated, then all non-symmetric large-scale results (add32, wang2, etc.) are based on a term that does not cancel as claimed. Please ask the authors to clarify the exact hardware mapping used in the simulator and to re-run or re-report the affected experiments. Also, the energy/latency comparisons should be scrutinized for completeness; the current write-only metrics likely overstate the benefits. The paper is salvageable, but the revisions needed are substantial."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The paper has a specific algebraic claim about cancelling device errors in RRAM MVM, but the described hardware implementation actually computes A^T x~ where it needs A x~. The cancellation in Eq. (7) only holds for symmetric matrices, and the paper never states that restriction. That undercuts the headline “over 90%” error reduction for the non-symmetric test matrices (add32 with 30.5% numeric symmetry, wang2 with 80.8%).\n\nWhat is genuinely new: the combination of triple-product first-order cancellation, a Tikhonov denoising step, and an MPI-based virtualized tiling framework for RRAM MVM. The framework itself, built on NeuroSim+ with four device models, is a useful benchmarking contribution for in-memory computing. The algebra in Eqs. (4)–(7) is correct under the stated multiplicative error model, and the write-and-verify procedure is clearly specified. The scaling to 65k×65k matrices in simulation, with weak/strong scaling analysis, is a legitimate engineering demonstration.\n\nThe soft spots are serious. The implementation description for computing A~x is wrong: storing X^T with rows x~^T and inputting columns of A gives A^T x~, not A x~. For symmetric matrices the two coincide, but the experiments on add32 and wang2 do not qualify. Also, the “over 90%” claim is contradicted by the M2 rows of Table 1, where reductions range from 61% to 85%. Energy and latency numbers are write-only, which overstates the benefit. The regularization parameter λ=10^−12 is chosen post hoc on the same matrices, and no code or artifacts are released.\n\nIf the authors either fix the implementation to compute the actual A x~ or clearly restrict the claims to symmetric matrices, the framework and benchmarks could be solid. As written, the central claim is not supported. Still, the paper deserves a serious referee: the distributed framework has independent value, and the error-cancellation idea is worth pursuing. I would send it to review with a clear expectation of major revision.","headline":"Clever error-cancellation scheme and a useful RRAM simulation framework, but the described implementation computes A^T x~ instead of A x~, so the headline error-reduction claims only hold for symmetric matrices.","tokens_in":17965,"tokens_out":5903,"would_cite":false,"duration_ms":54378,"reading_group":"maybe","serious_thinker":"no","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Two-tier error correction in the MELISO+ framework cancels first-order RRAM programming errors algebraically and denoises the residual, cutting arithmetic errors by over 90% and letting low-precision RRAM arrays outperform high-precision…","keywords":["in-memory computing","RRAM","resistive random access memory","matrix-vector multiplication","error correction","distributed computing","write-and-verify","analog crossbar arrays"],"falsifier":"Program a real RRAM crossbar with a known matrix and vector, then read the same programmed array several times without reprogramming and compute the three products needed for $p$; if the residual after forming $p$ does not fall by roughly 90% relative to a naive $Ax$ product, or if errors do not follow the multiplicative form $\\tilde A = A(1+\\epsilon_A)$, the central claim is falsified. A simulation that injects additive or state-dependent noise instead of multiplicative noise should show the same failure.","tokens_in":16996,"feed_emoji":"⚡","tokens_out":10985,"duration_ms":105121,"temperature":0.7,"pith_summary":"This paper introduces MELISO+, a full-stack framework for matrix-vector multiplication on RRAM in-memory hardware, and claims it removes the two obstacles that have kept such hardware from wide use: device variability and small array sizes. Its two-tier error correction cancels first-order programming errors algebraically and then denoises what remains, reducing arithmetic errors by more than 90% across several RRAM material systems. With that correction, low-precision, low-latency devices such as TaOx-HfOx can match the accuracy of the high-precision benchmark device while consuming three to five orders of magnitude less energy and running about 100 times faster. A distributed backend partitions large matrices and vectors row-wise across a multi-array cluster with a virtualization layer, letting fixed-size crossbars compute on matrices larger than 65,000 by 65,000. If these claims hold, RRAM memory arrays become a practical, energy-efficient substrate for the large matrix workloads behind modern AI.","feed_headline":"Two-tier fix cuts RRAM math errors by over 90%","feed_subtitle":"Lower-precision RRAM arrays could match high-accuracy chips with far less energy and latency.","key_machinery":"The load-bearing object is the algebraic cancellation identity $p = \\tilde{A}x + A\\tilde{x} - \\tilde{A}\\tilde{x} = Ax(1-\\epsilon_A\\epsilon_x)$, which holds when programming errors are multiplicative and stable. The vector $x$ is first written as repeated rows of a matrix $X^\\top$ so that the three required products can be generated on the same array; reading them out and combining them removes the first-order error. The second stage is a regularized least-squares denoiser $y(\\lambda) = (I_n + \\lambda L^\\top L)^{-1}p$, where $L$ is the first-order difference matrix, used to attenuate the remaining second-order term. The scalability claim is carried by a distributed mechanism: the matrix and vector are partitioned row-wise into chunks for individual crossbar arrays, coordinated through the Message Passing Interface (MPI), and a virtualization layer zero-pads dimensions and serially maps sub-blocks onto fixed-size arrays.","core_discovery":"On the paper's own terms, the central discovery is that the dominant programming error of an RRAM crossbar can be cancelled in software without changing the device. If encoding $A$ and $x$ as conductances introduces multiplicative perturbations, $\\tilde A = A(1+\\epsilon_A)$ and $\\tilde x = x(1+\\epsilon_x)$, then computing the three products $\\tilde Ax$, $A\\tilde x$, and $\\tilde A\\tilde x$ and forming $p = \\tilde Ax + A\\tilde x - \\tilde A\\tilde x$ yields $p = Ax(1-\\epsilon_A\\epsilon_x)$; every first-order error term is gone, leaving only the product of two small errors. The paper then applies a regularized least-squares denoiser, $y(\\lambda) = (I_n + \\lambda L^\\top L)^{-1}p$ with $L$ the first-order difference matrix and $\\lambda = 10^{-12}$, to suppress that second-order residual. On the scaling side, the paper shows that a fixed array of crossbars, with row-wise partitioning governed by MPI and a virtualization layer that serializes and zero-pads sub-blocks, can carry out reliable matrix-vector multiplication at dimensions beyond $65{,}000 \\times 65{,}000$ with roughly linear memory and runtime scaling.","pith_inferences":["Because the cancellation identity assumes stable multiplicative errors, its 90% figure should not be expected to survive in the presence of additive read noise, analogue-to-digital conversion error, or drift between the three passes; those effects would require a third correction tier.","The regularized denoiser assumes the true output vector is smooth in its index order; for matrices whose outputs are not ordered smoothly, the second-stage gain is untested, so the error reduction may be smaller on arbitrary matrix layouts.","A direct extension would be to run the same two-tier scheme on error models with state-dependent or nonlinear programming errors; the gap between observed and claimed error reduction would quantify how much of the result depends on the multiplicative perturbation assumption.","The framework supplies a concrete systems argument for using cheap, low-precision RRAM crossbars in AI inference, where the workload is dominated by large matrix-vector products, rather than reserving in-memory computing for small demonstrations."],"forward_implications":["Lower-precision RRAM devices such as TaOx-HfOx can reach the accuracy of high-precision benchmark devices in matrix-vector multiplication, with the paper reporting 3-5 orders of magnitude lower write energy and roughly two orders lower write latency.","A fixed physical configuration of RRAM crossbars can process matrices far larger than its own footprint, with the paper demonstrating reliable computation at matrix sizes up to at least 65,025 by 65,025.","Because the two-tier correction is formulated from the algebra of the MVM itself, the paper argues it transfers across device material systems and error models without per-device retuning.","Combining write-and-verify iteration with error correction lets accuracy stabilize at small iteration counts, so the correction overhead does not erase the device's speed advantage.","The distributed and virtualized scheme gives roughly linear scaling of memory and runtime with problem size, making RRAM-based MVM practical for high-dimensional workloads."],"supporting_citations":[{"why":"the earlier MELISO benchmarking platform that MELISO+ extends with error correction and distribution","marker":"[5]"},{"why":"the device-to-array simulator used to emulate MVM execution and report energy and latency metrics","marker":"[32]"},{"why":"the closed-loop write-and-verify protocol used to encode matrices and vectors within tolerance","marker":"[33]"},{"why":"the high-accuracy EpiRAM benchmark device that lower-precision devices are compared against","marker":"[31]"},{"why":"the TaOx-HfOx device data used to demonstrate accuracy parity with large energy and latency savings","marker":"[30]"},{"why":"the AlOx-HfO2 bilayer device data used as another lower-precision RRAM under test","marker":"[29]"},{"why":"the Ag-aSi device data that exercises the correction under strongly nonlinear weight-update behaviour","marker":"[34]"},{"why":"the SuiteSparse matrix collection that supplies the test matrices for accuracy and scaling experiments","marker":"[35]"},{"why":"the least-squares denoising formulation the second-order correction stage is built on","marker":"[38]"},{"why":"the MPI implementation used to coordinate the distributed multi-array computation","marker":"[36]"}],"fun_headline_variants":["Error-cancelling math lets low-precision RRAM outperform high-end chips","90% error cut in RRAM via two-tier software fix scales to 65k","Distributed RRAM computing: 90% less error, 100x faster","Software trick cancels RRAM noise, enables 65k-dim computations"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The error reduction depends on each RRAM programming error being a small percentage error that stays identical every time the encoded matrix or vector is reused; if device noise is nonlinear, changes between reads, or includes read-out and conversion noise, the cancellation in Equation (7) breaks down.","fun_headline_variants_meta":{"raw":{"variants":["Error-cancelling math lets low-precision RRAM outperform high-end chips","90% error cut in RRAM via two-tier software fix scales to 65k","Distributed RRAM computing: 90% less error, 100x faster","Software trick cancels RRAM noise, enables 65k-dim computations"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001403,"raw_usage":{"total_tokens":5719,"prompt_tokens":1038,"completion_tokens":4681,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":654,"completion_tokens_details":{"reasoning_tokens":4596}},"tokens_in":654,"tokens_out":4681,"duration_ms":37230,"temperature":1.0,"reasoning_tokens":4596,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T17:15:39.009087+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Program a real RRAM crossbar with a known matrix and vector, then read the same programmed array several times without reprogramming and compute the three products needed for $p$; if the residual after forming $p$ does not fall by roughly 90% relative to a naive $Ax$ product, or if errors do not follow the multiplicative form $\\tilde A = A(1+\\epsilon_A)$, the central claim is falsified. A simulation that injects additive or state-dependent noise instead of multiplicative noise should show the same failure.","supporting_citations":[{"cited_title":"Nature materials17(4), 335–340 (2018) https://doi.org/10.1038/s41563-017-0001-5","cited_arxiv_id":null,"evidence_quote":"the high-accuracy EpiRAM benchmark device that lower-precision devices are compared against"},{"cited_title":"In: 2018 IEEE Symposium on VLSI Technology, pp","cited_arxiv_id":null,"evidence_quote":"the TaOx-HfOx device data used to demonstrate accuracy parity with large energy and latency savings"},{"cited_title":"IEEE Electron Device Letters 37(8), 994–997 (2016) https://doi.org/10.1109/LED.2016.2582859","cited_arxiv_id":null,"evidence_quote":"the AlOx-HfO2 bilayer device data used as another lower-precision RRAM under test"},{"cited_title":"Journal of Open Source Software4(35), 1244 (2019) https://doi.org/10.21105/ joss.01244","cited_arxiv_id":null,"evidence_quote":"the SuiteSparse matrix collection that supplies the test matrices for accuracy and scaling experiments"},{"cited_title":"Connexions4, 1–25 (2013)","cited_arxiv_id":null,"evidence_quote":"the least-squares denoising formulation the second-order correction stage is built on"},{"cited_title":"In: Recent 22 Advances in Parallel Virtual Machine and Message Passing Interface: 11th Euro- pean PVM/MPI Users’ Group Meeting Budapest, Hungary, September 19-22,","cited_arxiv_id":null,"evidence_quote":"the MPI implementation used to coordinate the distributed multi-array computation"}],"review_version":2}