{"id":"784f6d49-35e4-46b7-b36d-50b5617d0b5f","arxiv_id":"2508.13840","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"The Sophon SG2044 RISC-V CPU outperforms the SG2042 by up to 4.91x on 64 cores, mainly through improved memory bandwidth and RVV 1.0 vectorization, narrowing the HPC performance gap.","lead":"This paper benchmarks a new 64-core RISC-V server chip, the Sophon SG2044, against its predecessor and common HPC CPUs using the NAS Parallel Benchmarks. It finds the chip scales well at high core counts, up to 4.91 times faster than the older SG2042, and closes much of the gap with x86 and Arm for compute-heavy work.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Uncontrolled compiler generations across platforms inflate SG2044 speedups; paper's claim that GCC 8.4 was fastest on SG2042 is unsubstantiated.","rationale":"The reader's weakest assumption is precisely the most load-bearing concern I identified: the SG2044 vs SG2042 comparisons use different compiler generations (GCC v15.2 vs T-Head GCC v8.4), and the paper's own sensitivity analysis shows compiler version can change SG2044 performance by 35% for IS and 8.6% for FT at 64 cores. The paper asserts that GCC 8.4 was fastest for the SG2042 but provides no numerical evidence; this unsupported claim is in Section 4 and must be flagged. If a modern compiler improves the SG2042 by a similar margin, the headline 4.91× speedup shrinks and the memory-subsystem interpretation weakens. The reader's conditional verdict is appropriate; my concern does not change that verdict, but it reinforces the need for a common-toolchain comparison and public raw data. The proposed test directly addresses whether the compiler effect is real and material.","tokens_in":11450,"tokens_out":5110,"duration_ms":49475,"concrete_test":"Re-run NPB class C OpenMP benchmarks on the SG2042 at 64 cores using GCC v15.2 (or LLVM) with -O3, exactly as done for the SG2044, and compute the SG2044/SG2042 speedup ratios in Table 4. If the IS ratio drops from 4.91 to below ~3.9 (i.e., >20% SG2042 improvement), the compiler version is a major confound; if the ratios remain above 4.5, the concern is resolved.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central quantitative claim—the SG2044 delivering up to 4.91× the SG2042's performance over 64 cores—rests on a cross-generation compiler comparison that is not controlled. Section 4 states that for the SG2042, T-Head's fork of GCC v8.4 was 'consistently the best' after experimenting with 'different versions of the compiler, including GCC v15.2', but no data for that experiment are shown. Meanwhile, Section 6 reports that on the SG2044, GCC v15.2 vs v12.3.1 improves IS by 35% at 64 cores (Table 8) and FT by 8.6%, and the SG2044's vectorisation is disabled for CG. If a modern compiler gave the SG2042 even a fraction of that improvement, the IS speedup of 4.91× (Table 4) would shrink materially, and the memory-subsystem attribution would be weakened. The reader's verdict correctly identifies this as a measurement-attribution gap; without the SG2042 compiler experiment data or a common-toolchain rerun, the headline ratio cannot be trusted.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents the first HPC-oriented performance evaluation of the Sophon SG2044, a 64-core RISC-V processor. Using the NAS Parallel Benchmark suite (OpenMP version, class B/C), it compares the SG2044 against the SG2042, several smaller RISC-V systems, and x86/Arm HPC CPUs (AMD EPYC 7742, Intel Skylake 8170, Marvell ThunderX2). It reports that the SG2044 outperforms the SG2042 by up to 4.91x on 64 cores (IS kernel, Table 4), attributes this to an improved memory subsystem and RVV v1.0 support, and uses STREAM to show that memory bandwidth scales beyond 8 cores on the SG2044 while it plateaus on the SG2042. A final section studies compiler version and vectorisation effects, including a documented anomaly where vectorisation hurts the CG kernel.","tokens_in":11737,"tokens_out":3893,"duration_ms":40500,"significance":"If the results are robust, this is a valuable and timely data point: the SG2044 appears to be the first commodity 64-core RISC-V CPU on which mainline compiler auto-vectorization works and on which memory-bound NPB kernels continue to scale across all cores. The paper's strengths are its direct measurements, use of unmodified benchmark code, the independent STREAM scaling evidence, and the honest reporting of the CG vectorisation anomaly. The evaluation is more thorough than a simple 'look, it boots' paper and will be useful to the HPC and RISC-V communities as an early characterisation of this processor. The central claims are, however, weakened by uncontrolled cross-compiler comparisons and a lack of clock normalization, as detailed below.","major_comments":[{"comment":"The headline multi-core speedup of the SG2044 over the SG2042 (up to 4.91x for IS, Table 4) is measured with different compilers on the two CPUs: T-Head's fork of GCC v8.4 for the SG2042, GCC v15.2 for the SG2044. The text states that v8.4 was 'consistently the best' among versions tried on the SG2042, but no data for that sweep are shown. This is load-bearing because Section 6 shows that on the SG2044, moving from GCC v12.3.1 to v15.2 alone improves IS by about 35% at 64 cores (2255.72 to 3038.14 Mop/s, Table 8). If a modern compiler similarly improves the SG2042, the reported ratios, and particularly the memory-subsystem attribution, would shrink. Please provide the compiler sweep data for the SG2042 or re-run the SG2042 comparison with a common toolchain; without this, the 4.91x figure is not substantiated.","section":null},{"comment":"Clock frequency is not normalized when comparing the SG2044 (2.6 GHz in the test system) with the SG2042 (2.0 GHz). The single-core improvement for the compute-bound EP kernel is 1.30x, which is exactly the frequency ratio (2.6/2.0). The paper attributes EP's benefit to RVV v1.0 and memory performance ('this is potentially due to the C920v2 providing RVV v1.0 along with the memory performance to keep the vector unit fed'), but the data are equally or more consistent with a pure clock-speed effect. Please report per-GHz or otherwise normalized figures for single-core comparisons, or explicitly discuss this confound. The multi-core comparison is less severely affected, but the 'compute-bound' attribution in the conclusions is not supported without normalization.","section":null},{"comment":"No error bars or variance information are reported. Section 5 states that 'all results represent the average of five independent runs', but no standard deviations, ranges, or per-run values are given anywhere, and Section 4 does not even state the number of runs. For a benchmark paper whose conclusions depend on differences such as 1.08x (IS single-core) and 2.20x (CG multi-core), the absence of variability information makes it impossible to judge whether these ratios are within run-to-run noise. Please add error bars or at least report the spread for the key SG2044-vs-SG2042 comparisons in Tables 3 and 4.","section":null}],"minor_comments":[{"comment":"The phrase 'delivering up to 4.91 greater performance' should read '4.91 times greater' or '4.91x'.","section":null},{"comment":"Typo: 'Since it's release in 2023' should be 'Since its release in 2023'.","section":null},{"comment":"Typo: 'agsinst' should be 'against'.","section":null},{"comment":"The entry 'DNR' for the AllWinner D1 FT benchmark is undefined. If it means 'did not run', please state so in the caption or text.","section":null},{"comment":"The thread-placement experiment with OMP_PROC_BIND/OMP_PLACES is described only qualitatively ('consistently the best performance was obtained by either leaving these environment variables unset...'). This would be more convincing with a small table or a sentence quantifying the impact.","section":null},{"comment":"Reference [10] is titled 'SG2042 Empowering RISC-V in High-Performance Computing' but is cited to support claims about SG2044 promises; please clarify the source or use a more directly relevant reference if available.","section":null}],"recommendation":"major_revision","confidential_remarks":"The paper is a single-author system evaluation. The central concern is not the novelty but the rigor of the measurement-attribution: the SG2042 compiler choice is unsubstantiated, clock frequencies are not normalized, and no error bars are provided. These are fixable within the manuscript's scope (add a compiler sweep table, per-GHz normalization or a caveat, and variance information), so I recommend major revision rather than reject. The author's heavy reliance on prior SG2042 papers is appropriate for background, but the 'consistently best' compiler claim must be evidenced. The CG vectorisation anomaly is a strong point and should be kept."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Nick Brown has done the first published HPC-style benchmark study of SOPHGO's SG2044. That alone is the main novelty: a 64-core RISC-V server chip with RVV 1.0, previously uncharacterized in the HPC literature. The central qualitative result, that the SG2044's advantage over the SG2042 appears only at high core counts, is well supported by the NPB scaling plots and independently by the STREAM bandwidth curves. The compute-bound EP numbers are genuinely interesting, with the SG2044 tracking the Skylake core-for-core.\n\nThe soft spots are real and the stress-test has the right target. The 4.91x IS speedup is GCC 15.2 on the SG2044 against T-Head GCC 8.4 on the SG2042. The paper asserts that 8.4 was consistently best but presents no data from that compiler sweep. Given the paper's own Table 8 shows IS improving by 35% between GCC 12.3.1 and 15.2 on the SG2044, the across-generation comparison can easily shift the headline by tens of percent. The cross-ISA comparisons in Section 5 mix GCC 11.2, 8.4, 9.2, and 15.2, so the relative positions are approximate. There are also no error bars and no raw data. These are measurement-attribution weaknesses, not signs of fabrication: the STREAM scaling and the multi-core curves point consistently in the same direction.\n\nThe paper is honest about its own limitations, including the CG vectorisation anomaly, and the citation pattern is fair. It leans on the author's earlier SG2042 work, which is exactly the relevant baseline. The remaining gaps are that this is one chip, one benchmark suite, and one benchmark generation, and the compiler question is not resolved.\n\nWho should read it: anyone considering SG2044 hardware for compute workloads and anyone tracking RISC-V readiness. It deserves a serious referee. My recommendation: send it out, and ask for either the SG2042 compiler-sweep data, a common-toolchain rerun of the headline comparisons, or a carefully hedged abstract that presents the ratios as compiler-dependent. With that fix it becomes a solid reference point.","headline":"First useful NPB data for the SG2044; the multi-core and memory story is credible, but the headline speedups over the SG2042 are compiler-dependent and need a controlled rerun before being used for procurement decisions.","tokens_in":12168,"tokens_out":4523,"would_cite":true,"duration_ms":48392,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The Sophon SG2044's memory and vector upgrades let RISC-V scale to 64 cores, outrunning its predecessor by up to 4.91x and closing the HPC gap on compute-bound kernels.","keywords":["RISC-V","High Performance Computing","Sophon SG2044","NAS Parallel Benchmarks","RVV v1.0 vectorisation","memory bandwidth","SG2042","OpenMP scaling"],"falsifier":"Re-run the 64-core NPB class C IS and MG comparisons and the STREAM copy benchmark on the SG2042 with the same GCC 15.2 used on the SG2044 (or vice versa); if the SG2044's 4.91x IS advantage and threefold bandwidth advantage shrink substantially, the attribution to the SG2044's memory subsystem is wrong.","tokens_in":11371,"feed_emoji":"🖥️","tokens_out":6466,"duration_ms":58430,"temperature":0.7,"pith_summary":"This paper is the first HPC-focused performance study of SOPHGO's Sophon SG2044, a 64-core RISC-V CPU aimed at workstation and server workloads. The author's central claim is that the SG2044's upgraded memory subsystem and RVV v1.0 vector support remove the bottlenecks that limited its predecessor, the SG2042, so the chip is most advantageous at high core counts: across 64 cores it delivers up to 4.91 times the performance of the SG2042, with the memory-latency-bound IS kernel benefiting most. A single C920v2 core beats all other commodity RISC-V cores tested, and on compute-bound EP the SG2044 tracks an Intel Skylake core-for-core while scaling like an AMD EPYC at high thread counts. If correct, this means RISC-V is no longer confined to embedded use: mainline GCC can auto-vectorize code and the memory subsystem can feed 64 cores, making RISC-V a credible contender for at least compute-bound HPC workloads.","feed_headline":"64-core RISC-V chip scales past its predecessor by 4.91x","feed_subtitle":"First NPB study of SOPHGO's SG2044 shows memory and vector upgrades make RISC-V competitive for compute-bound HPC.","key_machinery":"The load-bearing object is the SG2044's memory subsystem redesign plus the RVV v1.0 vector unit in each C920v2 core. The CPU keeps 64 T-Head cores in clusters of four, but replaces the SG2042's 4 memory controllers/channels with 32, moves to DDR5-4266, doubles per-cluster L2 to 2MB, and puts all cores in one NUMA region. This is what lets memory-bandwidth-bound kernels keep scaling past 8 threads; the RVV v1.0 support is what lets a stock compiler (GCC 15.2) generate vector code, which is what makes the single-core compute-bound EP result competitive. The STREAM copy kernel is the direct probe of the memory claim, and the NPB kernels are the workloads that demonstrate the end-to-end effect.","core_discovery":"On the paper's own terms, the discovery is that the SG2044 turns RISC-V from a CPU that peaks early into one that keeps scaling: the STREAM copy benchmark shows bandwidth on the SG2042 plateauing after 8 cores while the SG2044 continues rising to over three times the SG2042's 64-core bandwidth. With 32 memory controllers and channels, DDR5-4266, and a single NUMA domain, all 64 T-Head C920v2 cores can be fed, so memory-bound NPB kernels (IS, MG, CG, FT) that stalled on the SG2042 now run 2.2 to 4.91 times faster at full occupancy. The other half is RVV v1.0, which lets unmodified mainline GCC v15.2 auto-vectorize code; on the compute-bound EP kernel the SG2044 matches a Skylake core-for-core","pith_inferences":["Because the SG2044 uses the same C920 core family as the SG2042, most of the multi-core win is attributed to the memory subsystem; a future RISC-V server chip pairing a stronger core with similar memory could close the remaining per-core gap with x86 and Arm.","The CG vectorization slowdown (vectorised binary about three times slower) looks like a compiler autovectorization pathology rather than a hardware limit; it offers a concrete target for tuning GCC and LLVM's RISC-V vector code generation and could become a regression test.","The comparison assumes each platform's chosen compiler is representative; re-running the SG2042 with GCC 15.2, or the x86 and Arm systems with their best compilers, would test whether the reported ratios are hardware or toolchain effects.","The single-NUMA, 32-channel design suggests the SG2044 may behave more predictably than multi-socket x86 nodes for OpenMP because there is no remote NUMA penalty, though the paper does not make this claim."],"forward_implications":["The SG2044 is the first commodity 64-core RISC-V CPU shown to scale on memory-bound NPB kernels (IS, MG, CG, FT) across all 64 cores, not just compute-bound ones.","Mainline GCC v15.2 can auto-vectorize HPC code targeting RISC-V, so the software stack no longer depends on vendor forks of GCC.","At full CPU occupancy the SG2044 is competitive with an Intel Skylake and an AMD EPYC on compute-bound EP, and comparable to Skylake and ThunderX2 on MG when comparing full CPUs.","At low core counts the gap with x86 and Arm remains significant, so HPC users on the SG2044 should run whole-node to get the benefit.","SOPHGO's claimed roughly threefold memory bandwidth improvement is confirmed by STREAM at 64 cores, aligning with the 4.91x IS improvement."],"supporting_citations":[{"why":"Prior SG2042 NPB characterisation; establishes the memory bottleneck and supplies the profiling methodology and baseline SG2042 results.","marker":"[3]"},{"why":"Earlier SG2042 evaluation whose single-core RISC-V comparisons and scaling observations the paper extends to the SG2044.","marker":"[4]"},{"why":"Supplies the OpenMP implementation of the NAS Parallel Benchmarks used for all benchmark runs.","marker":"[6]"},{"why":"SOPHGO announcement promising roughly a threefold DDR bandwidth increase on the SG2044; the paper's STREAM and NPB results test this claim.","marker":"[10]"},{"why":"SOPHGO documentation for SG2044 configuration (core count, caches, clock); grounds the hardware description.","marker":"[11]"},{"why":"Same-version Geekbench comparison of SG2044 and SG2042; provides independent prior evidence that the multi-core advantage is around 1.3 times.","marker":"[13]"},{"why":"Earlier multi-socket RISC-V investigation identifying memory as one of the primary bottlenecks in the SG2042; motivates the memory focus.","marker":"[2]"}],"fun_headline_variants":["SG2044: RISC-V scales to 64 cores, beats SG2042 by 4.91x","RISC-V's SG2044 closes HPC gap with 64-core memory scaling","SG2044's RVV v1.0 and memory upgrades triple bandwidth","SG2044 matches Skylake per core, scales past SG2042","From plateau to peak: SG2044 keeps scaling past 8 cores"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The comparison assumes each platform's chosen compiler is representative: the SG2044 runs GCC 15.2, the SG2042 runs T-Head GCC 8.4, and the x86 and Arm systems run GCC 11.2, 8.4, or 9.2, so if a different compiler changed any machine's score by 20 to 30 percent the reported speedup ratios would shift.","fun_headline_variants_meta":{"raw":{"variants":["SG2044: RISC-V scales to 64 cores, beats SG2042 by 4.91x","RISC-V's SG2044 closes HPC gap with 64-core memory scaling","SG2044's RVV v1.0 and memory upgrades triple bandwidth","SG2044 matches Skylake per core, scales past SG2042","From plateau to peak: SG2044 keeps scaling past 8 cores"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000338,"raw_usage":{"total_tokens":1717,"prompt_tokens":770,"completion_tokens":947,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":514,"completion_tokens_details":{"reasoning_tokens":837}},"tokens_in":514,"tokens_out":947,"duration_ms":9373,"temperature":1.0,"reasoning_tokens":837,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T18:51:36.902774+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-run the 64-core NPB class C IS and MG comparisons and the STREAM copy benchmark on the SG2042 with the same GCC 15.2 used on the SG2044 (or vice versa); if the SG2044's 4.91x IS advantage and threefold bandwidth advantage shrink substantially, the attribution to the SG2044's memory subsystem is wrong.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Prior SG2042 NPB characterisation; establishes the memory bottleneck and supplies the profiling methodology and baseline SG2042 results."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Earlier SG2042 evaluation whose single-core RISC-V comparisons and scaling observations the paper extends to the SG2044."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the OpenMP implementation of the NAS Parallel Benchmarks used for all benchmark runs."},{"cited_title":"SG2042 Empowering RISC-V in High-Performance Computing","cited_arxiv_id":null,"evidence_quote":"SOPHGO announcement promising roughly a threefold DDR bandwidth increase on the SG2044; the paper's STREAM and NPB results test this claim."},{"cited_title":"Sophgo-doc: SG2044","cited_arxiv_id":null,"evidence_quote":"SOPHGO documentation for SG2044 configuration (core count, caches, clock); grounds the hardware description."},{"cited_title":"Geekbench: SOPHGO SG2044 RISC-V vs Milk-V Pioneer","cited_arxiv_id":null,"evidence_quote":"Same-version Geekbench comparison of SG2044 and SG2042; provides independent prior evidence that the multi-core advantage is around 1.3 times."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Earlier multi-socket RISC-V investigation identifying memory as one of the primary bottlenecks in the SG2042; motivates the memory focus."}],"review_version":1}