{"id":"18254fbf-94a9-4c84-a5ce-2ec0f81914e9","arxiv_id":"2508.16868","paper_version":1,"verdict":"UNVERDICTED","confidence":"LOW","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"An attacker can accelerate NBTI aging on a specific processor path to produce silent, targeted data corruption in a co-running victim application.","lead":"This paper describes a software-only attack that deliberately ages a specific circuit path inside a processor, causing a targeted bit to flip in a victim program. If it works, it adds a new threat model to shared computing hardware.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Abstract reports >7x wear but does not establish that the wear actually produced an observed silent bit flip; if the corruption is only inferred from an aging model, the central attack claim is unsupported.","rationale":"The reader's verdict is UNVERDICTED because only the abstract is available; my concern is consistent with that but focuses on a more specific logical gap: the abstract's evidence for increased wear does not by itself prove the claimed silent data corruption. This is the single most load-bearing assumption because the attack's impact depends on the corruption actually occurring, not merely on accelerated aging. The reader's weakest assumption addresses attacker control and victim scheduling, which is a necessary condition but downstream of the wear-to-fault linkage. My proposed test would settle whether the case study contains empirical evidence of corruption or only an extrapolated prediction. Since the full text is not available, I cannot determine whether the concern lands; the correct verdict remains UNVERDICTED, and no verdict change is warranted. I agree only partially with the reader because we identify different weak points, though both point to the need for full experimental details.","tokens_in":717,"tokens_out":2700,"duration_ms":38275,"concrete_test":"Obtain the full text and locate the case-study demonstration of silent data corruption. Determine whether the victim bit flip was measured on real silicon, emulated on an FPGA with controllable delay, or predicted by an aging simulation. If it was simulated, reproduce the timing check: compare the post-aging path delay (with the claimed >7x wear applied to the targeted transistors) against the pipeline stage's setup-time slack under the same voltage/frequency used for the victim workload. If the delayed arrival time does not exceed the clock period minus setup time, no timing fault can occur. Also check whether the reported corrupted value is repeatable across multiple runs and input seeds, and whether any ECC/parity or architectural detection would catch it.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim has two links: (1) a software-only attacker can deliberately increase NBTI wear by >7x on a targeted functional-unit path, and (2) this wear causes a targeted, silent incorrect calculation in a co-running victim. The abstract directly supports only the first link; for the second it says an attacker 'could leverage such an attack, leading to targeted and silent data corruption,' without stating that corruption was actually observed. The weakest load-bearing point is the causal chain from wear to silent bit flip. NBTI primarily increases transistor threshold voltage and path delay; it does not directly produce a stuck bit. To get silent data corruption, the aged path delay must exceed the available timing margin under the victim's actual voltage/frequency/temperature conditions, the resulting timing error must not trigger detection mechanisms, and the victim must exercise the same path at the critical moment. The abstract gives no information about whether the demonstration used a fabricated chip, an FPGA with injected delay, or a gate-level/SPICE aging simulation. If the 'silent data corruption' is extrapolated from a wear model rather than observed in a running system, the attack remains a plausible hypothesis, not a demonstrated one. This is not an accusation of inconsistency; it is a gap between the headline claim and the available evidence.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript (arXiv:2508.16868), available here only as an abstract, describes a software-only fault-injection attack called a Targeted Wearout Attack. The authors claim that by executing a carefully crafted user-privilege program, an attacker can exploit the input dependence of Negative-Bias Temperature Instability (NBTI) to accelerate aging of a specific logic path in a microprocessor functional unit. As a case study, they report a >7x increase in wear on a targeted path in a RISC-V fused multiply-add (FMA) pipeline compared with typical workloads, and state that an attacker could leverage this degradation to cause targeted and silent data corruption in a co-running victim application. The central claim is that such aging-induced wear can be deliberately steered and then exploited to produce a specific incorrect calculation.","tokens_in":1022,"tokens_out":1870,"duration_ms":24570,"significance":"If the full evidence supports the abstract's claims, this is a novel and potentially important result: it identifies a new class of microarchitectural fault-injection attacks that require only user privilege and exploit a physical aging mechanism rather than a conventional software or hardware vulnerability. The concrete RISC-V FMA case study, with a reported >7x wear increase, is a useful proof-of-concept if the measurement methodology is sound. However, the abstract alone does not establish the full causal chain from software-controlled stress to silent data corruption, so the significance is conditional on the full paper providing direct experimental or simulation evidence for that link. The work could open new directions in aging-aware security and reliability analysis of processor cores.","major_comments":[{"comment":"The central demonstration is the >7x increase in wear on a targeted FMA pipeline path. The abstract does not state how this figure was obtained: fabricated chip, FPGA emulation with injected delays, gate-level simulation, or SPICE-level NBTI modeling. It also does not report error bars, sample size, or the statistical significance of the comparison against 'typical workloads.' Because this quantitative claim is the primary evidence that software can intentionally steer aging, the methodology must be specified and justified.","section":"Abstract"},{"comment":"The claim of 'targeted and silent data corruption in a co-running victim application' is phrased as 'an attacker could leverage such an attack,' which is weaker than a demonstration. The abstract does not state whether silent corruption was actually observed in a running system or whether it was inferred from an aging and timing model. If the corruption is only inferred, the second half of the attack claim is unsupported. The paper must clarify whether a timing error leading to a silent bit flip was directly observed, and if so, under what voltage, frequency, temperature, and detection-mechanism conditions.","section":"Abstract"},{"comment":"The threat model is underspecified. The attack requires 'sufficient knowledge of the processor core' and the ability to steer one path while a victim later uses the same path at a critical time. The abstract gives no information about how the attacker aligns victim execution, how the degraded path is chosen, or how the attack avoids error-detection mechanisms (e.g., parity, ECC, timing speculation recovery). These assumptions are load-bearing for the claimed end-to-end attack, and the full paper must state them explicitly and argue their plausibility in a real system.","section":"Abstract"}],"minor_comments":[{"comment":"The term 'wear' is used without a definition. Is it the relative increase in NBTI-induced threshold voltage shift, path delay, or some other aging metric? Defining the metric in the abstract would help readers interpret the >7x claim.","section":"Abstract"},{"comment":"The acronym 'TWA' is introduced as 'Targeted Wearout Attack' but not used consistently; the abstract alternates between 'attack mechanism,' 'such an attack,' and 'Targeted Wearout Attack.' A single defined term would improve clarity.","section":"Abstract"},{"comment":"No reference is given to prior work on NBTI modeling or fault-injection attacks. If this is a full paper, the introduction should cite relevant prior art (e.g., aging simulations, rowhammer-style wearout, and timing fault-injection methods) to position the novelty.","section":"Abstract"}],"recommendation":"uncertain","confidential_remarks":"This review is based solely on the abstract; the full text was not available. The abstract's central quantitative claim (>7x wear) and the end-to-end silent-corruption claim are both plausible but unverified at this level of detail. I would need the full methodology, experimental setup, and the actual corruption observation to make a sound accept/reject recommendation. The paper may be scientifically sound, but the review process should ensure that the distinction between demonstrated corruption and modeled potential corruption is explicit and honest."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThis is an abstract-only read, so treat everything with some salt. The idea is genuine news: a user-mode program that deliberately stresses a specific logic path to accelerate NBTI aging, then exploits the aged path to produce a silent miscompute. That is a new software-only fault injection vector if it holds. The abstract's case study on a RISC-V FMA pipeline showing >7x wear is concrete and suggests the authors actually ran something.\n\nWhat the abstract does not show is the second half of the attack chain. It says an attacker 'could leverage such an attack' to get silent data corruption, but there is no observation reported of a corrupted result in a running victim. If the authors only simulated aging and inferred a timing failure, then the title overstates. NBTI raises threshold voltage and slows transitions; it doesn't create a stuck bit cleanly. Whether the slowed path actually flips a bit depends on voltage/frequency margins, temperature, and whether the victim hits the same path at the degraded time. None of that appears in the abstract.\n\nThat gap is not fatal by itself—a follow-up with a full measurement would be worth reading—but it means the central claim is under-supported in this version. I'd also want to know what stress patterns they used, whether the >7x is measured on silicon or from a model, and how they rule out other aging mechanisms like HCI.\n\nFor a serious referee: yes. The idea is important enough to warrant a close look, and the authors are credible (known groups in hardware security and reliability). But the review should push hard for evidence of actual silent corruption, not just an aging estimate.\n\nFor citation: I wouldn't cite it yet, because the verified payload is only the wear figure. If the full paper has victim-corruption results, it becomes citable.\n\nBring to reading group? Maybe—a good discussion piece about what counts as demonstrating an attack.","headline":"A plausible targeted-aging attack, but the abstract only demonstrates the wear side; the silent-corruption claim is inferred, not shown.","tokens_in":1438,"tokens_out":1604,"would_cite":false,"duration_ms":19670,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Unprivileged code can age a CPU path and silently corrupt data","keywords":["Negative-Bias Temperature Instability","aging attack","wearout","fault injection","RISC-V","fused multiply-add","hardware security","silent data corruption"],"falsifier":"Measure the delays on the targeted FMA path in a real RISC-V core after running the attack software for the claimed duration; if the path delay does not shift by the predicted >7x amount relative to a control workload, or if the victim application never produces a corrupted result in repeated trials, the central claim fails.","tokens_in":697,"feed_emoji":"🔬","tokens_out":2107,"duration_ms":28465,"temperature":0.7,"pith_summary":"This paper proposes and demonstrates a new class of hardware attack it calls a Targeted Wearout Attack. The authors claim that an attacker with only user-level privileges can run a deliberately crafted software program that repeatedly stresses one specific logic path in a processor core, accelerating the normal NBTI aging mechanism on that path by more than sevenfold. The degraded path can then flip a bit during a later victim computation, producing a wrong answer without crashing the program. The work provides a general methodology for the attack and a concrete demonstration in a RISC-V fused multiply-add pipeline, showing targeted and silent data corruption in a co-running victim application. If true, this shifts the threat model for aging: wearout is not just a reliability concern but an exploitable security vulnerability.","feed_headline":"Unprivileged code can age a CPU path and silently corrupt data","feed_subtitle":"A RISC-V fused-multiply-add path sees a >7x wear increase, letting user-level code induce silent errors.","key_machinery":"The central mechanism is Negative-Bias Temperature Instability (NBTI), a dominant aging process in nanoscale CMOS circuits in which the threshold voltage shifts over time depending on the voltage stress applied to individual transistors. Because the stress is controlled by the logic values and switching activity driven by software, an attacker can deliberately steer the circuit into patterns that maximize wear on a targeted path. The paper's contribution is treating this input-dependent aging as a fault-injection vector rather than merely a reliability issue.","core_discovery":"The central claim is that an attacker with sufficient microarchitectural knowledge can intentionally and selectively accelerate hardware aging through software alone. By controlling the data flowing through a functional unit, the attacker repeatedly toggles the transistors on a chosen path, increasing the stress on that path well beyond normal workloads. The abstract reports a case study in which a targeted path inside a RISC-V fused multiply-add pipeline experiences a greater-than-sevenfold increase in wear, and the resulting aged circuit silently corrupts data in a co-running victim application. The attack mechanism is general: any input-dependent aging mechanism in a functional unit can,","pith_inferences":["This attack class likely extends beyond NBTI to other input-dependent aging mechanisms such as hot-carrier injection (HCI) and electromigration, meaning the same methodology could apply to different circuit types and process nodes.","The generalization of the technique suggests that any computational unit whose internal data paths are attacker-influenced — caches, integer ALUs, address generation — could be a target, not just the FMA pipeline.","One implied countermeasure is to randomize or schedule functional-unit usage so that no single path accumulates disproportionate stress, but such wear-leveling would need to be invisible to performance and power constraints.","The dependency on exact victim scheduling and data flow makes the real-world attack probabilistic; a natural next step would be measuring the success rate on actual hardware under varying victim workloads."],"forward_implications":["If the attack is generally viable, hardware designers must treat aging as a security concern, not only a reliability one, and consider path-wear balancing or aging monitors in critical units.","The attack demonstrates that fault injection can be achieved without physical access, voltage glitching, or electromagnetic probes; pure software suffices.","The 'stuck bit' effect from aged transistors can be deliberately positioned in a functional unit to cause a specific incorrect calculation, making silent data corruption a credible outcome.","The RISC-V FMA pipeline demonstration suggests that floating-point units, commonly used in scientific and security-critical code, are a realistic target.","The >7x wear increase shows that an attacker can dramatically shorten the effective lifetime of a specific component, raising denial-of-service and hardware-tampering possibilities."],"supporting_citations":[],"fun_headline_variants":["Software ages CPU paths to silently corrupt data","User-level code triggers >7x wear, causing silent errors","Targeted wearout: software-driven aging attack on CPUs","RISC-V CPU's FMA pipeline ages 7x faster under attack","Unprivileged code ages CPU logic for silent corruption"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The attack assumes the attacker can precisely and repeatedly stress one specific microarchitectural path while a victim later happens to use that same path at the moment the aged circuit flips a bit.","fun_headline_variants_meta":{"raw":{"variants":["Software ages CPU paths to silently corrupt data","User-level code triggers >7x wear, causing silent errors","Targeted wearout: software-driven aging attack on CPUs","RISC-V CPU's FMA pipeline ages 7x faster under attack","Unprivileged code ages CPU logic for silent corruption"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000343,"raw_usage":{"total_tokens":1717,"prompt_tokens":731,"completion_tokens":986,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":475,"completion_tokens_details":{"reasoning_tokens":904}},"tokens_in":475,"tokens_out":986,"duration_ms":8356,"temperature":1.0,"reasoning_tokens":904,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T17:06:42.649213+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the delays on the targeted FMA path in a real RISC-V core after running the attack software for the claimed duration; if the path delay does not shift by the predicted >7x amount relative to a control workload, or if the victim application never produces a corrupted result in repeated trials, the central claim fails.","supporting_citations":[],"review_version":1}