{"id":"7e257a2c-7c34-4e4a-a376-598b254f6b75","arxiv_id":"2508.17562","paper_version":1,"verdict":"UNVERDICTED","confidence":"LOW","novelty_score":5.0,"correctness_risk":"unknown","formal_verification":"none","parameter_count":0,"one_line_summary":"A 28nm hybrid digital/analog SRAM compute-in-memory macro uses a 2D-weighted capacitor array to perform complex-number MACs at 1.80 Mb/mm2 density with 0.435% RMS error.","lead":"The paper reports a 28nm SRAM compute-in-memory chip that performs complex-number multiply-accumulate calculations using a hybrid digital/analog design with a new 2D-weighted capacitor array. The design achieves high density and low error without input DACs, which matters for energy-efficient AI and wireless signal processing hardware.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Reported 0.435% RMS error lacks a defined operating envelope (bit split, accumulation length, measurement corners), making the central accuracy claim unverifiable from the abstract.","rationale":"The reader's verdict is UNVERDICTED due to abstract-only evidence. I agree with that but identify a more precise gap: the RMS error number is not merely missing a baseline; it lacks a defined operating point, so no statistical claim can be evaluated. The hybrid architecture is plausible, and the density number could be checked later from a die photo, but the error number is the crux. No internal inconsistency can be found in the abstract, because no mechanism is described. Therefore the verdict should remain unchanged pending full-text inspection.","tokens_in":703,"tokens_out":6208,"duration_ms":78310,"concrete_test":"Locate the measurement section of the full text and verify the definition of the 0.435% RMS error. Then run a Monte Carlo mismatch simulation of the analog lower-bit path using the 28nm PDK mismatch model and the paper's reported array dimensions; recompute the RMS error for the stated accumulation length and worst-case corner. If the simulated error exceeds 0.435% by more than 2×, the reported single number is not representative of the design across its operating envelope.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is the 0.435% RMS error, and it is load-bearing because the entire value proposition (DAC-free hybrid CIM with improved accuracy) depends on it. For this number to be meaningful, the full text must define the error metric: normalized to what full scale? What input range? What analog/digital bit split? How many terms are accumulated in one MAC? How many chips, at what supply and temperature? Charge-sharing capacitor-array CIM accumulates mismatch, charge-injection, parasitic, and noise errors that scale with array size and accumulation length; the abstract provides no constraints. If the 0.435% was measured on a single chip at a single corner with a short accumulation, it cannot support the headline. In addition, 'without the need for input DACs' is uncheckable from the abstract; if the binary-weighted capacitor array acts as a charge-scaling DAC, the claim is nominal. Thus the paper's main quantitative assertion is not falsifiable from the abstract.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This abstract-only submission reports a 28nm 6T-SRAM compute-in-memory (CIM) macro for complex-number MAC operations. The proposal is a hybrid digital/analog architecture in which digital CIM handles the upper bits and analog CIM handles the lower bits via a 2D-weighted capacitor array, with no separate input DACs. The abstract claims a measured memory density of 1.80 Mb/mm2 and 0.435% RMS error, and states that the complex CIM unit produces real and imaginary outputs in a single conversion. Because the full text was not supplied, this report evaluates only what the abstract itself supports.","tokens_in":927,"tokens_out":2248,"duration_ms":27518,"significance":"If the full paper supports the headline numbers with proper measurement conditions, this would be a competitive density figure for 28nm CIM and the hybrid upper-digital/lower-analog split is an interesting area-accuracy trade-off. The single-conversion generation of real and imaginary parts is a useful latency feature. The abstract is plausible but not verifiable: the 0.435% RMS error has no defined operating envelope, the density metric is unspecified, and the 'without input DACs' claim is ambiguous. The result is potentially significant, but the abstract alone does not establish it.","major_comments":[{"comment":"The central accuracy claim, '0.435% RMS error,' is not defined. The abstract does not state the normalization full-scale range, input bit width and the digital/analog bit split, the number of accumulated MAC terms, supply voltage and temperature corners, number of measured chips, or any comparison against a digital or full-analog baseline. Because this number is load-bearing for the paper's value proposition, the abstract makes it unfalsifiable. The full text must supply this measurement envelope before the claim can be assessed.","section":"Abstract"},{"comment":"The density claim '1.80 Mb/mm2' is ambiguous. It is not clear whether this is bit-cell array density, macro-level density including peripherals, or another basis. CIM density claims are only meaningful when the area definition is specified; otherwise the headline figure cannot be checked against prior art.","section":"Abstract"},{"comment":"The phrase 'without the need for input DACs' is ambiguous. A binary-weighted capacitor array that is charged or discharged based on input bits effectively performs charge-scaling DAC conversion. If the design uses the array itself as the DAC, the abstract should state that explicitly; as written, it invites the inference that no DAC-like function exists anywhere in the input path.","section":"Abstract"}],"minor_comments":[{"comment":"The line-break hyphen in 'num-ber' should be removed; the word should be 'number'.","section":"Abstract"},{"comment":"The notation 'Digital(D)/Analog(A)' should be formatted as 'Digital/Analog' or with appropriate spacing for readability.","section":"Abstract"},{"comment":"The abstract does not mention energy, throughput, or accuracy-versus-energy trade-offs, which would strengthen the comparison with other CIM macros.","section":"Abstract"}],"recommendation":"uncertain","confidential_remarks":"This is an abstract-only review; the full text is essential. The skeptic's concern about the missing operating envelope for the 0.435% RMS error is decisive at the abstract level. I cannot recommend acceptance, revision, or rejection without access to the full paper. If the full text defines the RMS error metric, density basis, measurement corners, and DAC interpretation, and those definitions are consistent with the claims, the paper could be a solid CIM contribution."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"You should know this paper before the other CIM work you're tracking: it reports a 28nm 6T-SRAM compute-in-memory macro for complex-number MACs, and the hook is a 2D-weighted capacitor array that lets the design split MAC work into digital upper bits and analog lower bits without input DACs. That split, plus a single conversion that outputs both real and imaginary parts, is a real circuit contribution as far as I can tell from the abstract. The reported 1.80 Mb/mm2 density and 0.435% RMS error are the kind of numbers that make this worth a second look.\n\nWhat the paper does well: the hybrid digital/analog scheme is a sensible way to trade accuracy against area, and the 2D-weighted capacitor array appears to be a new twist, not a restatement of prior hybrid CIM. Avoiding input DACs is also a legitimate area saver for complex MACs, which usually need heavy peripheral circuitry. If the measurement data holds up, this is a useful datapoint for baseband and edge AI accelerators.\n\nThe soft spots are real but mostly about the abstract, not necessarily the work. The 0.435% RMS error is load-bearing and the abstract gives no operating envelope: no bit split, no accumulation length, no supply/temperature corners, no chip count, no definition of what the error is normalized to. The stress-test note is right that this makes the claim unverifiable from the abstract. But that's an abstract-length problem, not evidence the paper is wrong. The same goes for the DAC-free claim: a binary-weighted capacitor array can behave like a charge-scaling DAC, so I'd want the full text to clarify how the input path differs from a conventional DAC. Those are the two questions a referee should push on.\n\nI don't see circular derivation here. The error and density are measured outputs, not fitted predictions. The citation pattern is impossible to judge from an abstract that cites nothing, but that's normal for a conference-style report.\n\nBottom line: this is a paper for people building SRAM-CIM macros, especially for complex arithmetic. It deserves a serious referee if the full text includes the measurement details that the abstract omits. I'd want the reviewer to check the accuracy metric and the DAC-free claim closely. I wouldn't cite it on the abstract alone, but I'd read the full version and probably bring it to our next CIM reading group.\n\nRecommendation: send it to peer review, with a strong request for measurement conditions and a baseline comparison.","headline":"A plausible hybrid SRAM-CIM complex-MAC macro with a genuinely new capacitor-array topology and promising silicon numbers, but the abstract alone doesn't let anyone verify the headline accuracy claim.","tokens_in":1411,"tokens_out":1432,"would_cite":false,"duration_ms":18253,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Complex-number MAC in SRAM: 1.80 Mb/mm2, 0.435% RMS error","keywords":["compute-in-memory","SRAM","complex-number MAC","analog compute","2D-weighted capacitor array","hybrid digital-analog","28nm macro","edge AI"],"falsifier":"Take a fabricated version of the macro and run complex MACs at several supply voltages and temperatures while sweeping input magnitudes; if RMS error exceeds 0.435% under nominal conditions or varies widely between chips, the accuracy claim as stated is not reproducible. Alternatively, compare against a fully digital complex MAC on identical data; the hybrid must stay within its claimed error bound to support the DAC-free accuracy advantage.","tokens_in":630,"feed_emoji":"⚡","tokens_out":4112,"duration_ms":41953,"temperature":0.7,"pith_summary":"The paper claims a new way to make a memory chip that also performs complex-number multiply-accumulate (MAC) operations, by splitting the computation into two parts: digital circuits handle the upper (more significant) bits, and analog circuits built around a 2D-weighted capacitor array handle the lower bits. This removes the need for input digital-to-analog converters, which the authors say improves accuracy and lowers area overhead. The prototype macro in 28nm 6T-SRAM is reported to achieve 1.80 Mb/mm2 memory density and 0.435% RMS error, and it outputs the real and imaginary parts of each complex MAC in a single conversion step, reducing latency. A sympathetic reader would care because this is a concrete path to running complex-number workloads inside memory with near-digital accuracy and high density, which matter for on-device neural networks.","feed_headline":"Complex-number MAC in SRAM: 1.80 Mb/mm2, 0.435% RMS error","feed_subtitle":"Digital upper bits + analog capacitor array removes input DACs; real and imaginary outputs come in one conversion.","key_machinery":"The key mechanism is the 2D-weighted capacitor array, a capacitor network with weights varying in two dimensions that performs multi-bit analog multiply-accumulate on the lower bits of the inputs. It carries the analog half of the hybrid computation, and its compact layout is what allows the macro to dispense with input DACs—the upper bits are processed by the digital CIM path, the lower bits by this array, and the two results are combined. The array is also what enables the single-conversion output of the real and imaginary parts of a complex MAC.","core_discovery":"The central discovery claimed is that a hybrid digital/analog compute-in-memory design can avoid input DACs while keeping error low, by confining digital CIM to the upper bits and analog CIM to the lower bits. The 2D-weighted capacitor array is the enabler: it allows the analog path to handle the less significant bits directly from a 6T-SRAM array without conversion. On a 28nm prototype, the authors report 1.80 Mb/mm2 memory density and 0.435% RMS error for complex-number MAC operations, with both real and imaginary outputs available after a single conversion.","pith_inferences":["If the error stays near 0.435% across supply and temperature, this macro could serve as a compact building block for complex-valued neural networks in radio-frequency or beamforming applications, where complex arithmetic is native.","The hybrid bit-split suggests a generalizable rule: spend digital resources only where precision matters, and let analog handle the rest; the same principle might extend to other analog compute primitives beyond capacitor arrays.","A natural next test would be measuring how RMS error scales with the number of lower analog bits, input magnitudes, and array size; that would reveal where the analog path's matching limits begin.","If the density claim is compared against a fully digital CIM with the same MAC throughput, the hybrid approach could show an area advantage proportional to the number of upper bits kept digital."],"forward_implications":["Complex-number MAC operations run inside a 6T-SRAM array, so weights do not need to be moved out of memory to be multiplied.","Eliminating input DACs reduces the area overhead of analog CIM, contributing to the reported 1.80 Mb/mm2 density.","Outputting real and imaginary parts in one conversion lowers latency relative to designs that need separate conversions for each part.","The reported 0.435% RMS error suggests the hybrid path can approach digital accuracy, making it usable for inference workloads.","The digital/analog bit-split shows a design choice for balancing precision and density that could scale to other bit partitions."],"supporting_citations":[],"fun_headline_variants":["No DACs needed: hybrid SRAM CIM hits 0.435% error","2D capacitor array eliminates input DACs in 28nm SRAM CIM","Hybrid SRAM CIM: complex MAC without DACs, 1.80 Mb/mm2","Single-conversion complex MAC on 6T SRAM: 0.435% error","No input DACs: analog capacitor CIM for complex MAC"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The 0.435% RMS error assumes the 2D-weighted capacitor array maintains sufficient matching and tolerable parasitics across the operating conditions of the 28nm process; the abstract gives a single error number without supply voltage, temperature, input range, or chip count.","fun_headline_variants_meta":{"raw":{"variants":["No DACs needed: hybrid SRAM CIM hits 0.435% error","2D capacitor array eliminates input DACs in 28nm SRAM CIM","Hybrid SRAM CIM: complex MAC without DACs, 1.80 Mb/mm2","Single-conversion complex MAC on 6T SRAM: 0.435% error","No input DACs: analog capacitor CIM for complex MAC"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001225,"raw_usage":{"total_tokens":4825,"prompt_tokens":646,"completion_tokens":4179,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":390,"completion_tokens_details":{"reasoning_tokens":4070}},"tokens_in":390,"tokens_out":4179,"duration_ms":31456,"temperature":1.0,"reasoning_tokens":4070,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T16:51:33.393305+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a fabricated version of the macro and run complex MACs at several supply voltages and temperatures while sweeping input magnitudes; if RMS error exceeds 0.435% under nominal conditions or varies widely between chips, the accuracy claim as stated is not reproducible. Alternatively, compare against a fully digital complex MAC on identical data; the hybrid must stay within its claimed error bound to support the DAC-free accuracy advantage.","supporting_citations":[],"review_version":1}