{"id":"dbf7c9b2-a235-4578-8b06-d5ebc9d1545f","arxiv_id":"2509.01339","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"LinkBo is a new Manchester-encoded single-wire protocol with priority messages, CRC and ACK, demonstrated on two FPGAs at 50.4 us latency and up to 7.5 Mbps.","lead":"The paper introduces LinkBo, a single-wire chip-to-chip protocol with priority messages, CRC error detection, and hardware interrupts. It reports a 50.4 microsecond high-priority message latency on two FPGAs, 20 times faster than 1-wire, and up to 7.5 Mbps over short wires.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Claimed hardware-interrupt preemption that justifies the 50.4 us high-priority latency guarantee is never implemented or tested; the measured 50.4 us is an idle-bus point measurement.","rationale":"The reader identified the receiver's first-edge synchronization as the weakest assumption. That is a real robustness limitation, but it is common to any edge-triggered single-wire scheme and is partially supported by the distance data. The more load-bearing concern is the unverified hardware-interrupt mechanism, because the 50.4 us 'guarantee' is the paper's headline differentiator and is explicitly tied to preempting LP traffic. The paper never tests a busy bus, never shows HP interrupting an in-flight LP message, and does not specify how a half-duplex transmitter detects an external HP sync while driving. This leaves the central latency claim as an idle-bus measurement. The measured idle-bus numbers are credible, so the correct response is to keep the reader's CONDITIONAL verdict and add the condition that interrupt preemption be demonstrated or the claim be qualified. No ad hominem is intended; this is purely about the scope of the evidence.","tokens_in":12898,"tokens_out":9597,"duration_ms":109944,"concrete_test":"Use two FPGAs with a wire-AND bus: FPGA A repeatedly transmits a 7-byte LP message while FPGA B (or a third wire-AND node) asserts an HP request at controlled offsets (e.g., after 1, 2, and 3 LP bytes). Measure the time from HP request assertion to valid ACK and verify that the LP transmitter cleanly aborts or resumes and the bus returns to idle without lockup. Pass criterion: HP completes within 50.4 us plus one Manchester slot. If this fails, the interrupt/preemption claim in the abstract should be re-scoped to idle-bus latency.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section III-B states that 'LinkBo allows HP messages to interrupt LP messages transmission', and Section III-C says the LBDET 'watches for prolonged low-level signals on the bus, signaling a high-priority event and triggering an interrupt.' Section V-A mentions a TOP FSM that manages activation/deactivation during interruptions, but no state-machine details, timing, or experimental validation are given. Figure 13(a) and Section VII-A measure HP latency for a single message on an idle 11 cm wire; Section VII-B's distance sweep also transmits one message type at a time. Therefore the abstract's 'protocol-level guarantees that high-priority messages are delivered ... in just 50.4 us' is not established under the bus-contention condition that the interrupt feature is meant to address. The mechanism is also underspecified: in half-duplex operation, a transmitting node is driving the wire, so it cannot simply 'watch' for the HP sync low pulse without an explicit collision-detection/abort rule. Without a demonstrated abort/resume protocol, the 50.4 us figure is an unloaded transmission time, not a latency guarantee.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes LinkBo, a single-wire, Manchester-coded chip-to-chip protocol with two message priorities, a 4-bit CRC, acknowledgment, and a hardware-interrupt mechanism for high-priority (HP) messages. The authors present a Simulink system/channel model, an RTL-style architecture for TX/RX/driver, and an FPGA implementation on two Cyclone-IV boards. Measured results include a 50.4 µs HP latency on an idle 11 cm wire, LP latencies up to 224.4 µs for 7 bytes, HP throughput up to 15 m (300 kbps) and 7.5 Mbps over 11 cm, and LP throughput up to 5.6 m. The paper compares LinkBo against 1-wire and UNI/O in latency, effective bit rate, and distance.","tokens_in":13124,"tokens_out":2516,"duration_ms":33422,"significance":"If the claims are fully validated, LinkBo would be a useful contribution to single-wire interfaces for short-range chip-to-chip links: it offers a concrete message format, CRC/ACK error handling, and a measured latency advantage over commercial 1-wire and UNI/O. The strengths of the paper include a working FPGA demonstration, measurement-based latency and throughput figures, and a parameterized channel model (Section IV-C) that gives quantitative sensitivity trends. However, the headline claims are currently broader than the evidence: the 50.4 µs latency is not shown under bus contention, the 15 m/300 kbps and 7.5 Mbps figures apply only to HP messages, and the hardware-interrupt feature is described but not implemented or tested. These discrepancies need to be resolved before the central claims can be accepted.","major_comments":[{"comment":"The abstract states that 'LinkBo protocol-level guarantees that high-priority messages are delivered ... in just 50.4 µs.' This is not established for the interrupt scenario. Section III-B describes HP messages interrupting LP transmission, and Section V-C introduces the LBDET interrupt trigger, but no contention experiment, timing diagram, or state-machine detail is provided. The 50.4 µs value in Section VII-A and Fig. 14 is measured for a single HP message on an idle bus (11 cm and 5 m, one message type at a time). The abstract should say 'measured on an idle bus' or the authors must add an experiment where an HP message interrupts an ongoing LP transmission and measure the actual delivery latency under that condition.","section":"Abstract; Section III-B; Section VII-A"},{"comment":"The abstract's distance and bitrate claims are not qualified by message priority. Fig. 15 shows LP throughput drops to near zero beyond ~5.6 m, while HP throughput persists until ~15 m. Fig. 17 shows 11 cm HP reaches 7.5 Mbps but LP reaches only 2.3 Mbps. Therefore the statement 'reliably supports wire lengths up to 15 meters with a data rate of 300 kbps, while reaching a maximum data rate of 7.5 Mbps over an 11 cm wire' is misleading when read as applying to the protocol generally. These numbers are HP-only. The abstract and Section VII-B must state that the 15 m/300 kbps and 7.5 Mbps figures are for high-priority messages only, and that low-priority messages are limited to 5.6 m and 2.3 Mbps.","section":"Abstract; Section VII-B; Fig. 15; Fig. 17"},{"comment":"The hardware-interrupt mechanism is underspecified at the physical layer. In half-duplex operation, a transmitting node is actively driving the bus; it cannot simply 'watch' for a falling-edge HP sync without an explicit collision-detection or abort rule. The paper states LBDET 'watches for prolonged low-level signals' and triggers an interrupt, but does not explain how a transmitting node can observe the bus while driving, how it aborts its own transmission, or how bus turn-around is managed. This is load-bearing for the claimed HP preemption capability. A concrete state diagram, a timing diagram of the interruption sequence, and an experimental demonstration are needed.","section":"Section III-B; Section III-C; Section V-C"},{"comment":"The synchronization scheme relies on detecting the first falling edge and measuring the low-pulse duration to distinguish HP from LP messages. The sensitivity of this single-point edge detection is not characterized beyond the distance sweep. The paper's own data show that LP messages (shorter sync low pulse) fail at 5.6 m, while HP messages (three-times-longer low pulse) survive to 15 m. This suggests that the claimed robustness is strongly dependent on the sync-pulse edge being clean. The authors should provide a quantitative analysis of timing margin versus wire length, capacitance, or supply voltage to support the 'fault-tolerant' characterization, or soften the robustness claim to the tested conditions.","section":"Section III-C; Section VII-B"}],"minor_comments":[{"comment":"The left panel of Fig. 1 appears to show total communication pins for SPI and I2C, but the figure caption is ambiguous; please clarify which line corresponds to SPI and which to I2C, and define 'Total Devices' on the x-axis.","section":"Section I; Fig. 1"},{"comment":"Table I lists 'Speed' ranges for 1-wire and UNI/O, but the LinkBo row is absent from that table; the comparison table in Section VII-C is more complete. Consider consolidating the two tables or adding LinkBo to Table I to avoid confusion.","section":"Section II-C; Table I"},{"comment":"The text says HP messages use '2 bit slots for synchronization,' but the description of the sync field says the first slot is held low and the second is Manchester 1. Clarify that a Manchester 'slot held low' is not a valid Manchester code; this is intentional for HP detection, but the wording should explain that the HP sync is not Manchester-encoded in the first slot.","section":"Section III-B; Fig. 5"},{"comment":"The 'LPF' label in Fig. 10 and Eq. (3) is unclear: the low-pass filter cutoff frequency is computed, but the relationship between LPF condition and throughput drop is not explained. Also, the star marker in Fig. 10 is not defined in the caption.","section":"Section IV-C; Fig. 10"},{"comment":"The figure shows '50.4 µs' for HP on 11 cm, but the text in Section VI says the HP message takes 47.5 µs plus 2.9 µs ACK. The discrepancy is small but should be reconciled, or explicitly state that the 50.4 µs includes ACK time.","section":"Section VII-A; Fig. 14"},{"comment":"The paper contains several typographical issues: 'thesis' in Section II-B, 'Linkbo' vs 'LinkBo' inconsistency, and missing commas in references. These should be cleaned up.","section":"General"}],"recommendation":"major_revision","confidential_remarks":"The paper is a solid starting point for a single-wire protocol with a real FPGA demonstration and useful measurement data, but the current write-up overclaims on three fronts: the unvalidated interrupt/preemption feature, the priority-dependent distance/bitrate numbers, and the missing physical-layer details of half-duplex collision handling. These are fixable with re-scoping and additional experiments, so I recommend major revision rather than rejection. The authors should also be asked to state explicitly which measurements are for idle-bus transmissions and which are under contention, and to provide a concrete state machine for the interrupt/abort procedure."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read the LinkBo paper. The short version: the FPGA measurements are credible and the protocol is a sensible integration of known building blocks — Manchester encoding, CRC-4, ACK, and wired-AND arbitration. The 50.4 µs HP latency on a quiet 11 cm wire is a solid data point, and the comparison to 1-wire and UNI/O is fair. But the paper oversells three things: the 'hardware interrupt' is never actually implemented or tested; the abstract's 15 m/300 kbps and 7.5 Mbps figures apply only to HP messages, not the LP messages that carry multi-byte payloads; and there is an internal contradiction about whether 1-wire has CRC.\n\nThe interrupt claim is the biggest gap. Section III-B says HP messages can interrupt LP transmission and the LBDET triggers an interrupt, but there is no state-machine description, no timing analysis, and no oscilloscope trace of preemption. All the latency measurements are single-message, idle-bus tests. In half-duplex, a node transmitting LP is driving the wire, so it cannot simply 'watch' for the HP sync pulse; you need an explicit abort/collision-detect rule, and the paper doesn't give one. Without that, the 50.4 µs is an unloaded transmission time, not the 'protocol-level guarantee' the abstract promises. This needs a real implementation or a scaled-back claim.\n\nThe distance/bitrate overstatement is more of a clarity problem. The abstract says 'supports wire lengths up to 15 meters with a data rate of 300 kbps' — true only for HP. LP messages die at 5.6 m. Since LP is the mechanism for multi-byte transfers, the practical range for general data is 5.6 m. The paper should qualify by priority class.\n\nThe 1-wire CRC confusion: the intro says 1-wire 'lacks mechanisms to secure data integrity,' but Table II credits it with an 8-bit CRC. The related-work section is sloppy here. The Simulink channel model uses parameters from the same PCB but is never validated against the FPGA results; that weakens the sensitivity analysis, though the FPGA distance sweep is the more direct evidence.\n\nAll that said, the protocol design is coherent. The idea of using a longer sync pulse for HP messages to improve long-distance robustness is clever and is supported by the distance sweep. The measured latency numbers are plausible: 15 Manchester bits at 3 MHz plus ACK gives ~50 µs. No code or raw data, but the oscilloscope captures and parameter sweep give enough evidence that the main latency figure is real. The receiver's sync scheme does rely on detecting one falling edge, and the paper doesn't characterize tolerance to glitches or temperature, but the HP/LP robustness difference at least indirectly supports the design choice.\n\nBottom line: this deserves a serious referee — the protocol is useful for area-constrained embedded systems — but the revision needs to either implement the interrupt or drop that claim from the abstract, and the distance/bitrate claims need to be qualified by priority class. I'd send it out.","headline":"The 50.4 µs latency is real for a quiet bus, but the 'hardware interrupt' and the 15 m/7.5 Mbps claims are not backed by the experiments.","tokens_in":13667,"tokens_out":5960,"would_cite":true,"duration_ms":61747,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"LinkBo claims a single wire can deliver an acknowledged, CRC-checked high-priority message in 50.4 µs, at least 20X faster than the 1-wire protocol and 6.3X faster than UNI/O, by encoding sync, priority, and clock recovery into a two-slot M","keywords":["single-wire protocol","Manchester encoding","chip-to-chip communication","low-latency serial interface","hardware interrupt","CRC error detection","FPGA implementation","asynchronous serial bus"],"falsifier":"Re-run the two-FPGA demonstration while sweeping wire length in half-meter steps from 5 m to 24 m at the 3 MHz clock, and also inject a spurious edge just before the sync edge at the receiver pin. The paper's argument predicts LP messages cease between 5.6 and 9 m and HP messages between 15 and 23 m, and that any ambiguity in the very first low pulse corrupts the frame: a mismatch in the cliff locations or a recovered message after an early spurious edge would overturn the synchronization claim.","tokens_in":12763,"feed_emoji":"⚡","tokens_out":7569,"duration_ms":79500,"temperature":0.7,"pith_summary":"LinkBo is a new single-wire protocol for chip-to-chip links that attacks the two weaknesses of today's 1-wire and UNI/O buses: long latencies and no acknowledgment. The paper's central claim is that a one-byte high-priority message with CRC error detection and an acknowledgment can cross a single wire in 50.4 µs, at least 20X faster than 1-wire and 6.3X faster than UNI/O. The same protocol adapts to distance, running at 7.5 Mbps over an 11 cm wire and at 300 kbps over 15 m, with the receiver and transmitter on independent clocks. If the measurements hold, single-wire communication becomes attractive for pin-constrained embedded systems that today use spare I2C or SPI lines. Hardware-level message priorities also let an urgent frame preempt a lower-priority transfer, which is new for single-wire buses.","feed_headline":"50 microseconds: one wire beats 1-wire by 20x","feed_subtitle":"LinkBo packs sync, payload, CRC, and ACK into one Manchester frame — 7.5 Mbps over 11 cm.","key_machinery":"The synchronization field is the load-bearing object. It consists of two Manchester slots whose low-pulse pattern distinguishes message priority and whose measured duration — counted by a prescaler from the first falling edge — recovers the transmitter's bit-slot time in the receiver's clock domain. That single measurement sets every subsequent decode; the re-synchronization module then keeps mid-slot edges aligned, and the 4-bit CRC plus ACK edge closes the loop with positive error feedback. The HP sync's three-times-longer low pulse is also what makes high-priority messages reach 15 m while low-priority messages fail past 5.6 m.","core_discovery":"LinkBo is a half-duplex single-wire protocol using IEEE802.3 Manchester encoding, so data, clock, and acknowledgment share one pin. Messages start with a two-slot synchronization field that also tags priority: a low first slot marks a high-priority message, a high first slot a low-priority one. The receiver's prescaler counts the first low pulse and divides by 1.5 to recover the transmitter's slot time, so the chips need no shared clock. A 4-bit CRC plus a no-edge/edge ACK gives the sender positive confirmation of a valid frame. On two FPGAs joined by one wire, the paper reports a 50.4 µs end-to-end high-priority message — 20X faster than 1-wire, 6.3X faster than UNI/O — and adaptive operati","pith_inferences":["The sync-pulse length is the real dial between speed and reach: the paper effectively samples only two settings (a one-slot low for LP, a three-times-longer low for HP), so an intermediate sync length might extend LP-class messages well beyond 5.6 m at a modest latency cost — an axis the paper leaves unmapped.","If the single-edge sync assumption is the weak point, a multi-edge or averaging sync (for example measuring both the first low pulse and the following half-slot) could make the protocol immune to a missed or glitched first edge without changing the frame format.","The wired-AND arbitration is only sketched; an interesting test the paper does not run is arbitration between simultaneous LP and HP sync patterns, where the winner's sync is already partly distorted before the loser stops driving."],"forward_implications":["Interrupt-class messages can be acknowledged and CRC-checked end-to-end in 50.4 µs, making single-wire links viable for time-critical traffic that previously required multi-wire buses.","A single wire now spans the distance range that matters for board-level design — centimeters on a PCB up to tens of meters between boards — by trading bit rate for reach (7.5 Mbps at 11 cm, 300 kbps at 15 m).","Because CRC and ACK are built into every frame, a receiver can silently drop corrupted messages and the sender learns of failure, closing a robustness gap the paper identifies in 1-wire and UNI/O.","The protocol's peer-to-peer wiring with wired-AND arbitration and a repurposable size field gives a route to multi-drop busses without a dedicated host, removing the single point of failure in 1-wire's master/slave model."],"supporting_citations":[{"why":"Defines the 1-wire bus operation and timing that LinkBo is compared against and that supplies the baseline model.","marker":"[4]"},{"why":"Documents the 1-wire protocol's reset pulse and bit-slot durations, which are the source of the latency LinkBo claims to cut by 20X.","marker":"[5]"},{"why":"Specifies the UNI/O bus, the second commercial single-wire protocol LinkBo is benchmarked against (6.3X latency claim).","marker":"[7]"},{"why":"Supplies the Manchester encoding method (IEEE802.3 standard) that LinkBo uses for self-clocking and synchronization.","marker":"[6]"},{"why":"Supplies the LFSR-based CRC generation method used for the 4-bit error-detection field.","marker":"[22]"},{"why":"Motivates the pin-count cost argument by introducing I2C and SPI, the multi-wire protocols LinkBo aims to replace.","marker":"[1]"}],"fun_headline_variants":["One wire, no shared clock: LinkBo hits 50.4µs, 20x faster than 1-wire","LinkBo: single-wire protocol cuts high-priority latency to 50.4µs","Adaptive single-wire interface: 50.4µs latency, 7.5 Mbps, 15m reach","Fault-tolerant single-wire protocol: 20x quicker than 1-wire","Self-clocking one-pin link: 50.4µs messages, 20x speedup over 1-wire"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The receiver locks onto a message by measuring the first low pulse on the wire and deriving the bit time from that one measurement; if the first falling edge is missed or blurred by wire effects, the entire message is lost before any error check can run.","fun_headline_variants_meta":{"raw":{"variants":["One wire, no shared clock: LinkBo hits 50.4µs, 20x faster than 1-wire","LinkBo: single-wire protocol cuts high-priority latency to 50.4µs","Adaptive single-wire interface: 50.4µs latency, 7.5 Mbps, 15m reach","Fault-tolerant single-wire protocol: 20x quicker than 1-wire","Self-clocking one-pin link: 50.4µs messages, 20x speedup over 1-wire"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000257,"raw_usage":{"total_tokens":1435,"prompt_tokens":785,"completion_tokens":650,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":529,"completion_tokens_details":{"reasoning_tokens":511}},"tokens_in":529,"tokens_out":650,"duration_ms":6222,"temperature":1.0,"reasoning_tokens":511,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T12:37:23.324672+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-run the two-FPGA demonstration while sweeping wire length in half-meter steps from 5 m to 24 m at the 3 MHz clock, and also inject a spurious edge just before the sync edge at the receiver pin. The paper's argument predicts LP messages cease between 5.6 and 9 m and HP messages between 15 and 23 m, and that any ambiguity in the very first low pulse corrupts the frame: a mismatch in the cliff locations or a recovered message after an early spurious edge would overturn the synchronization claim.","supporting_citations":[{"cited_title":"Overview of 1-wire technology and its use,","cited_arxiv_id":null,"evidence_quote":"Defines the 1-wire bus operation and timing that LinkBo is compared against and that supplies the baseline model."},{"cited_title":"Implementing 1-wire enumeration for tmp1826 with tm4c129x microcontrollers,","cited_arxiv_id":null,"evidence_quote":"Documents the 1-wire protocol's reset pulse and bit-slot durations, which are the source of the latency LinkBo claims to cut by 20X."},{"cited_title":"Uni/o bus sepecification,","cited_arxiv_id":null,"evidence_quote":"Specifies the UNI/O bus, the second commercial single-wire protocol LinkBo is benchmarked against (6.3X latency claim)."},{"cited_title":"Encoder circuit for inverse differential manchester code operating at any frequency,","cited_arxiv_id":null,"evidence_quote":"Supplies the Manchester encoding method (IEEE802.3 standard) that LinkBo uses for self-clocking and synchronization."},{"cited_title":"Automatic generation of parallel crc circuits,","cited_arxiv_id":null,"evidence_quote":"Supplies the LFSR-based CRC generation method used for the 4-bit error-detection field."},{"cited_title":"An introduction to i 2 c and spi protocols,","cited_arxiv_id":null,"evidence_quote":"Motivates the pin-count cost argument by introducing I2C and SPI, the multi-wire protocols LinkBo aims to replace."}],"review_version":1}