{"id":"9efdce68-084e-4bf9-bae5-4d9fcc6ecc32","arxiv_id":"2509.01555","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A heavily-doped narrow-trench silicon microring modulator demonstrates open-eye 400 Gbps PAM6, 360 Gbps PAM4, and 200 Gbps NRZ, plus a 0.97 fJ/bit bias-free 32 Gbps mode.","lead":"A silicon photonics team reports a microring modulator that reaches 400 Gbps per wavelength using PAM6, the highest rate yet shown on a CMOS-compatible silicon ring modulator, along with a low-voltage bias-free mode that consumes about 1 fJ/bit. The result matters because 400G-per-lane links are the target for next-generation AI data-center interconnects and co-packaged optics.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"400-Gbps/λ claim rests on averaged, equalized open-eye data at a 55-GHz test-bench limit; the paper's own Methods say 155-Gbaud PAM4 eyes were barely discernible, so the record is not yet established as device capability.","rationale":"The reader's weakest assumption correctly identifies the absence of BER/FEC validation and the reliance on heavily averaged, equalized open-eye data at the 400-Gbps/λ headline. My stress-test adds two specific pieces of in-scope evidence: (1) the equalized E/E vs E/O/E comparison in Fig. S11 is insufficient because the FFE is re-optimized per measurement and can compensate the combined channel, and (2) the Methods section itself concedes that the setup is marginal at these rates, saying 155-Gbaud PAM4 eyes were barely discernible and that a clearer 400-Gbps PAM6 eye is expected with higher-bandwidth AWGs and RF components. This makes the central record claim conditional rather than established. I did not find an independent fatal flaw in the core device physics: the reported >110-GHz EO bandwidth, wafer uniformity, and error-free low-swing self-biased NRZ results are internally consistent. The appropriate requirement before accepting the 400-Gbps/λ record is a direct BER/FEC measurement or a repetition with a less bandwidth-limited test bench. The reader's CONDITIONAL verdict therefore remains correct.","tokens_in":19145,"tokens_out":8120,"duration_ms":94134,"concrete_test":"Measure pre-FEC BER of 133.3-Gbaud PAM6 at 5.75 dBm received power using the same drive condition, but with a real-time error detector and no 16× waveform averaging, keeping the 16-tap FFE fixed. If the BER is above the KP4-FEC threshold (2.4e-4) or the eye closes when averaging is removed, the 400-Gbps claim should be reported as an equalized/averaged open-eye demo, not a device-level 400G/λ capability. For completeness, repeat with a ≥70-GHz RF path; if the eye improves substantially, the 55-GHz bench, not the MRM, was the limiting element.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The headline '400-Gbps/λ' claim is carried by a single open-eye measurement at 400 Gbps PAM6 (Fig. 5c), made with an AWG/RF chain whose direct electrical bandwidth is ~55 GHz, a 16-tap FFE, a half-baud Bessel filter, and 16× averaging, and without BER or FEC-threshold validation at 360/400 Gbps. The paper's attempt to isolate the MRM via similarity between E/E and E/O/E eyes (Fig. S11) is not decisive: the FFE is re-optimized for best eye quality (Fig. S9), so an adaptive equalizer can compensate the combined MRM+bench response; equalized similarity shows only that the full optical link matches the electrical back-to-back after processing, not that the MRM is the bottleneck-free component. The manuscript's own Methods section states: 'Due to the limited bandwidth of the measurement setup, eye openings at 155 Gbaud PAM4 were barely discernible... It's expected to get a clearer eye diagram for 400 Gbps PAM6 signal with higher-bandwidth AWGs and improved RF components.' Since PAM6 at 133.3 Gbaud is more SNR-hungry than PAM4 at a similar baud, this is an explicit indication that the 400-Gbps eye is marginal. With no quantitative SNR/TDECQ/BER for the headline case, the central claim is underdetermined: the open eye may reflect real modulator headroom or an artifact of averaging/equalization near the test-bench noise floor. The credible >110-GHz EO S21 and error-free 32-Gbps self-biasing results are not affected.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a silicon microring modulator (MRM) fabricated on a 300-mm SOI platform, using a heavily doped narrow-trench design to increase optical and electrical bandwidth while maintaining modulation efficiency. The authors report an electro-optic bandwidth exceeding 110 GHz at -3 V bias and >80 GHz at 0 V, a Vπ·L of ~0.57 V·cm, and good wafer-scale uniformity across nine dies. In a self-biasing mode, they demonstrate error-free 32-Gbps NRZ transmission over 2 km with 0.43-Vpp drive and 0.97 fJ/bit, plus error-free 80-Gbps NRZ with a 3-tap FFE. In a depletion mode, they report open eye diagrams at 200 Gbps NRZ, 360 Gbps PAM4, and 400 Gbps PAM6, claiming the first wafer-scale silicon MRM reaching 400 Gbps/λ.","tokens_in":60,"tokens_out":2812,"duration_ms":64418,"significance":"If the headline 400-Gbps/λ result is established, this would be a significant advance for silicon photonic transmitters: it combines a credible >110-GHz EO response with wafer-scale manufacturability and a low-voltage, sub-fJ/bit operating mode, offering a path toward both scale-up and scale-out optical interconnects. The DC, S21, and low-voltage BER measurements are internally consistent and support the device's high-bandwidth, low-energy claims. However, the central novelty claim—the 400-Gbps/λ record—rests on open-eye measurements with heavy receiver-side equalization, averaging, and a test bench limited to ~55 GHz, without BER, FEC-threshold, or quantitative signal-quality metrics at the headline rates. The paper's own Methods section concedes that 155-Gbaud PAM4 eyes were barely discernible. The result is therefore plausible but currently underdetermined; the central claim needs either stronger evidence or a more limited statement.","major_comments":[{"comment":"The 400-Gbps/λ claim is supported only by an open PAM6 eye after 16× averaging, a 16-tap FFE, a half-baud Bessel filter, and an AWG/RF chain whose effective bandwidth is ~55 GHz. No BER, FEC-threshold margin, TDECQ, or SNR is reported for 360G PAM4 or 400G PAM6. The Methods explicitly state that 'eye openings at 155 Gbaud PAM4 were barely discernible' and that a clearer eye is expected with higher-bandwidth AWGs. Since PAM6 at 133.3 Gbaud is more SNR-hungry than PAM4 at a similar baud, this statement directly undermines the conclusion that the device—rather than the equalizer, averaging, or test bench—achieved 400 Gbps. The claim should be downgraded to 'equalized open-eye demonstration subject to test-bench limitations' or supported by quantitative link metrics (e.g., TDECQ under a defined FEC limit, or BER) at 360G/400G.","section":"Fig. 5(c), Methods, Supplementary Note 3.E"},{"comment":"The similarity between E/E and E/O/E eyes is used to argue that the MRM is not the bottleneck. This argument is not decisive because the FFE taps are re-optimized for best eye quality (Fig. S9), so an adaptive equalizer can compensate the combined MRM-plus-bench response. Matching post-equalized eyes only shows that the optical link can be made to mimic the electrical back-to-back after DSP; it does not isolate the modulator's intrinsic penalty. The authors should provide a quantitative comparison of pre-FFE SNR/TDECQ, or a channel penalty estimate, to separate modulator distortion/roll-off from AWG/connector roll-off.","section":"Supplementary Note 3.D, Fig. S11"},{"comment":"The claim that the device 'breaks the bandwidth–efficiency trade-off' and 'dispels the prevailing concern that silicon modulators cannot support 400 Gbps-per-wavelength' is stronger than the evidence. The device has a Q of ~1500 and a Vπ·L of 0.57 V·cm, which is competitive but not a fundamental break; the 400G demonstration is not yet validated as error-free or FEC-clean. I recommend tempering the Discussion to state that the device shows a promising path toward 400G/λ, pending link-level validation with a test bench capable of the baud rate.","section":"Discussion, Fig. 5 caption"}],"minor_comments":[{"comment":"The caption says the driving signal is amplified to '1 Vpp', while the main text and Methods state the device is driven at 2 Vpp. Please clarify the actual swing at the DUT and reconcile the voltage reported in Fig. 5(b).","section":"Fig. 5 caption"},{"comment":"The text states the AWG has 'nominal analog bandwidth exceeding 80 GHz' but later says the actual direct link is limited to ~55 GHz. Since Fig. S10(a) shows calibration flattening over 0–90 GHz, the discrepancy between nominal AWG bandwidth, calibrated channel response, and the 55-GHz limitation should be stated more clearly.","section":"Methods, Eye diagram measurements"},{"comment":"The FFE tap count is varied only for 128 Gbaud PAM4. It would be helpful to state the number of taps used for the 180-Gbaud NRZ, 140-Gbaud PAM4, and 155-Gbaud PAM6 measurements, since the eye quality depends strongly on this choice.","section":"Supplementary Note 3.C, Fig. S9"},{"comment":"There are several typographical errors: 'MRMS' in the abstract, 'capaticance' in Fig. S2, 'out MRM' in the Methods, 'mircroring' in Table S2, and an apparent duplicate reference [19] in the reference list. Please proofread carefully.","section":"Throughout"},{"comment":"The table reports line rates but does not indicate whether the cited results are BER-verified or open-eye-only. Adding a column with 'BER' or 'open eye' would help readers compare the strength of evidence across prior work and this paper.","section":"Supplementary Table 2"}],"recommendation":"major_revision","confidential_remarks":"The core device work appears solid, and the wafer-scale bandwidth uniformity and sub-fJ/bit self-biasing results are likely publishable even without the 400G claim. My main concern is that the title and abstract emphasize a 'record 400 Gbps/λ' that is not yet supported by the presented evidence. If the authors can either provide BER/FEC-threshold validation or rephrase the claim to reflect an equalized, test-bench-limited open-eye demonstration, the paper could become acceptable. I do not see evidence of circularity in the energy-efficiency calculation, though the Cj estimate is simulation-based and should be clearly labeled as such in the main text."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's the short version: the device work is real and worth taking seriously, but the 400-Gbps/λ headline is not yet proven. The paper demonstrates a heavily-doped narrow-trench silicon MRM with >110 GHz EO bandwidth at -3 V and good wafer uniformity, and the self-biasing low-voltage results are solid. What is genuinely new is the junction/trench design—I don't see that combination in the prior MRM literature—and the combination of high bandwidth with Vπ·L ≈ 0.57 V·cm. The DC spectra, RC/photon-lifetime model, and S21 measurements are internally consistent; the wafer-scale data across nine dies is a real plus for manufacturability.\n\nThe soft spot is exactly where the reader's report puts it. The 400G and 360G demonstrations are open-eye diagrams after 16× averaging, a 16-tap FFE that is re-optimized for best eye quality, and an AWG/RF chain whose direct electrical bandwidth is ~55 GHz. No BER or FEC-threshold data is reported at those rates. The authors' own Methods say that 155 Gbaud PAM4 eyes were 'barely discernible' with this setup, and PAM6 at 133 Gbaud is more SNR-hungry than PAM4, so the record claim is underdetermined. The E/E vs E/O/E comparison in Fig. S11 does not fix this: an adaptive equalizer can compensate the combined MRM+bench response, so equalized similarity only shows the full link behaves like the electrical back-to-back after processing, not that the MRM is the bottleneck. I don't think this is fatal to the device story, but the abstract should not state 'record 400 Gbps/λ' as a device capability.\n\nMinor issues: the 0.97 fJ/bit is a modulator-only estimate from simulated Cj (21 fF), with thermal tuning excluded; it's a fair model-based number, not circular, but it shouldn't be quoted without those caveats. The 400G eyes also used a PDFA and 2 Vpp, so link-level energy would be much higher.\n\nOverall: the core physics and device characterization hold up; the overclaim is in the interpretation of the eye measurements. This deserves a serious referee. I'd send it to review and ask the authors to either provide BER/TDECQ at 360/400G or soften the headline to 'DSP-assisted open eye at 400 Gbps' with the bench limits stated.","headline":"A credible high-bandwidth silicon MRM with solid low-voltage results, but the 400-Gbps/λ headline is carried by an averaged, equalized open eye and should not be taken as device capability as written.","tokens_in":20058,"tokens_out":2693,"would_cite":true,"duration_ms":30794,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["42.79.Hp","42.82.-m"],"model":"deepseek-v4-flash","headline":"A wafer-scale silicon microring modulator with a heavily doped narrow trench is claimed to reach 400 Gbps per wavelength, breaking the usual speed-efficiency trade-off.","keywords":["silicon microring modulator","400 Gbps per wavelength","silicon photonics","optical interconnects","wafer-scale uniformity","self-biasing modulation","PAM6","energy-efficient optical I/O"],"falsifier":"Run the same 400-Gbps PAM6 transmission with a higher-bandwidth AWG above 80 GHz and a wideband receiver, then count bit errors at a forward-error-correction threshold rather than relying on an averaged open eye. If the bit-error rate cannot be met without aggressive equalization, or if the electrical and optical eyes diverge once the bench bandwidth is lifted, the device is not actually 400-Gbps capable.","tokens_in":19083,"feed_emoji":"⚡","tokens_out":6892,"duration_ms":72103,"temperature":0.7,"pith_summary":"This paper reports a silicon microring modulator fabricated on a 300-mm CMOS-compatible silicon photonics platform and claims it can support 400 Gbps per wavelength, the first wafer-scale silicon ring solution to claim that rate. The key is a heavily doped narrow-trench ring that deliberately lowers the optical quality factor and lowers series resistance at the same time, decoupling the usual trade-off between modulation efficiency and speed. The device runs in two modes: a zero-bias self-biasing mode for energy-efficient short-reach links, achieving error-free 32-Gbps NRZ at 0.43 Vpp and 0.97 fJ/bit, and a reverse-biased depletion mode for ultrafast scale-out links, with open eyes at 200 Gbps NRZ, 360 Gbps PAM4, and 400 Gbps PAM6. If the headline rate holds under error-counting rather than open-eye criteria, it would make CMOS-compatible silicon photonics competitive with lithium-niobate and InP modulators for next-generation AI interconnects.","feed_headline":"Silicon microring modulator reaches 400 Gbps per wavelength","feed_subtitle":"A trench-doped ring widens optical and electrical bandwidths at once, keeping the device efficient and foundry-compatible.","key_machinery":"The central mechanism is the heavily doped narrow-trench PN junction inside the ring waveguide. By adding controlled propagation loss, the trench lowers the Q factor and raises the photon-lifetime-limited optical bandwidth; by reducing series resistance, the same geometry raises the RC-limited electrical bandwidth. This decouples the two terms in the combined electro-optic bandwidth formula 1/f_EO^2 = 1/f_ph^2 + 1/f_e^2, which is the design equation the paper uses to place the device above 100 GHz. Heavy doping also enhances the plasma-dispersion modulation efficiency and preserves spectral symmetry at zero bias, enabling distortion-free self-biasing operation.","core_discovery":"The paper's central claim is that the bandwidth-efficiency trade-off that has capped silicon microring modulators can be broken by a structural change: a symmetric, heavily doped P+N+ junction placed in a narrow-trench rib waveguide. The trench adds controlled optical loss, lowering the cavity Q factor and raising the photon-lifetime-limited bandwidth; the heavy doping lowers series resistance and increases carrier density, improving electrical bandwidth and modulation efficiency. Together these effects give an electro-optic bandwidth above 110 GHz at -3 V and roughly 80-83 GHz at zero bias, while keeping modulation efficiency at Vπ·L ≈ 0.57 V·cm. The authors demonstrate two operating regime","pith_inferences":["The decisive test is whether a wider-bandwidth AWG preserves the 400G eye; if the equalizer is currently correcting the ring's own roll-off, the practical device-limited rate is lower than claimed.","A bit-error-rate measurement at 400G under a forward-error-correction threshold would convert the open-eye result into a system-level claim; without it, 400G remains a modulation demonstration rather than a link specification.","The trench-doping approach is not obviously limited to O-band racetrack geometries; porting it to add-drop rings, C-band operation, or other resonant electro-optic materials could be a fast path to similar bandwidth gains."],"forward_implications":["A six-channel WDM array of these depletion-mode rings would carry roughly 2.4 Tbps per fiber, and a 16-channel self-biased array about 2 Tbps, using the ring's free spectral range to set channel spacing.","Silicon-photonics transceivers could move from 200G PAM4 to 400G-class per-lane links without abandoning CMOS manufacturing.","Self-biasing mode removes the bias tee and driver circuit, so transmitter energy can approach sub-fJ/bit levels compatible with UCIe 2.0 voltage swings.","Wafer-level bandwidth spread of about 10 GHz across nine dies indicates the design is manufacturable rather than a one-off laboratory device."],"supporting_citations":[{"why":"Supplies the prior athermal silicon modulator operating at 0.5 Vpp with roughly 25 GHz bandwidth, the low-voltage benchmark the self-biasing mode must outperform.","marker":"17"},{"why":"Holds an earlier silicon microring speed record of 240 Gb/s that this work claims to surpass on the same platform.","marker":"24"},{"why":"Demonstrates a 5 x 200 Gbps silicon microring chip, the multi-ring density benchmark this WDM scaling proposal extends.","marker":"28"},{"why":"Shows 540-Gbps single-wavelength transmission from an InP EML, the competing technology whose CMOS-compatibility gap motivates a silicon solution.","marker":"33"},{"why":"Shows thin-film lithium-niobate MZMs beyond 400 Gbps per wavelength, the alternative platform whose integration barriers motivate a silicon answer.","marker":"34"},{"why":"Defines the self-biasing technique for depletion-mode silicon microring modulators that the paper's zero-bias mode relies on.","marker":"37"},{"why":"Establishes the optical-peaking model for ring modulators; the paper explicitly designs to avoid peaking, and this reference anchors that design choice.","marker":"38"},{"why":"Provides the small-signal electro-optic bandwidth relation combining optical and electrical bandwidths in quadrature, used as the design formula.","marker":"40"}],"fun_headline_variants":["Trench-doped silicon ring hits 400 Gbps per wavelength","Foundry-made ring modulator achieves 400 Gbps for AI","Sub-fJ silicon ring delivers 400 Gbps optical links","Dual-mode silicon ring powers 400 Gbps interconnects","Wafer-scale silicon ring reaches 400 Gbps for compute"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The 400-Gbps-per-wavelength figure is based on open eyes after digital equalization and 16x averaging through a test bench limited to roughly 55 GHz, with no bit-error measurement at that rate; the claim assumes the microring, not the test bench or the DSP, is the limiting component.","fun_headline_variants_meta":{"raw":{"variants":["Trench-doped silicon ring hits 400 Gbps per wavelength","Foundry-made ring modulator achieves 400 Gbps for AI","Sub-fJ silicon ring delivers 400 Gbps optical links","Dual-mode silicon ring powers 400 Gbps interconnects","Wafer-scale silicon ring reaches 400 Gbps for compute"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001068,"raw_usage":{"total_tokens":4383,"prompt_tokens":886,"completion_tokens":3497,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":630,"completion_tokens_details":{"reasoning_tokens":3410}},"tokens_in":630,"tokens_out":3497,"duration_ms":30703,"temperature":1.0,"reasoning_tokens":3410,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T12:25:03.985798+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same 400-Gbps PAM6 transmission with a higher-bandwidth AWG above 80 GHz and a wideband receiver, then count bit errors at a forward-error-correction threshold rather than relying on an averaged open eye. If the bit-error rate cannot be met without aggressive equalization, or if the electrical and optical eyes diverge once the bench bandwidth is lifted, the device is not actually 400-Gbps capable.","supporting_citations":[{"cited_title":"An 8 × 160 Gb s −1 all -silicon avalanche photodiode chip,","cited_arxiv_id":null,"evidence_quote":"Supplies the prior athermal silicon modulator operating at 0.5 Vpp with roughly 25 GHz bandwidth, the low-voltage benchmark the self-biasing mode must outperform."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Demonstrates a 5 x 200 Gbps silicon microring chip, the multi-ring density benchmark this WDM scaling proposal extends."},{"cited_title":"A 240 Gb/s PAM4 Silicon Micro-Ring Optical Modulator,","cited_arxiv_id":null,"evidence_quote":"Shows 540-Gbps single-wavelength transmission from an InP EML, the competing technology whose CMOS-compatibility gap motivates a silicon solution."},{"cited_title":"Ultra -Wide Free- Spectral-Range Silicon Microring Modulator for High Capacity WDM,","cited_arxiv_id":null,"evidence_quote":"Shows thin-film lithium-niobate MZMs beyond 400 Gbps per wavelength, the alternative platform whose integration barriers motivate a silicon answer."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the self-biasing technique for depletion-mode silicon microring modulators that the paper's zero-bias mode relies on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Establishes the optical-peaking model for ring modulators; the paper explicitly designs to avoid peaking, and this reference anchors that design choice."},{"cited_title":"Self-biasing of carrier depletion based silicon microring modulators,","cited_arxiv_id":null,"evidence_quote":"Provides the small-signal electro-optic bandwidth relation combining optical and electrical bandwidths in quadrature, used as the design formula."}],"review_version":1}