{"id":"b493228c-de4f-470a-8048-efb0fb330166","arxiv_id":"2509.10409","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"high","formal_verification":"none","parameter_count":5,"one_line_summary":"InterPlace selects inter-chip coupler placements in modular quantum systems via a multi-objective cost model, cutting SWAPs and inter-chip operations by up to 33.3% and boosting simulated fidelity by up to 53.0%.","lead":"This paper introduces InterPlace, a framework that chooses where to place the physical couplers connecting separate quantum chips. It uses a cost model balancing distance, error rates, congestion, and layout constraints, and reports lower SWAP overhead and higher fidelity in simulated modular systems.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Evaluation compares only model-selected extremes, not a distribution; headline fidelity gain also uses inconsistent denominators, so reported improvements may be selection artifacts.","rationale":"I selected the baseline-selection issue as the most load-bearing because the paper's headline numbers are the main contribution, and the evaluation design makes them potentially unrepresentative. The reader's weakest_assumption focused on the realism of the simulated device model; while that is a valid transferability concern, it is conditional on the method working under the assumed model. A more immediate threat is that the evidence for the method working even under the assumed model is weak: the comparison against manually selected extremes of the same cost function does not demonstrate predictive validity across the placement space. The arithmetic inconsistency in the fidelity percentage compounds this, as it directly undermines a stated headline result. The proposed test—sampling a distribution of placements and computing rank correlation—would directly settle whether the cost model's ranking is meaningful. If the test passes, the paper's central algorithmic claim would be solid even though physical transfer remains conditional; if it fails, the paper's central claim is largely unsupported. Thus I do not change the reader's conditional verdict.","tokens_in":17630,"tokens_out":8589,"duration_ms":92304,"concrete_test":"For a fixed two-chip system (e.g., Auckland(27)+CairoV2(27)) and a 30-qubit QFT circuit, enumerate or randomly sample at least 100 distinct 4-link placements spanning the full cost range. For each placement, run the 5 compilers and record InterPlace cost, combined on-chip SWAPs+inter-chip ops, and fidelity. Compute Spearman rank correlation between cost and each metric across all placements, and report the percentile of InterPlace's placement in the random distribution. If the correlation is weak (|ρ|<0.5) or InterPlace is not in the top decile, the claim that lower cost yields lower overhead/higher fidelity is unsupported. Separately, recompute the QFT fidelity improvement as (0.17−0.08)/0.08 and report the corrected percentage.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central evidence (Figs. 7, 8, 10; Table 1) compares the 'lowest-cost' placement chosen by InterPlace against a single 'median-cost' and a single 'highest-cost' placement, both selected post hoc using the same cost model (Eq. 1). This does not establish that the cost model predicts real-world performance across the placement space; it only shows the model's own extreme rankings correlate. The 'highest-cost' placement may be a pathological outlier (e.g., all couplers on one high-error, congested qubit), inflating the 53.0% fidelity and 33.3% overhead gains relative to typical random placements. Moreover, the fidelity improvement for QFT is reported as 53.0% from 8% to 17%, which under the standard relative-change formula is 112.5%; the same section uses the old-fidelity denominator for Random(depth 30). With no error bars, seeds, or distribution over random placements, the headline numbers are not robust evidence for the central claim.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces InterPlace, a hardware-aware framework for selecting inter-chip coupler link placements in modular and chiplet quantum processors. The core contribution is a five-term cost model (Eq. 1) combining average path length, fidelity-aware effective path cost (via a Time-to-Fidelity model), congestion, qubit overload, and sparsity penalties. A constrained optimization procedure selects a fixed number of coupler links while respecting degree and spacing limits. The framework is implemented in Python/Qiskit and evaluated on simulated multi-chip systems built from IBM fake backends, with 5 compilers and 2–5 chips. The paper reports that lower InterPlace cost leads to fewer on-chip SWAPs and inter-chip operations and improved fidelity, with headline claims of up to 53.0% fidelity improvement and 33.3% reduction in combined operations.","tokens_in":17963,"tokens_out":3646,"duration_ms":45525,"significance":"If the central claim were robustly supported, InterPlace would make a useful contribution to architectural co-design for modular quantum systems, a topic of growing practical importance. The cost model is plausible and the paper demonstrates a working software pipeline across multiple compilers and moderately large simulated systems. The use of realistic IBM backend snapshots and several chip topologies is a strength. However, the empirical validation as presented does not currently establish that InterPlace cost values predict real routing/fidelity outcomes across the placement space, because the evaluation compares only extremes selected by the same model and lacks statistical controls. The paper's headline fidelity number is also arithmetically inconsistent.","major_comments":[{"comment":"The evaluation compares only three placements per configuration: 'lowest', 'median', and 'highest' cost, all selected using the identical cost model (Eq. 1) being validated. This is largely circular: it demonstrates that the model's own extremes differ, but not that the cost metric predicts real-world routing/fidelity performance across the placement space. To support the claim that lower cost causes lower SWAP overhead and higher fidelity, the authors should sample a distribution of random placements spanning the cost range, show a correlation (with error bars), and include multiple seeds and circuits. As reported, the head-to-head differences could be selection artifacts of the model's own ranking.","section":"§6.2.1, Fig. 7; §6.4, Fig. 10"},{"comment":"The headline fidelity improvement is reported inconsistently. For QFT, fidelity is said to increase from 8% (highest-cost) to 17% (lowest-cost), and the paper calls this a '53.0% increased'. The standard relative-change formula gives (17−8)/8 = 112.5%; the 53.0% figure uses the new value as denominator. This contradicts the immediately preceding Random(depth 30) example, which correctly reports (25−19)/19 = 31.6% using the old-fidelity denominator. The abstract and conclusion repeat the 53.0% claim. This arithmetic inconsistency must be corrected, and the claim should be recomputed with a stated, consistent convention.","section":"§6.4, Fig. 10 and Abstract"},{"comment":"For each configuration the paper appears to use a single random circuit (e.g., 'a random 40-qubit circuit', 'a random 30-qubit circuit', 'Random(60)', etc.) with no error bars, no multiple seeds, and no report of variance. Because routing and SWAP counts are highly circuit-dependent, a single instance cannot support claims such as 'consistently reduces' or 'reliably predicts'. At minimum, the authors should run several random circuits per configuration and report mean ± standard deviation, or per-instance scatter plots showing cost versus overhead.","section":"§6.1.5, §6.2, Table 1, Fig. 8"},{"comment":"The Time-to-Fidelity model contains a scaling factor λ in TTF_edge(e) = t_gate(e) + λ·ln(1/(1−ε_gate(e))). This λ directly controls the relative weight of gate error versus time in the effective path cost, and hence materially affects which coupler placements are selected. The evaluation settings state α=γ=δ=ε=1 and β=10, but never state the value of λ used in the experiments, nor any sensitivity analysis. Without this value the experimental results are not reproducible, and the claimed insensitivity to model parameters is unsubstantiated.","section":"§4.1.2, Eq. (4); §6.1.2"},{"comment":"The fidelity evaluation appears to assume independent per-gate errors, with SWAPs modeled as three CNOTs and coupler CNOTs fixed at 3.5% error / 235 ns. This independent-error model is a clean abstraction, but real multi-chip systems exhibit crosstalk, calibration drift, and correlated errors that can change the relative ranking of placements. The paper should explicitly state this assumption as a limitation and, ideally, perform a sensitivity analysis over the coupler error rate and latency to show that the qualitative conclusions are not artifacts of the particular simulated values. A single point estimate from the IBM Flamingo report is not sufficient to establish physical transferability.","section":"§6.1.4, §6.4"}],"minor_comments":[{"comment":"The +1 term for the inter-chip hop is constant for fixed n, as the paper notes. For clarity, this could be stated as an additive constant that does not affect optimization, and Eq. (2) could be simplified to suppress the constant when n is fixed.","section":"§4.1.1, Eq. (2)"},{"comment":"The text says 'an n×n cost matrix', but there are |V_A| × |V_B| candidate pairs; n×n is misleading unless n here denotes the number of candidate links. Please clarify the notation.","section":"§5.2, Phase 1"},{"comment":"The caption says 'Each category shows ten bars: the first five are InterPlace results... the last five are the matched baseline', but the figure appears to show six groups with ten bars each. The caption and figure should be aligned.","section":"§6.4, Fig. 10 caption"},{"comment":"The paper does not state the random seed(s) used for circuit generation, baseline placement selection, or solver stochasticity, nor does it mention plans for releasing code. This hampers reproducibility; please provide seeds or an artifact appendix.","section":"General"},{"comment":"Typos and minor wording issues include 'a more challeng set setting' (§6.2.1), 'Inter-Chip' inconsistency, and 'the Inter-chip coupler operations directly fidelity' (§6.4). A careful proofread is needed.","section":"Various"}],"recommendation":"major_revision","confidential_remarks":"The paper fits the journal's scope and the proposed cost model is a plausible starting point for inter-chip coupler placement. The main concern is that the validation is substantially circular and statistically underpowered; the headline fidelity improvement is arithmetically wrong as stated. These are fixable with a more rigorous evaluation (distribution of placements, multiple seeds, corrected percent-change reporting, and stated λ), so I do not recommend rejection, but the current empirical evidence cannot support the claims as written."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Zefan Du et al. propose InterPlace, a framework for choosing which qubits get inter-chip couplers in modular/chiplet quantum systems. The idea is genuinely new: instead of fixing the coupler map and optimizing the compiler, they optimize the hardware connectivity itself, at design time, using a multi-objective cost model. That is a useful framing, and the paper is the first I've seen to treat coupler placement as an optimizable design variable with compiler-aware validation.\n\nThe cost model (Eq. 1) is reasonable: average path length, a TTF-based fidelity-aware latency, congestion, degree limits, and sparsity. The TTF transformation (latency + lambda * log(1/(1-error))) is sensible, and the greedy + local refinement workflow is practical. They evaluate across five compilers, multiple chip sizes/counts, and both homogeneous and heterogeneous systems. That is a substantial amount of work, and the direction deserves attention.\n\nThe empirical support, however, has three problems. First, the baselines are chosen post hoc from the same cost model: the 'median' and 'highest' cost placements are selected after seeing the model's ranking. That does not test the model's predictive power; it only shows that the model's own extremes differ. A random sample of placements, or at least several seeds, would be needed to establish that cost ordering predicts actual SWAP/fidelity ordering. Second, the headline '53.0% fidelity improvement' is arithmetically inconsistent: 8% to 17% is a 112.5% relative gain using the old denominator (or 52.9% using the new one), but the same section uses the old denominator for Random(depth 30) (19% to 25% is 31.6%). So the percentages are not computed consistently. Third, key parameters are missing: lambda (the TTF scaling factor) is never specified, and D_max, delta, and eta are not given values. Without them, the cost model cannot be reproduced. Also, there are no error bars or seeds; each configuration appears to use a single random circuit. That makes the quantitative claims fragile.\n\nThese are fixable. The central argument—that cost-guided coupler placement reduces SWAP overhead and improves fidelity—is plausible and the data roughly support it, but the current evidence doesn't let you distinguish the model's guidance from the luck of picking two extreme points.\n\nWho is this for? Hardware architects and compiler designers working on modular quantum systems. A reader interested in co-design will get a concrete framework and a set of cost terms worth borrowing. It is not a breakthrough, but it is a solid first step in a direction that will matter as multi-chip systems become common.\n\nRecommendation: yes, send it to peer review. It deserves referee time. The idea is new and the implementation is substantive, but the evaluation needs to be redone with a proper baseline distribution, consistent statistics, and full parameter disclosure. I would ask for major revision.","headline":"Plausible co-design idea for coupler placement, but the evaluation is circular and the headline 53% fidelity gain is arithmetically inconsistent; worth refereeing after a major revision.","tokens_in":18360,"tokens_out":4598,"would_cite":true,"duration_ms":45038,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"InterPlace selects inter-chip coupler placements with a multi-objective cost model that lowers on-chip SWAP and inter-chip operation counts, improving circuit fidelity by up to 53% on simulated multi-chip systems.","keywords":["quantum computing","modular quantum systems","chiplet architecture","inter-chip coupler placement","qubit mapping","cost model","time-to-fidelity","fidelity optimization"],"falsifier":"On a two-chip device with reconfigurable inter-chip couplers, measure the actual success probability of the same benchmark circuits under InterPlace-optimized placement and under a high-cost placement. If the optimized placement does not reliably yield higher measured fidelity, the cost model's ranking is not predictive of real hardware performance.","tokens_in":17591,"feed_emoji":"⚛️","tokens_out":7064,"duration_ms":68575,"temperature":0.7,"pith_summary":"InterPlace is a pre-fabrication framework for deciding where inter-chip couplers should connect qubits in modular or chiplet quantum systems. It models the placement choice as a constrained network design problem and scores candidate link sets with a weighted cost function that includes average routing distance, fidelity-aware latency, congestion, per-qubit degree limits, and spatial sparsity. The paper claims that lower InterPlace cost predicts fewer on-chip SWAP gates and inter-chip operations across several compilers, and that the lowest-cost placement yields up to 53.0% higher fidelity and 33.3% fewer combined operations than high-cost baseline placements. These claims matter because current design practice treats coupler placement as a packaging decision rather than something that co-optimizes with compiler behavior; if the cost model is right, chip architects can choose link locations before fabrication and let compilers benefit immediately.","feed_headline":"Coupler-placement optimizer lifts quantum fidelity by up to 53%","feed_subtitle":"A pre-fabrication cost model weighing latency, errors, and congestion picks chip-to-chip links that reduce SWAPs and inter-chip operations.","key_machinery":"The central mechanism is the multi-objective cost model (Eq. 1), whose five terms encode routing efficiency (Average Path Length), noise- and latency-aware communication quality (Effective Path Cost via Time-to-Fidelity), spatial congestion, per-qubit degree overload, and endpoint sparsity. The Time-to-Fidelity metric converts gate time and error rate into a single effective delay, t + λ ln(1/(1−ε)), which is precomputed with Dijkstra's algorithm on each chip's graph and then averaged per candidate endpoint. The greedy-plus-refinement solver enforces hard constraints (maximum qubit degree D_max, minimum physical spacing δ, link budget n) and returns a link set L whose cost is claimed to corr","core_discovery":"InterPlace's central claim is that inter-chip coupler placement can be optimized before fabrication by minimizing a global cost function, and that doing so improves system-level performance in a way no compiler can fully recover later. Each candidate pair of qubits (u,v) across two chips is assigned a per-pair Time-to-Fidelity value, AvgTTFpair(u,v)=TTF_A(u)+TTF_coupler(u→v)+TTF_B(v), where TTF_A(u) is the average shortest TTF from all qubits in chip A to u, TTF_B(v) the analogous egress cost on chip B, and the coupler term is t_coupler + λ ln(1/(1−ε_coupler)). The optimization then selects n links minimizing the weighted sum of Average Path Length, Effective Path Cost, Congestion, Qubit Ove","pith_inferences":["The same cost function could be reused to compare coupler technologies, not just positions: by plugging in different latency/error figures for short-range vs. long-range links, the framework would output which physical link type deserves the higher link budget.","A natural extension is a closed loop with calibration: after a device is fabricated, measured error rates could re-run the solver to decide which of several spare couplers to activate, adapting placement to drift.","The TTF model treats errors as independent; adding measured crosstalk correlations to the edge weights or the congestion term could change the ranking of placements in dense layouts, and would be testable in the same simulator.","The reported fidelity gains are from circuits up to 30 qubits; scaling the fidelity simulation to larger circuits would test whether the advantage holds when SWAP overhead grows with system size."],"forward_implications":["Lower InterPlace cost consistently predicts lower combined on-chip SWAPs and inter-chip operations across multiple compilers and circuit families, so the cost model can be used as a pre-fabrication proxy for routing quality.","Increasing the number of inter-chip links does not automatically help; good placement is what converts extra couplers into lower overhead and higher fidelity, so link-budget decisions should be made jointly with placement.","The framework scales to larger systems: cost reductions persist when the number of chips grows from 2 to 5 and when chips grow to hundreds of qubits, suggesting placement optimization becomes more, not less, important in larger modular systems.","Because the search runs once at design time, the offline cost is amortized over all future circuits and compilers, making it practical to include in the hardware design flow.","Fidelity improvements are largest in circuits with many two-qubit operations (e.g., the quantum Fourier transform), where reducing SWAP and inter-chip gates directly cuts error accumulation."],"fun_headline_variants":["Pre-fab coupler placement boosts quantum fidelity 53%","Link placement model reduces SWAPs 33%, lifts fidelity","Optimizing chip links improves distributed quantum circuits","InterPlace: link selection raises fidelity 53%"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The ranking of coupler placements depends on the assumed gate-error and latency numbers fed into the Time-to-Fidelity metric; if the real chip-to-chip couplers have different error rates or correlated noise, the selected placements may not be the best on actual hardware.","fun_headline_variants_meta":{"raw":{"variants":["Pre-fab coupler placement boosts quantum fidelity 53%","Link placement model reduces SWAPs 33%, lifts fidelity","Optimizing chip links improves distributed quantum circuits","InterPlace: link selection raises fidelity 53%"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000302,"raw_usage":{"total_tokens":1586,"prompt_tokens":765,"completion_tokens":821,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":509,"completion_tokens_details":{"reasoning_tokens":756}},"tokens_in":509,"tokens_out":821,"duration_ms":9562,"temperature":1.0,"reasoning_tokens":756,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-04T17:51:34.771199+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On a two-chip device with reconfigurable inter-chip couplers, measure the actual success probability of the same benchmark circuits under InterPlace-optimized placement and under a high-cost placement. If the optimized placement does not reliably yield higher measured fidelity, the cost model's ranking is not predictive of real hardware performance.","supporting_citations":[],"review_version":1}