{"id":"f10cb4e4-ee40-4b07-a9c6-9f3cbe527bfc","arxiv_id":"2607.06600","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":6.0,"correctness_risk":"low","formal_verification":"none","parameter_count":5,"one_line_summary":"Under a 1 MB activation budget, an F-Clip-style center-length-angle CNN with int8 QAT, TTA, and a LoI verifier reaches sAP10=24.1 on ShanghaiTech Wireframe.","lead":"MiLSD is a tiny neural line-segment detector that runs inside 1 MB of MCU SRAM and reaches sAP10=24.1 on Wireframe. It maps which output encodings, bit-widths, and post-processing steps actually work when memory is the hard limit.","discovery_kind":"new_application","skeptic_critique":{"model":"grok-4.5","headline":"No significant objection identified beyond the reader's already-flagged hardware-confirmation gap.","rationale":"The paper's strongest claim is carefully scoped: under a sub-megabyte (ultimately 1 MB) activation budget, F-Clip is the best small-model representation, int8 is essentially free, and staged post-processing lifts Wireframe sAP10 from 10.6 to 24.1. Those numbers rest on standard Wireframe evaluation, clear ablations, and released code; they do not require on-device FPS to be true. The reader's weakest assumption correctly isolates the only open binding constraint (software-measured arena vs. real H7 SRAM). Because that gap is already acknowledged by the authors and already drives the CONDITIONAL verdict, no further load-bearing concern appears. A hardware confirmation run would close the remaining condition without altering the scientific substance of the representation/quantization study. Therefore the verdict stays CONDITIONAL and agreement with the reader is full.","tokens_in":15487,"tokens_out":553,"duration_ms":5010,"concrete_test":"Export the exact 0.39 M-parameter int8 MiLSD graph (with LoI head) through X-CUBE-AI / ST Edge AI for STM32H7, report measured peak activation arena and single-view + TTA4 latency on silicon; if peak arena exceeds ~1 MB or requires external memory, the 1 MB operating-point claim weakens while the sAP ablations remain intact.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is an engineering accuracy–memory map under a stated 1 MB activation budget, not a claim of GPU-competitive accuracy or of already-measured silicon FPS. Representation ablations (heatmap 0.3 / endpoint 3.6 / F-Clip 10.6 at 25k params), int8 vs int4 sensitivity (especially angle heads), capacity scaling to ~0.39 M params (sAP10 17.8), and staged inference gains (sub-pixel 18.1, TTA4 21.0, LoI 24.1) are internally consistent, transparent, and supported by released code. The only soft spot is the one the reader already named: Section V-E explicitly defers on-device arena and latency confirmation to ST Edge AI / X-CUBE-AI and reports only software-measured peaks. That does not undermine the sAP numbers or the representation/quantization conclusions; it merely leaves the final SRAM/latency binding unclosed. No hidden circularity, no misstated metric, and no evidence that the F-Clip or LoI gains are artifacts.","agreement_with_reader":"agree"},"referee_report":{"model":"grok-4.5","summary":"The paper studies line-segment detection under sub-megabyte MCU memory budgets. It compares three output encodings (heatmap, center+displacement, F-Clip center+length+double-angle) on a compact fully-convolutional backbone, shows that F-Clip is most effective at ~25k parameters (sAP10=10.6 on ShanghaiTech Wireframe), and reports that int8 quantization preserves fp32 accuracy while int4 collapses especially on the (cos2θ,sin2θ) head, with QAT only partially recovering. Scaling the backbone to ~0.39M parameters under a ~1 MB activation arena and adding sub-pixel decoding, 4-view TTA, and a frozen-backbone Line-of-Interest verifier yields MiLSD at sAP10=24.1. The work positions itself as an accuracy–memory map for embedded vision rather than a competitor to GPU parsers, and releases code.","tokens_in":15823,"tokens_out":1139,"duration_ms":11097,"significance":"If the reported trade-offs hold, the paper fills a previously empty MCU column in the line-detection literature: no prior learned detector is evaluated under sub-megabyte SRAM with an int8/int4 study. The representation ablation (heatmap 0.3 → endpoint 3.6 → F-Clip 10.6 at fixed 25k params), the angle-head sensitivity to 4-bit quantization, and the staged inference gains (17.8 → 18.1 → 21.0 → 24.1) are concrete, falsifiable engineering results on the standard Wireframe split and sAP metric. Released code and the explicit accuracy–resource frontier (Table IV, Fig. 9) are genuine strengths for TinyML geometric vision. The absolute accuracy remains far below GPU parsers, which the authors correctly treat as a regime limit rather than a failure.","major_comments":[{"comment":"Section V-E states that on-device arena and latency 'must be confirmed with ST Edge AI' and reports only software-measured peaks (~1 MB activation arena, ~0.54 MB weights). The central claim is an accuracy–memory map under a 1 MB budget on STM32H7; without measured peak SRAM, wall-clock FPS, and power on silicon (or an explicit X-CUBE-AI arena dump), the binding constraint remains unverified. This does not invalidate the sAP or quantization results, but it is load-bearing for the deployment claim and should be closed or clearly demoted to a software estimate.","section":null},{"comment":"Table V and Section V-C: the LoI verifier is trained with the backbone frozen and contributes the largest single gain (+3.1 sAP10). The paper does not report an ablation of verifier capacity, pooling density (32 points), or training labels (one-to-one matching), nor whether the verifier was quantized to int8 with the backbone. Because the 24.1 figure is the headline MiLSD number, a short sensitivity check or confirmation that the head fits inside the same arena under int8 is needed to make the staged gains fully reproducible.","section":null}],"minor_comments":[{"comment":"Abstract and Section IV-A: the abstract says F-Clip reaches 10.6 at 25k params, while the narrative climb in IV-A first quotes 7.2 then 10.6 after data/aug/epochs; a single consistent baseline number in the abstract and Fig. 5 caption would avoid confusion.","section":null},{"comment":"Fig. 5 y-axis and caption: the progression mixes representation changes with capacity and post-processing; labeling which bars share the same backbone width would make the representation-only claim clearer.","section":null},{"comment":"Table III: heatmap row notes that sAP is not the right metric and reports Q2/recall instead; either move heatmap to a separate classical-style evaluation or drop sAP for that row entirely to avoid mixing metrics.","section":null},{"comment":"Section II-A: the double-angle encoding is well motivated, but the loss weighting (2.0 on geometric terms) and masking are only in Table II; a one-sentence justification in the text would help.","section":null},{"comment":"Fig. 9 / Table IV: parameter counts for prior work are taken from LINEA and papers; a footnote that some counts are approximate (e.g., HAWPv2 ~11M) would be more precise.","section":null},{"comment":"Typos / polish: 'improvessAP' (abstract), 'On MCU?' column consistency, and a few missing spaces around sAP subscripts in the text.","section":null}],"recommendation":"minor_revision","confidential_remarks":"The hardware-confirmation gap is real but already flagged by the authors; requiring measured STM32H7 numbers is reasonable for a systems venue and should not block the representation/quantization contributions if the authors either measure or clearly reframe the 1 MB claim as a software arena bound. Fit for a TinyML / embedded-vision track is good; less so for a pure CV accuracy venue."},"author_rebuttal":null,"desk_editor":{"model":"grok-4.5","letter":"Punchline: this is the first paper that actually puts a learned line-segment detector inside a sub-megabyte MCU activation budget and measures what you get. They move Wireframe sAP10 from 10.6 (25k params, ~0.25 MB) to 24.1 inside ~1 MB with F-Clip, int8, sub-pixel decode, TTA, and a small LoI verifier. That fills the empty MCU cell between classical LSD/EDLines and phone/GPU parsers.\n\nWhat is new and solid is the systems map, not a new geometric theory. The representation climb at fixed tiny capacity (heatmap 0.3 → endpoint 3.6 → F-Clip 10.6) is clean and the right experiment for this regime. The quantization table is useful: int8 ≈ fp32; int4 PTQ collapses, especially on (cos 2θ, sin 2θ); QAT only partially recovers. Capacity scaling to ~0.39 M params and the staged inference gains (17.8 → 18.1 → 21.0 → 24.1) are transparent. They do not claim GPU parity. Code is released. Citations and the sAP protocol look standard; nothing is circular against Wireframe GT.\n\nSoft spot, in proportion: Section V-E still defers on-device arena and latency to ST Edge AI / X-CUBE-AI and reports software-measured peaks. That does not break the sAP or representation/quantization conclusions; it leaves the final SRAM/latency binding unclosed. Absolute accuracy stays far below HAWP/M-LSD-class numbers, which the authors own. Free parameters (widths, loss weight, LoI pooling) are normal engineering knobs, not hidden fitting of the metric.\n\nWho it is for: TinyML and embedded vision people who need a realistic operating point for SLAM/inspection on Cortex-M, not another transformer wireframe parser. The ablations are worth reading even if silicon FPS later moves a bit.\n\nI would send this to peer review. Engage if you care about MCU vision; treat the 1 MB claim as software-estimated until hardware numbers land.","headline":"First careful accuracy–memory map for learned line detection under real MCU SRAM; clean ablations, deferred silicon numbers, no circularity.","tokens_in":16468,"tokens_out":541,"would_cite":true,"duration_ms":14836,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.5","headline":"Under a one-megabyte activation budget, a compact int8 CNN with F-Clip encoding can reach sAP10 of 24.1 for line segments on microcontrollers.","keywords":["line segment detection","TinyML","quantization","memory-constrained inference","embedded vision","F-Clip","MCU","wireframe parsing"],"falsifier":"Export the exact int8 MiLSD graph through the vendor tool chain, flash it on a bare STM32H7, and measure peak SRAM occupancy together with Wireframe sAP10; if peak memory exceeds the 1 MB envelope or accuracy falls well below 24.1, the central resource claim fails.","tokens_in":16381,"feed_emoji":"📐","tokens_out":975,"duration_ms":22931,"temperature":0.7,"pith_summary":"Learned line-segment detectors have been accurate only on phones and GPUs, while classical detectors fit tiny hardware but pick up every edge. This paper asks how much structural accuracy is possible when peak activation memory is capped below one megabyte. It shows that a center-length-angle encoding learns far better than heatmaps or endpoint offsets at tiny model sizes, that 8-bit quantization preserves full-precision quality while 4-bit does not, and that sub-pixel decoding, flip averaging, and a small verification head can lift a 25k-parameter baseline from sAP10 of 10.6 to 24.1 once the budget grows to roughly 1 MB. The point is not to beat GPU parsers; it is to chart the real accuracy–memory frontier so embedded vision systems can place a learned wireframe detector on low-cost MCUs.","feed_headline":"MCU line detector hits sAP 24.1 inside 1 MB memory","feed_subtitle":"F-Clip encoding, int8, and a tiny verifier chart the accuracy–memory frontier for embedded vision","key_machinery":"F-Clip center-with-length-and-angle encoding: each segment is a center peak plus length and (cos 2θ, sin 2θ) on a 128×128 grid, decoded by peak NMS and optional sub-pixel fit, then re-scored by a tiny Line-of-Interest MLP that pools features along the candidate.","core_discovery":"At extreme memory limits the choice of output representation dominates capacity: the F-Clip formulation (center confidence, length, and double-angle orientation) is the only encoding that yields coherent segments with a 25k-parameter fully-convolutional backbone. Eight-bit quantization preserves that performance; four-bit quantization collapses angle regression even under quantization-aware training. Scaling the same backbone to a ~1 MB activation arena and adding only inference-time refinements (sub-pixel peaks, four-view TTA, and a lightweight Line-of-Interest verifier) raises sAP10 on ShanghaiTech Wireframe from 10.6 to 24.1, placing the first learned line detector inside microcontroller","pith_inferences":["Angle and other continuous geometric heads may systematically demand higher bit-width than classification maps in TinyML vision, so mixed-precision or specialized encodings for orientation could be the next lever.","The same three-axis map (representation, bit-width, post-processing) can be reused for other sparse geometric primitives—junctions, vanishing points, or short arcs—on the same MCU class.","Classical edge walkers may still win pure latency contests; MiLSD defines a learned niche rather than a universal replacement."],"forward_implications":["F-Clip-style geometric heads should be the default starting point for any new sub-megabyte line detector.","Int8 is a safe deployment target; sub-8-bit designs for angle regression need new encodings or training methods.","Accuracy can be roughly doubled after training by memory-neutral post-processing (sub-pixel, TTA, small verifier) without enlarging the stored network.","The previously empty MCU column in the line-detector table is now occupied, so future TinyML geometric work has a concrete accuracy–memory reference curve."],"fun_headline_variants":["MiLSD hits sAP 24.1 line detection inside 1 MB on MCU","F-Clip lets 25k-param net reach sAP 24.1 under 1 MB","Int8 MiLSD raises Wireframe sAP10 from 10.6 to 24.1","Sub-MB F-Clip detector charts embedded line accuracy","MiLSD: coherent MCU lines via center-length-angle encoding"],"cache_read_input_tokens":128,"weakest_assumption_plain":"The claim that the whole pipeline stays inside roughly 1 MB of real STM32H7 SRAM and runs usefully rests on software-measured activation arenas that the paper itself says still need on-device confirmation.","fun_headline_variants_meta":{"raw":{"variants":["MiLSD hits sAP 24.1 line detection inside 1 MB on MCU","F-Clip lets 25k-param net reach sAP 24.1 under 1 MB","Int8 MiLSD raises Wireframe sAP10 from 10.6 to 24.1","Sub-MB F-Clip detector charts embedded line accuracy","MiLSD: coherent MCU lines via center-length-angle encoding"]},"model":"grok-4.5","effort":"low","cost_usd":0.00658,"raw_usage":{"total_tokens":1702,"prompt_tokens":860,"num_sources_used":0,"completion_tokens":113,"cost_in_usd_ticks":65800000,"prompt_tokens_details":{"text_tokens":860,"audio_tokens":0,"image_tokens":0,"cached_tokens":128},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":729,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":860,"tokens_out":113,"duration_ms":7695,"temperature":1.0,"reasoning_tokens":729,"cache_read_input_tokens":128,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-11T03:21:49.900037+00:00","model_set":{"reader":"grok-4.5"},"falsifier":"Export the exact int8 MiLSD graph through the vendor tool chain, flash it on a bare STM32H7, and measure peak SRAM occupancy together with Wireframe sAP10; if peak memory exceeds the 1 MB envelope or accuracy falls well below 24.1, the central resource claim fails.","supporting_citations":[],"review_version":1}