{"id":"93a8cfd1-fb5e-489b-8462-b772e4433b81","arxiv_id":"2607.06881","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"unknown","formal_verification":"none","parameter_count":2,"one_line_summary":"Multiple double matrix multiplication on FP64 tensor cores is achieved by splitting doubles into 13-bit quarters with trailing zeros, enabling error-free inner products without branching renormalization.","lead":"This paper shows how to perform high-precision arithmetic (multiple doubles) on NVIDIA tensor cores by splitting numbers into bit-aligned parts, avoiding branching. It matters because tensor cores are much faster than regular GPU cores, and this could accelerate scientific computing tasks needing extra precision.","discovery_kind":"new_method","skeptic_critique":{"model":"glm-5.2","headline":"The 13.75 TFLOPS headline comes from the top-down method without full-pipeline timing or accuracy validation, while the bottom-up method that reports both shows the tensor core pipeline is 3–4x slower than regular CUDA cores.","rationale":"The reader correctly identified the performance disconnect and the lack of accuracy validation for the top-down method in the rationale, but placed the weakest_assumption on the balancing algorithms' formal correctness. While the balancing proofs are indeed missing, the empirical ε_max values in Table 1 suggest the accuracy is acceptable for random inputs, making this a secondary concern. The more load-bearing issue is the performance claim itself: the paper's headline number (13.75 TFLOPS) is an apples-to-oranges comparison that excludes the overhead that dominates the one method where full timing was reported. The bottom-up results in Table 1 are the strongest evidence in the paper, and they show the opposite of acceleration. The CONDITIONAL verdict is appropriate — the core idea (quartering with trailing zeros, Ozaki-style rewriting) is sound and the code is public, but the central claim of acceleration is not substantiated by the paper's own data. The paper would need to either (a) report full-pipeline timing for the top-down method showing it beats t_CUDA, or (b) reduce the overhead of matrix construction and reassembly to make the bottom-up method competitive. The concern is concrete and falsifiable: a single end-to-end timing of the top-down method with accuracy validation would settle it.","tokens_in":8451,"tokens_out":1670,"duration_ms":47702,"concrete_test":"Run the top-down method end-to-end on the same matrix sizes as Table 1 (n=1024, 2048, 3072, 4096 for double-double), measuring total wall-clock time including all steps: quartering, balancing, matrix construction, dmmaTensorCoreGemm execution, and reassembly into double-double output. Simultaneously compute ε_max against the CUDA-core reference. If the full-pipeline time exceeds t_CUDA from Table 1 (as the bottom-up method does), or if ε_max is significantly worse than the bottom-up values, the headline acceleration claim does not hold.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The paper's central performance claim — that tensor cores accelerate multiple double arithmetic (13.75 TFLOPS > 9.7 TFLOPS) — rests on the top-down method (§4.3), which reports only the raw dmmaTensorCoreGemm performance with shared memory. The paper does not report a full-pipeline timing for this method that includes the costs of splitting doubles into quarters, constructing the enlarged A and B matrices, applying balancing algorithms, and reassembling results. These overhead costs are precisely what doomed the bottom-up method: Table 1 shows t_TC (which includes construction, kernel execution, and reassembly) is 3–4x slower than t_CUDA for all tested sizes, despite the WMMA kernel alone being extremely fast (t_WMMA ≈ 0.0001s). For n=1024 double-double, t_TC=0.38s vs t_CUDA=0.097s. The paper itself attributes this to the size explosion of A and B ('the size of A, B' causes t_TC to grow faster than t_CUDA). Since the top-down method uses the same quartering and matrix expansion (Table 2 shows 8192×4096 for a 1024×512 double-double input), there is no reason to expect its full-pipeline timing to differ qualitatively from the bottom-up results. The 13.75 TFLOPS figure is therefore not comparable to the 9.7 TFLOPS regular-core figure: the former excludes overhead that the latter includes. Additionally, no accuracy data (ε_max) is reported for the top-down method, so we cannot confirm it achieves double-double accuracy. The bottom-up method does report ε_max, and the values look reasonable (3.5E-28 ≈ 2^{-91} for double-double at n=1024), but that method is the one that loses on performance.","agreement_with_reader":"partial"},"referee_report":{"model":"glm-5.2","summary":"The paper proposes a method for performing multiple double arithmetic on NVIDIA FP64 tensor cores, which are specialized for matrix multiplication and unsuited to the branching required by renormalization. The core idea is to partition each double into 13-bit quarters with trailing zero bits, rewrite the product of two multiple-double matrices as a single product of enlarged double matrices, and execute it on tensor cores. The approach is inspired by the Ozaki scheme. The paper presents both a bottom-up method (custom WMMA kernel) and a top-down method (adapted dmmaTensorCoreGemm), reporting 13.75 TFLOPS on an A100 for the latter.","tokens_in":8755,"tokens_out":1185,"duration_ms":145334,"significance":"The central technical idea—using 13-bit quartering with 26 trailing zero bits to enable exact inner products on tensor cores (Section 2, Eq. 5)—is clean and well-motivated. The overflow bound N = 67,108,865 is a direct and useful calculation. The software is released under GPL on GitHub, which supports reproducibility. The problem is timely given the growing interest in mixed-precision and extended-precision arithmetic on accelerators.","major_comments":[{"comment":"§4.3: The headline performance claim of 13.75 TFLOPS is reported for the top-down method using dmmaTensorCoreGemm with shared memory, but this figure appears to measure only the raw matrix multiply kernel. The paper does not report full-pipeline timing for the top-down method that includes the costs of splitting doubles into quarters, constructing the enlarged A and B matrices (8192×4096 per Table 2), applying balancing algorithms, and reassembling results. These overhead costs are precisely what caused the bottom-up method to be 3–4x slower than regular CUDA cores (Table 1: t_TC vs t_CUDA). Since the top-down method uses the same quartering and matrix expansion, there is no reason to expect its full-pipeline timing to differ qualitatively. The comparison '13.75 > 9.7' is therefore not apples-to-apples: the 9.7 TFLOPS figure for regular CUDA cores includes all overhead, while the 13.75 T","section":null},{"comment":"§4.3: No accuracy validation (ε_max) is reported for the top-down method. The bottom-up method reports ε_max in Table 1 (e.g., 3.5E-28 for n=1024 double-double), but the top-down method, which produces the headline performance number, has no corresponding accuracy data. Without this, the reader cannot confirm that the top-down method actually achieves double-double accuracy.","section":null},{"comment":"§3, Problems 3.1–3.4: The balancing algorithms are described informally through problem-solution pairs but lack formal proofs of correctness or termination. Problem 3.4 acknowledges worst-case exponent gaps (e.g., -25, -38, -51) and proposes corrective steps (Eq. 8), but it is not shown that these corrections always converge to grid-aligned exponents for arbitrary inputs. Additionally, Section 4.1 states that only random numbers were used in experiments. Adversarial inputs (e.g., numbers with maximal exponent gaps, cancellation scenarios) would stress the balancing algorithms and provide evidence for or against their robustness.","section":null}],"minor_comments":[{"comment":"§2: The notation in Eqs. (1)–(3) uses subscripts like a_{i,k,0} but the matrix A_{i,k} in Eq. (2) is written with a transpose that may confuse readers; clarifying whether the transpose applies to the column vector or the indexing would help.","section":null},{"comment":"Table 1: The units for ε_max are not specified. Are these absolute errors or relative errors? Adding units or a reference to the double-double precision range would contextualize the values.","section":null},{"comment":"§4.2: The bottom-up method reports f_WMMA and f_CUDA in teraflops, but the basis for the FLOP count (e.g., 2n³ for n×n matrix multiply) is not stated. Clarifying the formula used would make the performance figures verifiable.","section":null},{"comment":"§3, Problem 3.3: The corrective step in Eq. (7) assumes x_h > 0. The case x_h < 0 is not discussed; presumably the sign is handled symmetrically, but stating this explicitly would be clearer.","section":null},{"comment":"The abstract states the software is available 'under the GPU GPL license'; this should likely be 'GPL license' or specify the version (e.g., GPL v3).","section":null},{"comment":"§1: The phrase 'multiple the accuracy' should be 'multiply the accuracy'.","section":null}],"recommendation":"major_revision","confidential_remarks":"The stress-test concern about the 13.75 TFLOPS figure being an incomplete measurement is well-founded and is the most important issue. The paper's own bottom-up data (Table 1) essentially undermines the headline claim by showing that pipeline overhead dominates. The authors need to either (a) report full-pipeline timing for the top-down method, or (b) reframe the contribution as a methodological exploration rather than a demonstrated performance win. The lack of accuracy data for the top-down method is also a significant gap. If these are addressed, the paper could be a solid contribution."},"author_rebuttal":null,"desk_editor":{"model":"glm-5.2","letter":"The core idea is sound and the code is public, but the headline 13.75 TFLOPS number is not comparable to the 9.7 TFLOPS regular-core figure it's measured against. That's the main thing to know about this paper.","headline":"The core idea is sound but the headline performance number is apples-to-oranges.","tokens_in":9338,"tokens_out":107,"would_cite":false,"duration_ms":58836,"reading_group":"no","serious_thinker":"no","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"glm-5.2","headline":"Splitting doubles into 13-bit quarters unlocks tensor cores for extended precision","keywords":[],"falsifier":"An input matrix containing doubles whose quarter exponents fall into worst-case gaps (e.g., -25, -38, -51 as described in Problem 3.4) and for which the balancing corrections cascade without converging, causing the trailing-zero guarantee to break and introducing rounding errors into the tensor-core computation.","tokens_in":8688,"feed_emoji":"🧮","tokens_out":688,"duration_ms":125752,"temperature":0.7,"pith_summary":"The paper tackles a fundamental mismatch: multiple double arithmetic (representing numbers as unevaluated sums of doubles for extra precision) requires branching for renormalization after every operation, but tensor cores are pure matrix-multiply engines with no branching capability. The authors sidestep this by partitioning each 52-bit double fraction into four 13-bit quarters, each padded with 26 trailing zero bits. This padding guarantees that products and long inner products of quarters are computed exactly in standard double precision, because the results fit within the 52-bit fraction without overflow. A product of two double-double matrices is then rewritten as a single product of double matrices arranged in a block-convolution structure, which tensor cores can execute directly. The authors describe balancing algorithms that redistribute bits when input exponents deviate from the intended grid spacing, and report 13.75 TFLOPS on an A100 GPU for double-double matrix multiplication, exceeding the 9.7 TFLOPS theoretical peak of regular FP64 CUDA cores.","feed_headline":"13-bit quartering trick lets tensor cores do extended-precision math","feed_subtitle":"By splitting doubles into padded 13-bit pieces, matrix products gain double-double accuracy at 13.75 TFLOPS on A100 — faster than regular FP","key_machinery":"The quartering decomposition (splitting a 52-bit double fraction into four 13-bit quarters with 26 trailing zero bits each), the block-convolution rewrite mapping a product of double-double matrices into a single product of double matrices (equations 2-4), and the balancing algorithms of Section 3 that redistribute bits to keep quarter exponents on the grid {0, -13, -26, -39}.","core_discovery":"The central mechanism is the quartering decomposition: splitting each double's 52-bit fraction into four 13-bit pieces with 26 trailing zero bits each. This padding makes products of quarters exact in double precision and allows the renormalization step (which normally requires branching) to be deferred entirely, because no information is lost during the tensor-core matrix multiplication itself. The renormalization is then performed only once, after the matrix product is complete, as a massively parallel summation on regular cores. The product of two multiple-double matrices is rewritten as a single large double-precision matrix product using a block structure where one factor stacks quarter","pith_inferences":[],"forward_implications":[],"fun_headline_variants":["Splitting doubles into 13-bit quarters lets tensor cores do extended-precision math","Quartering trick turns A100 tensor cores into extended-precision multipliers","13-bit decomposition bypasses branching for tensor-core multiple-double math","Deferring renormalization lets tensor cores handle multiple-double arithmetic","Ozaki-style splitting makes tensor cores usable for multiple-double matrix products"],"cache_read_input_tokens":0,"weakest_assumption_plain":"The balancing algorithms are assumed to reliably force all quarter exponents onto the grid {0, -13, -26, -39} for arbitrary inputs, ensuring exact inner products. The paper acknowledges worst-case exponent gaps and proposes corrective bit-shuffling steps, but does not formally prove these corrections always terminate or guarantee exactness, and tests only random inputs rather than adversarial ones.","fun_headline_variants_meta":{"raw":{"variants":["Splitting doubles into 13-bit quarters lets tensor cores do extended-precision math","Quartering trick turns A100 tensor cores into extended-precision multipliers","13-bit decomposition bypasses branching for tensor-core multiple-double math","Deferring renormalization lets tensor cores handle multiple-double arithmetic","Ozaki-style splitting makes tensor cores usable for multiple-double matrix products","Quartering doubles into 13-bit pieces avoids branching on tensor cores","A100 tensor cores reach double-double accuracy via 13-bit fraction quartering","Splitting doubles into quarters defers renormalization off tensor cores"]},"model":"glm-5.2","effort":"low","cost_usd":0.0,"raw_usage":{"total_tokens":972,"prompt_tokens":414,"completion_tokens":558,"prompt_tokens_details":null},"tokens_in":414,"tokens_out":558,"duration_ms":21139,"temperature":1.0,"reasoning_tokens":468,"cache_read_input_tokens":0,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-09T23:37:43.503602+00:00","model_set":{"reader":"glm-5.2"},"falsifier":"An input matrix containing doubles whose quarter exponents fall into worst-case gaps (e.g., -25, -38, -51 as described in Problem 3.4) and for which the balancing corrections cascade without converging, causing the trailing-zero guarantee to break and introducing rounding errors into the tensor-core computation.","supporting_citations":[],"review_version":1}