{"id":"22c23fa3-424e-45df-be54-a588c0fd908e","arxiv_id":"2607.07577","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.5,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Area-ratio engineering of AlScN MFMIS gate stacks on GaN HEMTs yields record 27 V memory windows, 4-bit MLC arrays, multi-state inverters and the first GaN ferroelectric frequency-to-voltage converter.","lead":"Researchers built GaN transistors with ferroelectric AlScN gates whose electrode area ratio switches the same device between multi-bit non-volatile memory and analog signal processing. This could let high-power and RF GaN chips carry their own memory and converters instead of relying on separate silicon circuits.","discovery_kind":"new_method","skeptic_critique":{"model":"grok-4.5","headline":"High-ratio MW and forward SS claims rest on incomplete voltage-division accounting for 2DEG pinning and floating-electrode effects.","rationale":"The Reader correctly flags the voltage-division + permittivity model as the weakest assumption. The manuscript’s own data (incomplete depletion at high ratio, retention loss attributed to Q2DEG and floating-Pt conduction, series-resistance drop in Ion) already hint that the ideal series-capacitor picture is incomplete precisely where the largest MW and forward SS appear. This does not invalidate the experimental demonstrations of 4-bit arrays or the FVC, but it does leave the mechanistic attribution of “area-ratio engineering” as the sole design principle under-determined. Hence the verdict remains CONDITIONAL; no stronger rejection is warranted because the low-ratio memory results and the functional FVC waveforms stand independently of the exact voltage-partition model. The proposed intermediate-electrode voltage measurement is a direct, feasible check that would settle the issue.","tokens_in":16314,"tokens_out":574,"duration_ms":7004,"concrete_test":"Fabricate matched MFM capacitors (no 2DEG) and full MFMIS devices at SMIS/SMFM=8; extract P–V loops and C–V under identical bias, then compare measured VMFM (via intermediate-electrode voltage probe or Kelvin) against the formula prediction. If measured VMFM falls >15 % short of 0.97 VGS or if MW/SS collapse when floating-Pt leakage is blocked (e.g., by thicker insulator), the voltage-division account is incomplete and the dual-function claim weakens.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claim that area-ratio engineering alone unifies record MW (27 V) and forward SS (27 mV/dec) with dual memory/analog function rests on the capacitive division VMFM = VGS/(1+CMFM/CMIS) plus extracted εr (HfO2=19.3, AlScN=24) fully explaining 2DEG-pinned downward polarization and the observed dual behavior (energy-band diagrams and Eqs. after Fig. 1). At high ratios (4,8) the paper itself notes incomplete 2DEG depletion, larger required |VGS|, series resistance from extended LPt, and floating-Pt leakage that degrades erase retention after ~100 s (Figs. 3f, S3f). These unmodeled terms mean the simple capacitor network may not isolate pure ferroelectric voltage amplification; interface traps or leakage could contribute to the apparent MW enlargement and transient NC-like forward SS. Without quantitative separation, the design-knob narrative and “record” attributions remain under-supported for the high-ratio regime that enables the FVC.","agreement_with_reader":"agree"},"referee_report":{"model":"grok-4.5","summary":"The manuscript reports AlScN-based MFMIS ferroelectric GaN HEMTs in which the geometric area ratio SMIS/SMFM is varied (1, 2, 4, 8) by changing intermediate Pt electrode length. Capacitive voltage division is used to argue that higher ratios increase the fraction of VGS dropped across AlScN, producing a large memory window (up to 27 V), forward subthreshold swing of 27 mV/dec attributed to 2DEG-pinned polarization reversal, 4-bit multi-level cell operation with 4\times4 array uniformity at low ratios, and continuously tunable conductance at high ratios that enables multi-state inverters and a GaN ferroelectric frequency-to-voltage converter (0.5–500 Hz, 1.1 mV/Hz, R² = 0.97). TEM/EDS, bidirectional transfer curves, pulse maps, endurance/retention, array statistics, VTCs and FVC waveforms are presented to support dual memory/analog functionality on a single GaN platform.","tokens_in":16586,"tokens_out":1198,"duration_ms":12941,"significance":"If the dual-function claim holds, the work supplies a practical structural design knob (area ratio) that lets a single AlScN FeHEMT platform serve both high-density non-volatile storage and analog signal processing on a wide-bandgap technology already used for power and RF. The 4-bit MLC array data, low-VDS operation (0.5 mV), and first GaN ferroelectric FVC are concrete advances relative to prior GaN FeHEMTs and to Si/IGZO FeNAND benchmarks. The experimental breadth (four ratios, array maps, circuit demos) is a clear strength even if the electrostatic model remains incomplete.","major_comments":[{"comment":"Energy-band discussion and the two equations after Fig. 1: the central claim that area-ratio engineering alone produces the record MW (27 V) and forward SS (27 mV/dec) rests on VMFM = VGS/(1 + CMFM/CMIS) with εr(HfO2)=19.3, εr(AlScN)=24. At ratios 4 and 8 the paper itself reports incomplete 2DEG depletion, series resistance from extended LPt, and floating-Pt leakage that degrades erase retention after ~100 s (Figs. 3f, S3f). Without quantitative separation of pure ferroelectric voltage amplification from interface traps, leakage or series-resistance effects, the attribution of the high-ratio metrics and the FVC-enabling analog states remains under-supported.","section":null},{"comment":"Fig. 2d and abstract: the “record” MW of 27 V and forward SS of 27 mV/dec are extracted from high-ratio devices whose retention is already shown to be unstable (Figs. 3f, S3f). The manuscript should either (i) restrict the record claims to the low-ratio regime that actually retains data, or (ii) supply additional measurements (e.g., PUND under the same bias conditions, floating-electrode potential monitoring, or trap spectroscopy) that isolate ferroelectric switching from the unmodeled terms.","section":null},{"comment":"Figs. 5g–i and S6–S7: the FVC demonstration is novel, yet the bipolar Reset/Set scheme (1 V / –16 V) and the need for periodic re-initialization are presented without a quantitative model linking pulse frequency to fractional polarization. A short circuit-level analysis or SPICE-equivalent that predicts the observed 1.1 mV/Hz gain and R² = 0.97 would strengthen the claim that the converter is a direct consequence of area-ratio-engineered conductance states rather than an empirical pulse-train result.","section":null}],"minor_comments":[{"comment":"Fig. 2a and S2a: on-current and Ion/Ioff degrade with area ratio because of series resistance from LPt; this trade-off should be stated quantitatively in the main text rather than only in the SI.","section":null},{"comment":"Table S1: the comparison with Si/IGZO FeNAND is useful, but the VDS column for this work lists 0.005 V while the main text emphasizes 0.5 mV; align the numbers and note the corresponding current levels.","section":null},{"comment":"Notation: SMIS/SMFM is introduced without defining the geometric areas on the first occurrence; a brief parenthetical (SMIS = LPt × W, SMFM = LG × W) would help readers.","section":null},{"comment":"Fig. 1c TEM/EDS: the scale bar and layer thicknesses are hard to read; a higher-resolution inset or labeled thickness values would improve clarity.","section":null},{"comment":"References: several recent AlScN FeFET and GaN FeHEMT works (2024–2025) are cited; ensure the “first GaN-based ferroelectric FVC” claim is checked against any concurrent preprints.","section":null}],"recommendation":"major_revision","confidential_remarks":"The experimental data set is solid and the dual-function demonstration is of genuine interest for a materials/device journal. The main risk is over-attribution of high-ratio metrics to pure capacitive division; if the authors can either tighten the claims or add a modest set of control measurements, the paper should be publishable. Scope fit is good for a condensed-matter/materials journal that accepts device-oriented work."},"author_rebuttal":null,"desk_editor":{"model":"grok-4.5","letter":"This is a clean experimental device paper. The new piece is not AlScN FeHEMTs or MFMIS stacks—those already exist—but the systematic use of intermediate Pt length (area-ratio SMIS/SMFM = 1–8) as one process knob that deliberately splits the same gate stack into robust 4-bit MLC memory (low ratios) versus continuously tunable analog conductance (high ratios). They back it with transfer curves, pulse maps, 4×4 array statistics, multi-state VTCs, and the first GaN ferroelectric frequency-to-voltage converter (0.5–500 Hz, 1.1 mV/Hz, R²=0.97).\n\nWhat they do well: fabrication and electrical data are thorough. TEM/EDS confirm the stack; PUND loops show saturation; low-ratio devices give 12 V MW, 4-bit states, endurance to 1k cycles, retention >1k s, and good array uniformity even at VDS=0.5 mV. High-ratio devices deliver the analog demos. Voltage-division equations are standard electrostatics applied to measured εr values, not fitted to invent the MW. Citations cover prior GaN FeHEMTs and Si/IGZO FeNAND fairly; self-cites are process context. The dual-function claim is supported by the data they show.\n\nSoft spots are real but proportional. High-ratio devices (the ones that enable the FVC) show clear erase-state retention collapse after ~100 s, which the paper itself attributes to 2DEG depolarization field plus floating-Pt leakage. The simple capacitor network does not fully isolate pure ferroelectric amplification from series resistance, incomplete depletion, or interface effects at ratios 4 and 8; the forward SS=27 mV/dec and 27 V MW therefore rest partly on unmodeled terms. That weakens the clean “design-knob” narrative for the analog regime, but does not erase the measured dual behavior or the low-ratio memory results. No circular math, no invented entities.\n\nThis is for GaN device and power/RF integration people who care about on-chip NVM and analog blocks without silicon peripherals. It deserves a serious referee; the data are there, the caveats are visible, and the systems angle is concrete. I would engage.","headline":"Solid experimental device paper that turns intermediate-electrode length into a practical dual-use knob for AlScN FeHEMTs; records and first FVC are real, high-ratio retention is the soft spot.","tokens_in":17212,"tokens_out":574,"would_cite":true,"duration_ms":7130,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.5","headline":"Area-ratio engineering of AlScN gate stacks lets one GaN transistor family serve as both multi-bit memory and analog frequency converter.","keywords":["Ferroelectric HEMTs","AlScN","area-ratio","non-volatile memory","analog signal processing","MFMIS gate stack","frequency-to-voltage converter","GaN"],"falsifier":"Fabricate devices spanning the same area ratios but deliberately introduce a known interface trap density or floating-electrode leakage path and measure whether the claimed 27 V window, forward 27 mV/dec swing, and linear 0.5–500 Hz FVC response still appear as predicted by the pure capacitive-division model.","tokens_in":17233,"feed_emoji":"⚡","tokens_out":986,"duration_ms":11448,"temperature":0.7,"pith_summary":"GaN transistors dominate high-power and radio-frequency electronics, yet still rely on separate silicon chips for non-volatile memory and control. This paper shows that a single design knob—the area ratio of the metal-ferroelectric-metal-insulator-semiconductor gate stack—turns ferroelectric AlScN GaN HEMTs into devices that can be tuned for either dense multi-bit memory or continuous analog signal processing. By lengthening the intermediate electrode, more of the gate voltage drops across the ferroelectric, producing a 27 V memory window, sub-60 mV/dec switching even on the forward sweep, and 4-bit multi-level cells that remain uniform across a 4\times4 array. Larger ratios instead yield continuously tunable conductance that the authors use for multi-state inverters and the first GaN ferroelectric frequency-to-voltage converter, linear from 0.5 to 500 Hz. The result is a concrete path toward monolithic GaN systems that store configuration data and process analog signals on the same wide-bandgap platform already preferred for power and RF.","feed_headline":"One area-ratio knob turns GaN transistors into memory and analog converters","feed_subtitle":"Low ratios give 4-bit cells with 27 V windows; high ratios yield the first GaN ferroelectric frequency-to-voltage converter","key_machinery":"Area-ratio (SMIS/SMFM) capacitive voltage division: lengthening the intermediate Pt electrode increases the fraction of VGS that appears across the AlScN, amplifying polarization switching and, together with 2DEG-pinned downward polarization, simultaneously enlarges the memory window and enables partial, analog-like polarization states.","core_discovery":"Systematic scaling of the area ratio SMIS/SMFM in an AlScN-based MFMIS gate stack redistributes gate voltage so that low ratios (1–2) produce large, stable multi-bit memory windows while high ratios (4–8) produce continuously programmable conductance states usable for multi-state inverters and a linear frequency-to-voltage converter, all on the same GaN HEMT platform.","pith_inferences":["If the voltage-division model holds at higher frequencies, the same stack could be adapted for RF reconfigurable matching networks that store their own bias state.","The retention degradation seen only at high ratios suggests a materials path—thinner barriers or charge-blocking interlayers—that could push the analog regime into true non-volatile multi-state storage.","Because the intermediate electrode length is a lithographic parameter, foundry-compatible multi-project-wafer runs could offer designers a menu of memory versus analog FeHEMTs without process changes."],"forward_implications":["Low-ratio FeHEMTs can serve as high-density multi-bit non-volatile cells co-integrated with GaN power or RF stages, removing the need for separate silicon memory chips.","High-ratio devices enable single-transistor multi-state inverters and frequency-to-voltage converters on the same GaN wafer used for power switching.","The same area-ratio knob can be used to trade retention stability against continuous analog tunability within one process flow.","Monolithic GaN systems that store their own configuration data and perform local analog signal processing become architecturally feasible."],"fun_headline_variants":["Area-ratio AlScN stacks give GaN 27V multi-bit memory and F-to-V conversion","SMIS/SMFM ratio unifies 4-bit cells and analog converters on GaN HEMTs","Low ratios lock multi-level memory; high ratios enable GaN frequency-to-voltage","Area-ratio engineering turns GaN into memory cells plus multi-state inverters","One SMIS/SMFM knob yields record GaN memory window and linear F-V response"],"cache_read_input_tokens":128,"weakest_assumption_plain":"That the simple series-capacitor voltage-division formula, using only the measured dielectric constants of HfO2 and AlScN, fully explains the observed polarization pinning and dual memory/analog behavior without unmodeled traps, leakage or series resistance taking over at high ratios.","fun_headline_variants_meta":{"raw":{"variants":["Area-ratio AlScN stacks give GaN 27V multi-bit memory and F-to-V conversion","SMIS/SMFM ratio unifies 4-bit cells and analog converters on GaN HEMTs","Low ratios lock multi-level memory; high ratios enable GaN frequency-to-voltage","Area-ratio engineering turns GaN into memory cells plus multi-state inverters","One SMIS/SMFM knob yields record GaN memory window and linear F-V response"]},"model":"grok-4.5","effort":"low","cost_usd":0.005904,"raw_usage":{"total_tokens":1594,"prompt_tokens":867,"num_sources_used":0,"completion_tokens":107,"cost_in_usd_ticks":59040000,"prompt_tokens_details":{"text_tokens":867,"audio_tokens":0,"image_tokens":0,"cached_tokens":128},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":620,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":867,"tokens_out":107,"duration_ms":6826,"temperature":1.0,"reasoning_tokens":620,"cache_read_input_tokens":128,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-10T18:41:18.981946+00:00","model_set":{"reader":"grok-4.5"},"falsifier":"Fabricate devices spanning the same area ratios but deliberately introduce a known interface trap density or floating-electrode leakage path and measure whether the claimed 27 V window, forward 27 mV/dec swing, and linear 0.5–500 Hz FVC response still appear as predicted by the pure capacitive-division model.","supporting_citations":[],"review_version":2}