{"id":"b208ecfe-7951-488c-bc9c-badfce57530b","arxiv_id":"2607.08687","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"unknown","formal_verification":"none","parameter_count":4,"one_line_summary":"A PC-free FPGA control system achieves 282 μs feedback latency, enabling iterative rearrangement that boosts defect-free 10-atom array success probability from 65.7% to 95.4%.","lead":"Researchers built a custom FPGA-based electronic control system that removes the PC from the feedback loop, achieving 282 μs latency for rearranging neutral atoms in optical tweezers. This matters because real-time, low-latency feedback is a prerequisite for quantum error correction and mid-circuit measurement in neutral-atom quantum computers.","discovery_kind":"unclear","skeptic_critique":{"model":"glm-5.2","headline":"The QEC infrastructure claim is prospective: only atom-presence detection and rearrangement are demonstrated, not internal-state readout or syndrome-decoding feedback.","rationale":"The reader correctly identified the most load-bearing concern: the gap between what is demonstrated (atom rearrangement feedback) and what is claimed (QEC infrastructure). I agree with this assessment. The 282 μs latency characterization is thorough (8000-shot statistics, transparent decomposition into four sub-links), the rearrangement results are internally consistent (0.96^10 ≈ 66.5% matches the reported 65.68% single-round success for 10 atoms), and the dominant latency bottleneck (t_PS→PL ≈ 262 μs) is honestly disclosed with a concrete architectural fix proposed. No internal inconsistencies or circular reasoning were found. The CONDITIONAL verdict is appropriate: the engineering contribution is real and well-characterized, but the QEC significance claim is untested. The reader's weakest_assumption correctly pinpoints this gap. I recommend no change to the verdict—the concern is real but does not invalidate the core engineering contribution; it limits the scope of the claims as the reader already noted.","tokens_in":12227,"tokens_out":2701,"duration_ms":76860,"concrete_test":"Use the PXIe-QC100 system to perform hyperfine-state-selective fluorescence detection on trapped atoms (not just presence/absence), route the binarized state outcomes through the ARM processor to compute a simple syndrome (e.g., a 3-qubit repetition code parity), and apply a corrective microwave/Raman pulse via the AWG card. Measure the end-to-end latency from detection completion to correction-pulse onset. If the latency remains below ~300 μs and state-discrimination fidelity exceeds 99%, the QEC infrastructure claim is substantively supported; if the latency balloons or fidelity is insufficient, the claim remains prospective.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The abstract's final sentence claims the system 'establishes the electronic infrastructure necessary for mid-circuit measurement and real-time quantum error correction.' What is actually demonstrated is a feedback loop for atom rearrangement: fluorescence-based presence/absence detection → ARM path-planning → AWG-driven AOD atom transport. This is qualitatively different from QEC feedback in three respects: (1) QEC requires internal-state (hyperfine) readout, not just photon-counting above/below a threshold for atom presence—the paper asserts in §V that 'the same measurement setup applies directly to the internal state discrimination' but does not test this, and state-selective readout has different photon-rate regimes and fidelity constraints; (2) QEC requires syndrome decoding, a different computational problem than the 1D path-planning algorithm benchmarked at 0.89 μs; (3) QEC feedback actuates quantum gate corrections, not AOD atom transport. The 282(19) μs latency is measured only for the rearrangement task, where the dominant component (t_PS→PL ≈ 262 μs, Table I) scales linearly with frame count f = 15N_move + 12N_close—whether a QEC feedback cycle produces comparable or larger frame counts is unaddressed. The authors are transparent about this gap in §V ('this would in principle allow real-time extraction of error syndrome measurement'), but the abstract states it as established. This is the load-bearing concern because the engineering achievement (low-latency rearrangement) is solid, but the broader significance claim (QEC infrastructure) rests on an untested extrapolation.","agreement_with_reader":"agree"},"referee_report":{"model":"glm-5.2","summary":"This manuscript presents an FPGA-based electronic control system (PXIe-QC100) for neutral-atom quantum computing that eliminates the host PC from the real-time feedback loop. The system integrates photon counting (counter card), real-time decision-making (ARM processor), and waveform generation (AWG card) within a unified PXIe chassis. The authors demonstrate a total feedback latency of 282(19) μs for atom rearrangement—measured as the interval between detection completion and AWG-driven AOD actuation—and validate the system by assembling defect-free 1D atom arrays from 24 stochastically loaded optical tweezers. Single-round rearrangement achieves a ~96% filling fraction, and iterative feedback over five rounds improves the success probability for a 10-atom defect-free array from 65.7% to 95.4%. The latency budget is decomposed into four components (Eq. 1), each individually characterized (Eqs. 2–6, Fig. 5), and the dominant bottleneck is identified as the ARM-to-counter-card PL transmission (t_PS→PL ≈ 262 μs, Table I). The authors also project latency scaling under a redesigned architecture (ARM moved into the AWG-card FPGA), estimating <35 μs for 64 atoms and ~400 μs for 1000 atoms.","tokens_in":12602,"tokens_out":1435,"duration_ms":150024,"significance":"The engineering achievement is substantial and timely. Removing the PC from the feedback loop and achieving sub-millisecond latency (282 μs vs. >7 ms for PC-based systems, Ref. 24) is a meaningful step toward real-time QEC on neutral-atom platforms. The latency decomposition (Eqs. 2–6) is falsifiable and machine-checkable: each sub-link is characterized with fitted scaling parameters and sample sizes (8,000 shots for total latency, 70,000 for computation time). The multi-round iterative rearrangement protocol, which consumes only surplus atoms, is a practical demonstration of feedback-controlled atom assembly. The projected redesign latency figures (<35 μs for 64 atoms) provide concrete, testable benchmarks for the community. These strengths make the work a valuable contribution to the neutral-atom control hardware literature.","major_comments":[{"comment":"Abstract, final sentence: The claim that the system 'establishes the electronic infrastructure necessary for mid-circuit measurement and real-time quantum error correction' is not supported by what is demonstrated. The paper shows atom-presence detection (fluorescence thresholding) and 1D path-planning for rearrangement, not internal-state (hyperfine) readout, syndrome decoding, or gate-correction actuation. The authors acknowledge this prospectively in §V ('this would in principle allow real-time extraction of error syndrome measurement'), but the abstract states it as established. This is load-bearing because the QEC framing is a primary motivation. Recommendation: soften the abstract claim to match the demonstrated scope (e.g., 'establishes electronic infrastructure for real-time atom rearrangement and provides a pathway toward mid-circuit measurement and QEC').","section":null},{"comment":"Table I and Eq. (5): The dominant latency component is t_PS→PL ≈ 262 μs (for f ≈ 324 frames), which accounts for ~93% of the total 282 μs. This component scales linearly with frame count f = 15N_move + 12N_close. The paper does not discuss how f would scale for larger arrays or for QEC-relevant feedback tasks, nor whether the current architecture's dominance by this single transmission step would persist or worsen. Since the central claim is low-latency feedback, the authors should at minimum discuss the scaling of f with array size for rearrangement and note that QEC feedback tasks would involve different frame-count scaling. The projected redesign in §V addresses this architecturally but does not quantify the frame-count scaling for the current system.","section":null},{"comment":"§V, projected latency: The claim that moving the ARM into the AWG-card FPGA would yield 'a total latency below 35 μs for 64 atoms and about 400 μs for 1000 atoms' is based on projected per-channel and per-sub-waveform overheads, but the derivation is not shown. Given that the current system's dominant bottleneck is frame-count-dependent transmission (Eq. 5), the reader needs to understand how the redesign eliminates or reduces this scaling. A brief derivation or at least an explicit statement of the assumed frame counts for 64 and 1000 atoms would make this projection verifiable.","section":null}],"minor_comments":[{"comment":"Fig. 1(a): The numbered circles ①–⑤ are referenced in the text but are difficult to read in the figure. Consider enlarging or using a different marker style.","section":null},{"comment":"Fig. 2(a): The caption states 'channel 6 trap' but does not specify the detection window duration used for this histogram (5 ms is mentioned in the text but not in the caption). Include this for self-containedness.","section":null},{"comment":"§III: The text states 'the probability of stochastically obtaining a defect-free array decays exponentially with array size and becomes statistically negligible for N>8.' It would help to state the functional form (e.g., p^N) explicitly for clarity.","section":null},{"comment":"Eq. (3): The piecewise form has a discontinuity at N_trap = 7. A brief explanation of why the scaling changes at N_trap = 7 (presumably related to data packing or transmission format) would aid the reader.","section":null},{"comment":"Table I: The sum of the listed components (7.51 + 0.89 + 261.58 + 4.80 = 274.78 μs) is listed as t_total ≈ 274.78 μs, but the measured t_total is 282(19) μs. The ~7 μs discrepancy should be noted (likely trigger processing or other fixed overheads).","section":null},{"comment":"Ref. [12] (Rozanov et al., 2026) and Ref. [31] (Lu et al., 2026) appear to be future-dated. Verify these citations.","section":null}],"recommendation":"minor_revision","confidential_remarks":"The reader's stress-test concern about the QEC claim is valid and is the primary issue to address. The demonstrated work (low-latency rearrangement) is solid and publishable on its own merits; the overreach is in the framing. I would not hold the paper to demonstrating actual QEC feedback—that is clearly beyond scope—but the abstract and introduction should accurately scope the contribution. The projected latency figures in §V are interesting but currently unverified; they should either be better justified or clearly labeled as rough estimates. The citation of Ref. [24] (Dadpour et al., Phys. Rev. Applied 2025) as the PC-based comparison point is appropriate and provides a fair external benchmark."},"author_rebuttal":null,"desk_editor":{"model":"glm-5.2","letter":"The main thing to know: this paper builds a PC-free FPGA control system (PXIe-QC100) that achieves 282(19) μs total feedback latency for atom rearrangement, measured over 8,000 shots with a clean decomposition into readout, computation, and transmission stages. That's a real improvement over the >7 ms PC-based systems they cite (Dadpour et al. 2025), and the integration of photon counting, ARM-based path planning, and AWG waveform generation in a single PXIe chassis is genuinely new as a complete architecture. The rearrangement results are solid: 96% filling fraction in a single round, 95.4% success for 10 atoms over five iterative rounds, with adequate statistics (300 runs per data point). The latency budget is transparent—each sub-component is characterized with fitted scaling laws (Eqs. 2–6), and the dominant cost (t_PS→PL ≈ 262 μs) is honestly identified as an architectural choice (ARM embedded in the counter card) rather than a fundamental limit. They even project that moving the ARM to the AWG-card FPGA would bring total latency below 35 μs for 64 atoms. That's a useful, falsifiable projection. The soft spot is the abstract's final sentence: 'establishes the electronic infrastructure necessary for mid-circuit measurement and real-time QEC.' What's demonstrated is atom-presence detection and 1D path planning—not internal-state readout, not syndrome decoding, not gate-correction feedback. These are qualitatively different problems. The authors are transparent about this in §V ('this would in principle allow...'), but the abstract states it as established. The stress-test concern lands here: the QEC claim is an untested extrapolation. That said, this doesn't undermine the engineering achievement. The latency characterization is rigorous, the hardware is described in enough detail to evaluate, and the iterative rearrangement protocol is a legitimate demonstration of the system's real-time capability. No code or firmware is public, which limits reproducibility, but the hardware characterization is internally consistent. This paper is for groups building neutral-atom control systems who need a concrete latency benchmark and architecture reference. It deserves a serious referee. The referee should push the authors to either soften the QEC claim in the abstract or add even a preliminary internal-state readout demonstration to justify it.","headline":"Solid low-latency FPGA control for atom rearrangement; the QEC infrastructure claim is prospective and untested","tokens_in":13297,"tokens_out":554,"would_cite":true,"duration_ms":69868,"reading_group":"no","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"glm-5.2","headline":"FPGA control loop builds defect-free atom arrays in 282 microseconds","keywords":[],"falsifier":"If the 282-microsecond latency were found to increase non-linearly with array size beyond 24 traps, or if the iterative rearrangement protocol's success probability saturated well below the projected values for larger arrays due to cumulative atom loss, the central claim that this architecture scales to the regime needed for quantum error correction would be undermined.","tokens_in":12456,"feed_emoji":"⚛️","tokens_out":1068,"duration_ms":203096,"temperature":0.7,"pith_summary":"Neutral atom quantum computers need to detect errors and correct them in real time, but today's control systems route every measurement through a conventional PC, adding milliseconds of delay that is incompatible with the microsecond timescales of quantum circuits. This paper presents a custom FPGA-based electronic system that removes the PC entirely from the feedback loop, integrating photon counting, decision-making, and waveform generation on a single PXIe chassis. The system detects which optical tweezers contain atoms, computes rearrangement paths, and drives the tweezers to move atoms into a defect-free array, all within 282 microseconds. By repeating this feedback loop up to five times within a single experimental cycle, the authors boost the probability of assembling a perfect 10-atom array from 65.7% to 95.4%, starting from 24 stochastically loaded traps. The core claim is that a purpose-built, PC-free FPGA architecture can reduce feedback latency by more than an order of magnitude compared to prior systems, and that this latency reduction enables iterative correction protocols that meaningfully improve atom array preparation fidelity.","feed_headline":"FPGA control loop builds defect-free atom arrays in 282 microseconds","feed_subtitle":"Removing the PC from the feedback loop cuts latency 25-fold and enables iterative correction that lifts array fidelity to 95%.","key_machinery":"The system comprises a PXIe chassis hosting a counter card (with embedded ARM processor for path planning) and an AWG card (for driving the acousto-optic deflector). The feedback loop proceeds in five stages: (1) single-photon detectors convert atom fluorescence to TTL signals, (2) the counter card bins photon counts and thresholds them into binary occupancy, (3) the ARM computes rearrangement paths and compiles RF movement commands, (4) commands transfer across the PXIe backplane from counter card to AWG card, (5) the AWG outputs chirped RF waveforms to the AOD to physically move atoms. The total latency budget decomposes as t_read (7.51 microseconds for 24 traps), t_calculate (0.89 micro","core_discovery":"The central technical result is a total feedback latency of 282(19) microseconds for the complete loop from atom detection to tweezer actuation, achieved by eliminating PC communication overhead, transmitting only binarized occupancy data rather than raw photon counts, and using compact movement instructions rather than full waveforms. This latency is low enough to permit multiple rearrangement rounds within a single loading cycle, which is what allows the success probability for a 10-atom defect-free array to rise from 65.7% after one round to 95.4% after five rounds. The system architecture places a counter card with an embedded ARM processor and an arbitrary waveform generator card on a共享","pith_inferences":["If the projected sub-35-microsecond latency for 64 atoms is realized, it would bring the feedback loop comfortably within the coherence time of neutral-atom qubits, potentially enabling real-time syndrome extraction rather than post-hoc data analysis.","The iterative rearrangement scheme implicitly assumes that surplus atoms survive multiple transport rounds without loss; the paper does not report per-round atom survival rates, so the scaling of this protocol to larger arrays or more rounds remains an open empirical question.","Extending this architecture to two-dimensional arrays would require a fundamentally different transport scheme (e.g., 2D AODs or SLMs), and the latency budget for path planning in 2D may not scale as favorably as the linear case demonstrated here."],"forward_implications":["The iterative rearrangement protocol could be extended to actively compensate for atom loss during quantum circuit execution, provided a reservoir of spare atoms is maintained adjacent to the computational zone.","The same photon-counting and threshold-comparison hardware could be applied to internal-state (hyperfine) discrimination rather than just atom-presence detection, enabling mid-circuit measurement for quantum error correction.","The PXIe chassis already supports scaling from 8 to 18 slots within a single chassis, with multi-chassis synchronization available, so the architecture is not fundamentally limited to 24 traps.","The authors project that moving the ARM processor into the AWG-card FPGA would eliminate the dominant counter-card relay step, reducing total latency to below 35 microseconds for 64 atoms and approximately 400 microseconds for 1000 atoms."],"fun_headline_variants":["FPGA feedback loop assembles defect-free atom arrays at 282 μs latency","PC-free FPGA control reduces atom array feedback to 282 microseconds","On-FPGA decisions raise defect-free atom array success to 95%","FPGA system assembles 10-atom defect-free arrays at 95.4% success rate","Embedded FPGA control enables five-round atom rearrangement per cycle"],"cache_read_input_tokens":0,"weakest_assumption_plain":"The paper claims this system 'establishes the electronic infrastructure necessary for mid-circuit measurement and real-time quantum error correction,' but it only demonstrates atom-presence detection and physical rearrangement, not internal-state readout or syndrome decoding. The authors state that the same setup applies to hyperfine-state discrimination, but this is untested in the present work.","fun_headline_variants_meta":{"raw":{"variants":["FPGA feedback loop assembles defect-free atom arrays at 282 μs latency","PC-free FPGA control reduces atom array feedback to 282 microseconds","On-FPGA decisions raise defect-free atom array success to 95%","FPGA system assembles 10-atom defect-free arrays at 95.4% success rate","Embedded FPGA control enables five-round atom rearrangement per cycle","282 μs FPGA feedback loop permits iterative atom array correction","PXIe FPGA architecture removes PC from atom rearrangement feedback path","Binarized occupancy data drives 282 μs FPGA atom array feedback","FPGA control raises 10-atom array success from 66% to 95% over five rounds","Compact FPGA movement instructions cut atom rearrangement latency 25-fold"]},"model":"glm-5.2","effort":"low","cost_usd":0.0,"raw_usage":{"total_tokens":1580,"prompt_tokens":484,"completion_tokens":1096,"prompt_tokens_details":null},"tokens_in":484,"tokens_out":1096,"duration_ms":51540,"temperature":1.0,"reasoning_tokens":906,"cache_read_input_tokens":0,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-10T03:01:34.094907+00:00","model_set":{"reader":"glm-5.2"},"falsifier":"If the 282-microsecond latency were found to increase non-linearly with array size beyond 24 traps, or if the iterative rearrangement protocol's success probability saturated well below the projected values for larger arrays due to cumulative atom loss, the central claim that this architecture scales to the regime needed for quantum error correction would be undermined.","supporting_citations":[],"review_version":1}