{"id":"20bc3df7-39aa-412a-97d0-0e521062f8e8","arxiv_id":"2607.10262","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":6.5,"correctness_risk":"low","formal_verification":"none","parameter_count":3,"one_line_summary":"HSF-S reduces HSF effective path cost by up to 90% via rank-aware reordering and discounted-gain SWAP insertion, then accelerates the compiled workloads up to 4.34× on a dedicated RISC-V processor.","lead":"HSF-S is a compiler plus custom accelerator that cuts the exponential path explosion in hybrid Schrödinger–Feynman quantum-circuit simulation by reordering gates and inserting carefully chosen SWAPs. It makes exact classical emulation of larger circuits practical on ordinary and embedded hardware.","discovery_kind":"new_method","skeptic_critique":{"model":"grok-4.5","headline":"C_eff is only a surrogate: the regression-free selector does not guarantee wall-clock non-regression when SWAP insertion inflates W_path.","rationale":"The reader correctly isolates the load-bearing soft spot: C_eff under fixed balanced bipartition and a finite sweep is treated as a faithful enough runtime proxy that the regression-free selector yields practically faster circuits. That is exactly where the central “speed-optimized” claim is least secure—empirically supported on the completed Table 2 pairs and large-ΔC_eff cases, but not guaranteed by the selector invariant, and only partially stress-tested because most naive baselines time out. No stronger internal inconsistency (correctness, index-map semantics, or hardware measurement fabrication) appears in the manuscript; the evaluation is transparent and the co-design claims are carefully hedged. This does not justify moving past CONDITIONAL (artifacts and adaptive partitions still pending) nor down to REJECT. Verdict stays CONDITIONAL; confidence in that call remains high.","tokens_in":20033,"tokens_out":651,"duration_ms":55883,"concrete_test":"For all 56 circuits, re-score every Stage-2/3 candidate with primary key 2^{C_eff}×|G| (or a short-query measured qsimh time) instead of κ; re-run the selector. If any circuit’s wall-clock-best candidate differs from the C_eff-selected circuit by >2× in full 2^{15}-query qsimh time, or if any completed naive/HSF-S pair has T_HSF-S > T_naive despite lower C_eff, the surrogate-objective claim weakens.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The speed claim rests on optimizing and selecting by C_eff (Eq. 6) under fixed b=⌊n/2⌋ and a finite (L,γ) sweep (§3.1–3.4, §5.1). The selector only enforces C_eff(C*) ≤ C_eff(C_naive); it does not enforce T_HSF non-regression. From Eq. 5, T_HSF = 2^{C_eff} × W_path. Stage-3 SWAPs and denser Stage-1/2 schedules increase gate count and thus W_path, while the primary key ignores W_path except as a weak |G| tie-breaker. When ΔC_eff is small (e.g., QAOA_SBM_n30_inst10: 17→14, only 8× path factor), a moderate W_path increase can erase the gain. Table 2 shows no runtime regressions among pairs that both finish, but most naive runs are Timeout (1h), so non-regression is only partially observed. The paper itself calls C_eff a “surrogate … rather than a direct predictor” (§3.1), yet the abstract’s tractability claim treats C_eff cuts as practically decisive.","agreement_with_reader":"agree"},"referee_report":{"model":"grok-4.5","summary":"HSF-S is a compiler–accelerator co-design for exact Hybrid Schrödinger–Feynman (HSF) quantum-circuit emulation. The compiler lowers circuits to an HSF-compatible basis, optimizes a rank-aware effective path cost C_eff = |G_cross^¬swap| + 2|G_cross^swap| under a fixed balanced bipartition via dependency-preserving reordering and discounted-gain SWAP insertion, and uses a selector that never increases C_eff relative to the naive lowered baseline. A dedicated multi-engine accelerator performs per-path dual-slice evaluation with common-prefix checkpointing and scalar accumulation, integrated into a stand-alone RISC-V SoC. Across 56 benchmarks, amplitudes match full-state qsim references to floating-point precision (worst max abs error 3.37×10^{-8}), C_eff falls by up to 90%, many timeouts become sub-second under a 1-hour budget, and the FPGA prototype at 200 MHz adds up to 4.34× speedup on compiled workloads.","tokens_in":20402,"tokens_out":1579,"duration_ms":37171,"significance":"Exact HSF remains a practical route for memory-constrained classical emulation, but path explosion from cross-boundary gates has limited its usefulness. Treating cross SWAP as a path-cost-aware compile-time transform (rather than a routing artifact), with an explicit rank-based surrogate and a regression-free C_eff selector, is a clear and useful systems contribution. The matching HSF-specific accelerator (path-parallel dual-slice engines, cut-rank metadata, common-state checkpointing) fills a real gap left by Schrödinger-centric GPU/FPGA designs. Strengths that should be credited include: amplitude validation against full-state qsim; a monotonic ablation of pipeline stages on aggregate C_eff (Fig. 7); a uniform 56-circuit suite with timeout accounting; and a working FPGA prototype plus 14 nm area/power numbers. If the empirical tractability gains hold under broader partitions and workloads, the work meaningfully advances resource-constrained exact emulation.","major_comments":[{"comment":"§3.1–3.2 and Eq. (5)–(6): The selector guarantees only C_eff(C*) ≤ C_eff(C_naive), while wall-clock cost is T_HSF = 2^{C_eff} × W_path. Stage-3 SWAPs and denser Stage-1/2 schedules can increase gate count and thus W_path; |G| is only a weak tie-breaker in κ. The paper correctly calls C_eff a “surrogate … rather than a direct predictor” (§3.1), yet the abstract and §5.2 treat C_eff cuts as practically decisive for tractability. For small ΔC_eff (e.g., QAOA_SBM_n30_inst10: 17→14 in Table 2), a moderate W_path increase could erase the gain. Please report pre/post |G|, |G_2q|, and/or measured W_path (or per-path work) for all circuits, and either (i) show that 2^{ΔC_eff} dominates observed W_path growth in every finishing case, or (ii) strengthen the selector with an explicit W_path-aware or measured-runtime check among candidates. Clarify in the abstract that non-regression is guaranteed fo","section":"§3.1–3.2, Eq. (5)–(6), Table 2"},{"comment":"§5.1–5.2 and Table 2: Most naive qsimh runs are Timeout (1h), so wall-clock non-regression is only partially observed; only eight circuits finish under both CPU-preprocessed software and hardware for the 1.87–4.34× HW claim. Preprocessing time is excluded (avg 2.81 s, max 29.2 s), which is fine for former timeouts but can matter for already-fast circuits. Please (a) add a complete finishing-pair table (or appendix) with naive vs HSF-S software runtime whenever both finish, including preprocessing as a separate column; (b) state how many circuits finish under naive vs HSF-S software; and (c) discuss whether any candidate with lower C_eff but higher measured software runtime was ever selected (or would have been under the current κ). This is needed to support the “substantially improves practical tractability” claim beyond timeout-to-finish anecdotes.","section":"§5.1–5.2, Table 2"}],"minor_comments":[{"comment":"Figure 6 is very dense (many stacked bars and parenthetical SWAP contributions). Consider splitting by benchmark family or moving full per-circuit numbers to a table/appendix and keeping a summary plot in the main text.","section":"Figure 6"},{"comment":"§5.2: GPU (RTX 5090) results are mentioned only to say none finished in 1 hour, then omitted. Briefly state which backend was used (full-state vs HSF-style) and why the comparison is uninformative, so readers do not infer an incomplete experiment.","section":"§5.2"},{"comment":"§5.1: The bipartition is fixed at b = ⌊n/2⌋ and never co-optimized with reordering/SWAP. A short limitations paragraph noting that static or joint partitioning could be composed with HSF-S would place the contribution more accurately relative to [16, 17].","section":"§5.1, §2.2"},{"comment":"Eq. (6) vs Eq. (5): C_eff is defined as a sum of ranks in log-domain units, while N_paths = ∏ r_i. A one-sentence reminder that after lowering every non-SWAP cross gate has r=2 and SWAP has r=4 would help readers who skip §2.1.","section":"Eq. (6)"},{"comment":"Abstract and §1: “up to 2^{19}× path reduction on QAOA-SBM” is strong; ensure the main text states the corresponding C_eff drop (or product of ranks) explicitly next to that number for auditability.","section":"Abstract, §1, §5.2"},{"comment":"Table 1: FPGA LUTs for the accelerator dominate; a one-line note on whether state memory is the main consumer (as the text suggests) would help systems readers.","section":"Table 1"}],"recommendation":"minor_revision","confidential_remarks":"The manuscript states it has already been accepted at ICCAD 2026; treat this as a journal-style extension review. The core engineering contribution is solid and the correctness checks are real. The main risk is over-claiming that C_eff optimization alone is a wall-clock non-regression guarantee; that is a clarification/analysis issue, not a soundness failure. I would not reject on the skeptic’s point alone."},"author_rebuttal":null,"desk_editor":{"model":"grok-4.5","letter":"This is a competent systems paper that actually moves the needle on exact HSF emulation. The new piece is treating a cross-boundary SWAP as a deliberate path-cost move under a rank-aware C_eff (non-SWAP crosses cost 1, SWAPs cost 2), then exposing those moves with two dependency-preserving reorders and a discounted-gain insertion pass, plus a selector that never lets C_eff get worse than the naive lowered circuit. They also ship a matching dual-slice accelerator with common-prefix checkpointing and integrate it into a Rocket-based SoC that they prototyped on VCU118 and synthesized at 14 nm.\n\nWhat works: correctness is checked against full-state qsim (max abs error 3.37e-8 after index-map translation). Ablation shows monotonic C_eff drop as stages are added. On 56 circuits they report up to 90 % C_eff reduction and path factors up to 2^19 on QAOA-SBM; several 1-hour timeouts become sub-second or a few seconds on qsimh, and the FPGA prototype adds another 1.87–4.34× on the compiled workloads. The math is standard Schmidt-rank bookkeeping; the citations cover qsimh, joint cutting, GraFeyn, and routing/knitting SWAP work without obvious gaps. No circular fitting—C_eff is only a compile-time surrogate and they measure wall-clock separately.\n\nSoft spots, in proportion. The stress-test is right that the selector only guarantees C_eff non-regression, not T_HSF non-regression, because SWAPs and denser schedules can inflate W_path. When ΔC_eff is small (17→14) that could matter; most naive runs simply time out, so full non-regression is only partially observed. Fixed balanced bipartition and a finite (L,γ) sweep are ordinary engineering limits, not load-bearing flaws. No public code/RTL yet, which is the usual CAD-paper friction.\n\nThis is for people who care about classical quantum-circuit emulation and CAD for quantum. It deserves a serious referee; the central claims hold up under the evidence they give. I would engage with it and expect it to be useful once artifacts appear.","headline":"Solid compiler–accelerator co-design for HSF: rank-aware C_eff + discounted cross-SWAP + dual-slice engine turn real timeouts into usable runs; the surrogate-vs-wall-clock gap is real but secondary to the measured gains.","tokens_in":21002,"tokens_out":574,"would_cite":true,"duration_ms":5342,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.5","headline":"HSF-S shows that path-cost-aware compilation and an HSF-specific processor can cut Hybrid Schrödinger–Feynman path cost by up to 90% and turn many timeouts into sub-second exact emulations.","keywords":["Hybrid Schrödinger–Feynman","quantum circuit emulation","path-cost compilation","SWAP insertion","Schmidt rank","FPGA accelerator","exact simulation"],"falsifier":"Take a circuit family where HSF-S reports a large C_eff reduction, run both the naive-lowered and HSF-S-compiled versions under identical qsimh settings and the same amplitude query budget, and check whether measured runtime fails to scale roughly as 2 to the power of the reported ΔC_eff or whether any compiled circuit is slower than its naive baseline.","tokens_in":20941,"feed_emoji":"⚛️","tokens_out":758,"duration_ms":7369,"temperature":0.7,"pith_summary":"Exact classical emulation of quantum circuits is limited either by full-state memory growth or by exponential path growth when circuits are split. Hybrid Schrödinger–Feynman (HSF) simulation keeps two half-sized state slices and only expands cross-boundary two-qubit gates into paths, but a few hub qubits that keep crossing the cut can still make the path count explode. HSF-S treats that path-branching cost as a compile-time objective: it lowers the circuit to an HSF-executable gate set, reorders gates without changing the unitary, and inserts cross-boundary SWAPs only when a discounted-gain test shows they will remove more future cross interactions than they cost. A selector always keeps the naive lowered baseline if nothing better is found, so path cost never rises. The same compiler artifacts drive a dedicated dual-slice accelerator that evaluates independent paths in parallel and accumulates only the requested amplitudes. On 56 circuits the method preserves amplitudes to floating-point precision, reduces effective path cost by as much as 90%, turns many one-hour timeouts into sub-second runs, and the prototype processor adds up to another 4.34× on the compiled workloads.","feed_headline":"Compiler cuts HSF path cost up to 90%, timeouts become seconds","feed_subtitle":"Path-aware SWAPs plus a dual-slice processor make exact hybrid emulation practical on modest hardware.","key_machinery":"The rank-aware effective path cost C_eff together with discounted-gain SWAP insertion (gain ≥ 0 after the +2 cost of the SWAP itself), which turns SWAP from a routing artifact into a compile-time path-cost transformation under a fixed bipartition.","core_discovery":"A fixed bipartition’s HSF path burden is dominated by recurring cross-boundary gates on a few hub qubits; by measuring that burden with the rank-aware cost C_eff = |non-SWAP cross gates| + 2|cross SWAPs|, dependency-preserving reordering plus discounted-gain SWAP insertion can relocate those hubs so that many later interactions become local, and a regression-free selector guarantees the compiled circuit never increases C_eff relative to the naive lowered baseline while remaining exactly correct for amplitude queries.","pith_inferences":[],"forward_implications":[],"fun_headline_variants":["HSF-S relocates hub qubits cutting path cost up to 90%","Rank-aware compiler suppresses recurring cross-boundary gates","Dependency-preserving SWAPs make HSF timeouts into seconds","Dual-slice processor plus selector speeds exact HSF emulation","Path cost cut 90% while guaranteeing no regression on baseline"],"cache_read_input_tokens":16512,"weakest_assumption_plain":"That counting cross-boundary gates by their Schmidt ranks under a fixed half-and-half cut, after a limited sweep of window and discount parameters, is a good enough stand-in for real HSF wall-clock time that the selector will reliably produce faster circuits.","fun_headline_variants_meta":{"raw":{"variants":["HSF-S relocates hub qubits cutting path cost up to 90%","Rank-aware compiler suppresses recurring cross-boundary gates","Dependency-preserving SWAPs make HSF timeouts into seconds","Dual-slice processor plus selector speeds exact HSF emulation","Path cost cut 90% while guaranteeing no regression on baseline"]},"model":"grok-4.5","effort":"low","cost_usd":0.005106,"raw_usage":{"total_tokens":1465,"prompt_tokens":873,"num_sources_used":0,"completion_tokens":70,"cost_in_usd_ticks":51060000,"prompt_tokens_details":{"text_tokens":873,"audio_tokens":0,"image_tokens":0,"cached_tokens":128},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":522,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":873,"tokens_out":70,"duration_ms":5240,"temperature":1.0,"reasoning_tokens":522,"cache_read_input_tokens":128,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-14T13:04:07.993362+00:00","model_set":{"reader":"grok-4.5"},"falsifier":"Take a circuit family where HSF-S reports a large C_eff reduction, run both the naive-lowered and HSF-S-compiled versions under identical qsimh settings and the same amplitude query budget, and check whether measured runtime fails to scale roughly as 2 to the power of the reported ΔC_eff or whether any compiled circuit is slower than its naive baseline.","supporting_citations":[],"review_version":1}