{"id":"76007018-0c83-40a4-b968-b84cb7c1cb92","arxiv_id":"2607.13446","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":6,"one_line_summary":"Million-spin photonic Ising machines are argued to be within reach via chiplet, free-space, and all-optical spatiotemporal architectures, but only with major engineering advances.","lead":"This perspective reviews photonic Ising machines—optical hardware that tries to solve hard optimization problems by mapping them to networks of spins—and sketches three routes toward million-spin systems. It is useful for tracking whether optical accelerators could eventually compete with GPUs on large combinatorial optimization workloads.","discovery_kind":"review","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Correcting the power arithmetic: the real blocker for the spatiotemporal route is the unstated 10^6-core fiber and missing weight-loading scheme.","rationale":"The reader's verdict is CONDITIONAL, and I agree with that overall assessment, but the specific weakest assumption as stated is partly wrong: the 800 W vs 800 kW arithmetic error does not exist. 10^12 pulses at 4 fJ is 4 mJ per round trip, and at a ~5 µs round trip that is 800 W, matching the paper. However, the underlying concern about the spatiotemporal architecture is real and even stronger than the reader stated. Section 3.3 requires N=10^6 fiber cores for a million-spin machine, and the paper does not flag that this is four orders of magnitude beyond demonstrated multicore fibers. Additionally, the architecture provides no mechanism for loading or reconfiguring the 10^12 coupling weights, undermining the claimed reconfigurability. Because the other two routes (chiplet, free-space) do not obviously support a million all-to-all spins—chiplet is demonstrated for sparse connectivity, and free-space arbitrary all-to-all is pixel-limited—the spatiotemporal route is load-bearing for the central claim. Yet the paper is a perspective, not an experimental claim, and the free-space 360,000-spin demonstration (ref. 30) provides partial independent support for scaling. Thus the verdict remains CONDITIONAL: the roadmap is informative but the spatiotemporal section needs substantial revision to acknowledge and address the fiber-core and weight-programming challenges before it is presented as a viable path. The analysis should not be rejected outright because the perspective's other content and the cited demonstrations still make the overall roadmap plausible at a qualitative level.","tokens_in":27439,"tokens_out":11079,"duration_ms":116158,"concrete_test":"Use the paper's own loop parameters (200 GHz clock, 5 µs round trip, 10^6 time slots per core) with the current state-of-the-art 100-core multicore fiber. Total stored matrix elements = 100 × 10^6 = 10^8 = N^2, so N_max ≈ 10^4. If N_max remains ~10^4 unless fiber cores scale to 10^6, the spatiotemporal route to 10^6 all-to-all spins is not plausible without a four-orders-of-magnitude jump in fiber-core count. Also require the authors to specify a write/reconfiguration mechanism and its time/energy budget for loading 10^12 weights; if none exists, the architecture cannot implement arbitrary Ising problems.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The reader's 800 kW claim is an arithmetic error: 10^12 pulses × 4 fJ = 4 mJ per round trip, and with a ~5 µs round trip this is 800 W, so the energy budget is internally consistent. The substantive issue is Section 3.3: for N=10^6 spins the architecture requires N fiber cores, each storing N pulses, i.e., 10^6 parallel cores. State-of-the-art multicore fibers have about 100 cores (refs. 172,173), four orders of magnitude fewer. The 'Practical challenges' paragraph flags the 200 GHz clock, dispersion, synchronization, and TFLN wafer yield, but never the core count. Moreover, the 10^12 coupling-matrix elements are stored in a recirculating delay-line memory with no described mechanism for writing or reconfiguring those weights; without a load/update path the machine cannot be reconfigurable as claimed. Since this spatiotemporal route is the only one of the three that explicitly targets 10^12 all-to-all couplings, the central claim that 'several approaches could plausibly reach' a million spins is not supported for dense all-to-all problems: the chiplet route is demonstrated only for sparse connectivity, and the free-space route with arbitrary all-to-all coupling is limited by SLM pixel count to ~10^3–10^4 spins unless restricted to convolutional matrices.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This perspective reviews the state of the art in photonic Ising machines and argues that several emerging architectures—integrated photonic chiplets, free-space spatial/optoelectronic processors, and an all-optical coherent spatiotemporal processor—could plausibly scale to and beyond a million Ising spins. The paper classifies existing demonstrations by platform (fiber, free-space, integrated), tabulates representative results, identifies scalability/connectivity/precision bottlenecks, and provides order-of-magnitude resource estimates for the proposed spatiotemporal design. Its stated key point is that multiple approaches could plausibly reach million-spin scales, enabling practical heuristic solvers for combinatorial optimization.","tokens_in":27813,"tokens_out":5665,"duration_ms":59774,"significance":"If the roadmap is credible, the paper is a useful synthesis for a field moving from small laboratory demonstrations toward application-scale hardware. Its strengths include a broad and current survey (Table 1), a clear taxonomy of multiplexing strategies, and an explicit quantitative sketch of a specific all-optical architecture (Section 3.3). The paper does not report new experiments, so its value rests on the accuracy and completeness of its feasibility analysis. The main risk is overstatement: the qualitative claims for chiplet and free-space routes are qualified by sparse connectivity or convolutional restrictions, while the one route explicitly targeting dense all-to-all million-spin operation (Section 3.3) omits a critical hardware requirement—the number of parallel fiber cores—and the weight-loading mechanism. These gaps are fixable in a revision but are load-bearing for the central key-point claim.","major_comments":[{"comment":"The architecture stores the Ising matrix in a multicore fiber loop with 'N total fiber cores, with each fiber core storing N pulses' (text near Fig. 4b). For N=10^6 this requires 10^6 parallel fiber cores. State-of-the-art multicore fibers cited in refs. 172 and 173 have about 100 cores. The 'Practical challenges' paragraph discusses the 200 GHz clock, dispersion, synchronization, and TFLN wafer yield, but never mentions the core count. This is a central feasibility gap for the spatiotemporal route; without a path to ~10^6-core fiber, the claim that 'several approaches could plausibly reach' a million all-to-all spins is not supported for dense problems.","section":"Section 3.3"},{"comment":"The design says the Ising matrix elements 'are stored in a multicore fiber loop' and describes readout via outcoupling, but no mechanism is given for writing or reconfiguring the 10^12 coupling-matrix elements. A recirculating delay-line memory with no load/update path cannot serve as a reconfigurable general-purpose Ising machine, which the paper itself lists as a key requirement (Box 2b). The authors should either specify a weight-loading scheme (e.g., parallel write-in couplers or per-core modulation) or explicitly restrict the claim to fixed, pre-programmed instances.","section":"Section 3.3 / Fig. 4"},{"comment":"The other two routes do not currently establish arbitrary all-to-all million-spin capability. The chiplet example in Section 3.1 is explicitly for 'sparsely connected spins,' and the free-space route in Section 3.2 notes that Fourier-domain implementations are restricted to convolutional coupling matrices. The key-point claim of 'several approaches could plausibly reach this scale' should be qualified to distinguish dense all-to-all problems (only Section 3.3 targets those) from sparse or convolutional problems, which have lower connectivity requirements.","section":"Section 3.1–3.2"},{"comment":"The energy arithmetic is internally consistent: 10^12 pulses at 4 fJ/pulse in a 5 µs round trip gives 800 W circulating power; the 20 dB SNR overhead implies 80 kW circulating power, and at 10% round-trip loss the dissipated power is 8 kW, yielding 40 fJ/MAC. The text is easy to misread, however, because it jumps from '800 W total circulating power' to 'the total power dissipated is about 8 kW' without explicitly stating the factor-of-100 increase in circulating power. Clarifying this step would strengthen the presentation.","section":"Section 3.3 energy budget"}],"minor_comments":[{"comment":"The phrase 'Several approaches could plausibly reach this scale and beyond' is repeated in the key points and conclusion; given the qualifications in Sections 3.1–3.3, the authors may want to add a qualifier such as 'for suitable connectivity classes' to avoid overstating the current evidence.","section":"Abstract / Key points"},{"comment":"The table mixes 'spins' with 'nodes' and 'N' without a consistent notation; e.g., '2×10^3' and '>10^4' entries. Also, the column header 'Re. Coupling' is unclear—spell out 'Reconfigurable coupling' in the header or use a footnote.","section":"Table 1"},{"comment":"The sentence 'However, CMOS electronics, where dense integration is important to mitigate the energy-cost and heating issues associated with electrical interconnects between chips, an all-optical architecture...' is grammatically incomplete. It should be rephrased to compare the on-chip integration penalty in CMOS with the proposed optical chiplet approach.","section":"Section 3.3"},{"comment":"There is a duplicated word: 'spins spins' in the sentence 'free-space photonic Ising machines have been demonstrated at scales exceeding N> 10,000 spins spins with all-to-all connectivity.'","section":"Section 2.2"},{"comment":"Several reference entries contain typographical artifacts (e.g., 'Y oshihisa Yamamoto', 'V .', and 'T Y po' in ref. 159). These should be cleaned up before publication.","section":"References"},{"comment":"The spider chart legend uses 'L', 'M', 'H' without a scale; consider adding a short caption defining these as Low/Medium/High or a numeric axis.","section":"Figure 1"}],"recommendation":"major_revision","confidential_remarks":"The paper is a perspective rather than a primary research article, so the bar for acceptance should be whether the roadmap is honestly assessed. The missing 10^6-core requirement and the absent weight-loading scheme in Section 3.3 are the most serious issues; both are fixable by adding explicit discussion and tempering the key-point claim. I would not reject, but the paper needs a substantive revision before it can serve as a reliable guide for the community."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nRead the perspective. The value here is the survey: a clear, well-organized map of fiber, free-space, and integrated photonic Ising machines, with a useful table of state-of-the-art demonstrations and a sensible breakdown of the scalability, connectivity, and precision bottlenecks. If you want one reference to put the field in context, this does the job. The three roadmap sections—chiplet, free-space, and spatiotemporal—are extensions of existing ideas rather than new results; the only genuinely new element is the spatiotemporal architecture in Section 3.3.\n\nThat section deserves scrutiny. The energy arithmetic is internally consistent: 10^12 pulses at 4 fJ per pulse over a 5 µs loop is about 800 W circulating, not 800 kW. So the reader's flagged arithmetic error isn't one. The real problem is structural: the memory design stores the Ising matrix in a multicore fiber loop with N cores, one per column, each carrying N pulses. For N=10^6 spins that is 10^6 fiber cores. The paper cites 100-core fibers as the state of the art and never flags that the spatiotemporal path needs four orders of magnitude more. The 'Practical challenges' paragraph worries about clock rate, dispersion, and wafer yield—not the core count or the fact that the matrix lives in a recirculating delay line with no described mechanism for writing or reconfiguring the weights. Without a load/update path, that machine isn't reconfigurable, which undercuts the paper's own claims.\n\nThe central claim that 'several approaches could plausibly reach a million spins' is also uneven. The chiplet route with 5x5 chiplets at 40k spins each is only credible for sparse connectivity; the free-space route's all-to-all version is capped by SLM pixel count to ~10^3-10^4 spins unless you go convolutional. So for dense all-to-all problems, the spatiotemporal route is the only one that explicitly targets 10^12 couplings, and it's the weakest of the three. That asymmetry should have been called out in the paper.\n\nThat said, the review itself is solid and fair. The classification is useful, the table is comprehensive, and the authors are honest about many practical obstacles. It just overreaches in the roadmap, especially in Section 3.3.\n\nWho's this for? Anyone wanting a current overview of photonic Ising machines, or a graduate student looking for open problems. It deserves a serious referee—not because the central claim is established, but because the proposal is concrete enough to be worth critiquing and the review has standalone value. I'd ask the authors to add the core-count and weight-loading discussion before publication.\n\nBest,","headline":"Useful survey of photonic Ising machines, but the flagship spatiotemporal roadmap quietly needs a million-core fiber and a weight-loading scheme it never describes.","tokens_in":28321,"tokens_out":3151,"would_cite":false,"duration_ms":34316,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Photonic Ising machines can plausibly be scaled to and beyond one million spins, and this paper lays out three architectures that could get there.","keywords":["photonic Ising machine","combinatorial optimization","optical matrix-vector multiplication","spatial light modulation","thin-film lithium niobate","multicore fiber","coherent Ising machine","scalable architecture"],"falsifier":"A back-of-envelope power audit settles the flagship architecture: 10^12 pulses × 4 fJ per pulse per ~5 µs round trip yields roughly 800 kW, not 800 W; a prototype at 1,000 spins with the claimed 50 dB SNR and stable DOPA compensation over 1,000 round trips would further test the central claim.","tokens_in":27333,"feed_emoji":"💡","tokens_out":7073,"duration_ms":73167,"temperature":0.7,"pith_summary":"The paper argues that photonic Ising machines—hardware that maps combinatorial optimization problems onto networks of binary spins and lets light seek low-energy solutions—can be scaled to a million spins and beyond, a size the authors say real-world problems in drug discovery, logistics, and materials design require. It surveys demonstrated systems (fibre, free-space, and integrated, up to roughly 360,000 spins) and identifies the bottlenecks: connectivity, reconfigurability, time-to-solution, and precision. Its central contribution is a roadmap of three architectures judged able to cross the million-spin mark: a photonic chiplet processor that partitions the coupling matrix across many chips; a free-space processor using spatial light modulation, with Fourier-domain multiplication to avoid explicit fan-out; and an all-optical coherent spatiotemporal machine that stores the whole matrix as pulses in a multicore fibre loop and performs multiply-accumulate operations with second-order nonlinear optics. If these scale as argued, optical solvers could offer microsecond-scale iterations at room temperature with far lower energy than electronic approaches. The paper is a perspective, so its claims are architectural extrapolations and design targets rather than demonstrated milestones.","feed_headline":"Three designs could push photonic Ising machines past a million spins","feed_subtitle":"If the roadmap holds, optics could solve optimization problems that now defeat room-temperature digital hardware.","key_machinery":"The paper's load-bearing objects are the Ising Hamiltonian E = -ΣJ_ij s_i s_j - Σh_i s_i, whose ground states encode solutions; the optical matrix-vector multiplication (MVM) that implements spin-spin couplings; and three multiplexing dimensions—time, space, and wavelength. The most specific mechanism is the all-optical coherent spatiotemporal architecture: a multicore fibre loop stores one column of the coupling matrix per core as a train of optical pulses (N cores × N pulses = N² elements); a thin-film lithium niobate (TFLN) waveguide uses sum-frequency generation in a recirculating one-pulse register to multiply and accumulate pulse pairs, with difference-frequency generation ejecting the","core_discovery":"The paper's core claim is that obstacles to large-scale photonic Ising machines are architectural rather than fundamental. Currently demonstrated platforms—100,000-spin fibre machines, 360,000-spin free-space systems, and integrated chips near 40,000 spins—can be extended by three routes: chiplets that decompose the N×N coupling matrix across parallel photonic chips; free-space systems that encode spins in spatial light modulators and use Fourier-domain multiplication so fan-in/fan-out does not set the scale; and an all-optical coherent spatiotemporal architecture that stores N×N matrix pulses in a multicore fibre loop and performs multiply-accumulate operations with a sum-frequency-generati","pith_inferences":["The paper's own energy figures for the spatiotemporal memory appear inconsistent: 10^12 pulses at 4 fJ each in a ~5 µs loop round trip implies roughly 800 kW of circulating power, not the stated 800 W; a corrected budget would change the 40 fJ/MAC estimate materially.","The spatiotemporal architecture quietly assumes ~10^6 parallel fibre cores or waveguides for one million spins, about four orders of magnitude beyond demonstrated multicore fibre (roughly 100 cores); no current packaging or fabrication path is identified for that leap.","The free-space Fourier-domain route, restricted to convolutional couplings, could still cover many practical problems if combined with chiplet-style partitioning—the paper sketches but does not develop this hybrid.","A concrete testable extension: build a small spatiotemporal prototype (say 1,000 spins, one core per column) to measure whether the SFG accumulator and in-loop parametric amplifier maintain 50 dB SNR over hundreds of round trips; the architecture's feasibility hinges on exactly that measurement."],"forward_implications":["If the chiplet route works, a 5×5 array of chiplets, each handling more than 40,000 spins, would collectively implement a million-spin Ising machine while preserving all-to-all connectivity in the decomposed couplings.","A free-space processor built from commercially available multi-million-pixel spatial light modulators (or metasurfaces) could support thousands of spins per module today and a million via Fourier-domain multiplication, at the cost of restricting couplings to convolutional forms.","The all-optical spatiotemporal architecture, if realised, would need no optical-electrical-optical conversions, avoiding the DAC/ADC and memory-access latency that dominates time-multiplexed machines, at a 200 GHz clock.","At the paper's quoted energy budget, a million-spin machine's optical memory would consume about 40 fJ per MAC at 8-bit precision—orders of magnitude below the energy per operation of electronic solvers—and the whole computation could iterate in the microsecond range.","If these architectures reach the million-spin scale, problem classes requiring roughly 10^6 variables—1,000-city travelling-salesman instances and 200-amino-acid lattice protein models—become the native size class for photonic Ising hardware."],"fun_headline_variants":["Three photonic designs target million-spin Ising machines","Million-spin photonic Ising machines: three possible roadmaps","Photonic Ising machines: scaling to a million spins and beyond","Chiplets, free-space, and all-optical paths to million-spin Ising","Architectural fixes could scale photonic Ising to a million spins"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The million-spin claim for the flagship all-optical architecture rests on storing the full coupling matrix in a multicore fibre loop with about one million parallel cores, roughly four orders of magnitude beyond today's multicore fibres—and the accompanying 800 W circulating-power budget does not match the paper's own pulse-count and per-pulse energy figures.","fun_headline_variants_meta":{"raw":{"variants":["Three photonic designs target million-spin Ising machines","Million-spin photonic Ising machines: three possible roadmaps","Photonic Ising machines: scaling to a million spins and beyond","Chiplets, free-space, and all-optical paths to million-spin Ising","Architectural fixes could scale photonic Ising to a million spins"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000281,"raw_usage":{"total_tokens":1473,"prompt_tokens":686,"completion_tokens":787,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":430,"completion_tokens_details":{"reasoning_tokens":705}},"tokens_in":430,"tokens_out":787,"duration_ms":7138,"temperature":1.0,"reasoning_tokens":705,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-02T05:09:26.641113+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"A back-of-envelope power audit settles the flagship architecture: 10^12 pulses × 4 fJ per pulse per ~5 µs round trip yields roughly 800 kW, not 800 W; a prototype at 1,000 spins with the claimed 50 dB SNR and stable DOPA compensation over 1,000 round trips would further test the central claim.","supporting_citations":[],"review_version":1}