{"id":"d5303b3d-2b98-413b-bd87-49a6f313ffe3","arxiv_id":"2607.15782","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Vogls, an open-source Verilog simulator, combines compiled-code speed with full-timing simulation and interactive state forking for pre-silicon side-channel analysis, and recovers an AES key with DPA at three abstraction levels.","lead":"Vogls is a new open-source Verilog simulator built for pre-silicon side-channel analysis that compiles full-timing simulation into fast native code and lets users fork, inspect, and mutate simulation state from Python. A generalist should care because finding power leaks before a chip is fabricated requires collecting tens of thousands of simulation traces, and Vogls reports doing this many times faster than the standard open-source full-timing simulator.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Vogls' full-timing semantics are unvalidated: no differential test against a reference simulator, so the 'more accurate timing model' and full-timing MTD rest on an unverified delay scheduler.","rationale":"Agree with the reader. The central claim is a tool that provides faster full-timing simulation; the entire SCA value proposition depends on timing fidelity. I considered the novelty overclaim ('first simulator' despite no commercial comparison) and the missing artifact; both are real but secondary. The artifact absence is fixable and not an argument flaw; the novelty overclaim only weakens a phrase, not the technical contribution. Semantic fidelity, by contrast, is the load-bearing premise: if wrong, the paper's headline speedup is for a simulation that does not produce the physical leakage phenomenon it claims to model. I give credit for the honest §V limitations and the internally consistent MTD trend, but consilience with literature is not a correctness proof. The proposed differential test is cheap and decisive. Verdict stays CONDITIONAL: claims are plausible but not yet verified, and the missing differential test is the key blocker.","tokens_in":11876,"tokens_out":5408,"duration_ms":46094,"concrete_test":"Differential test Vogls vs Icarus on the exact UART+AES ICE40 netlist from §IV.A/B with identical testbench: run both simulators with the same SDF/specify delays, dump every signal transition to VCD, and compare event-by-event (signal, time, value). Add a hand-built corpus of small timing circuits that force pulse width < gate delay, back-to-back pulses, and min/typ/max SDF variants. If Vogls' VCD matches Icarus on all events for all circuits, the delay scheduler is validated for those semantics; any mismatch in glitch presence or transition time invalidates the full-timing MTD unless corrected.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Vogls' core advantage over Verilator and the motivation for full-timing SCA is that glitches matter: Mangard et al. show timing effects can bypass masking, and Table III's MTD grows from 6,897 (RTL) to 13,154 (GTL) to 18,341 (full-timing GTL). But the full-timing column is trustworthy only if Vogls' delay scheduler implements IEEE 1364 / SDF semantics faithfully. §V concedes the test suite 'mostly stem[s] from bugs found during development,' and no differential testing against Icarus Verilog or measurement on hardware is reported. The paper also does not describe how VIR's lupdt/varwait mechanism handles critical timing behaviors: inertial delay/pulse rejection, min:typ:max SDF selection, and timing checks. If, for example, Vogls always propagates a pulse whose width is shorter than the gate delay instead of rejecting it, glitch counts and the resulting Hamming-distance power traces would diverge from real silicon (and from Icarus), making the MTD values and the 'leakage characteristics preserved' forking claim artifacts of Vogls' model. The monotonic MTD trend is consistent with glitch literature but does not validate the scheduler: an incorrect simulator could still produce that trend. This is addressable, but until reference differential testing is done, the central 'full-timing' claim is not established.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents Vogls, a new open-source Verilog simulator aimed at pre-silicon power side-channel analysis. Vogls compiles Verilog designs to a custom intermediate representation (VIR) and then to either bytecode or native C code. Its main claimed contributions are (1) full-timing simulation performance superior to Icarus Verilog and comparable to Verilator on an RTL design, (2) a Python interface that supports forking, inspecting, and mutating simulation state without modifying the design, and (3) a case study showing a DPA attack recovering an AES key at RTL, GTL, and full-timing GTL abstraction levels. The performance numbers in Table II largely recompute as stated, and the case study in Table III demonstrates the workflow. However, the paper's central full-timing claim rests on an unvalidated delay scheduler, and the discussion in §V explicitly concedes that the test suite mostly stems from bugs found during development.","tokens_in":12030,"tokens_out":2477,"duration_ms":21863,"significance":"If the full-timing semantics are correct, Vogls would fill a genuine gap: no open-source simulator combines compiled-code speed, four-value/full-timing simulation, and interactive state forking. The forking workflow is a meaningful contribution for SCA trace collection, and the case study makes the utility concrete. The paper also provides reproducible benchmark-style measurements and a clear description of VIR. The main risk is that the full-timing model — the key differentiator over Verilator — is not validated against a reference simulator or hardware, so the full-timing MTD value and the 'more accurate timing model' claim are not yet established.","major_comments":[{"comment":"The load-bearing claim that Vogls provides a 'more accurate timing model' and valid full-timing leakage results is not supported by any differential validation. §V states that the test suite 'mostly stem[s] from bugs found during development,' and no comparison against Icarus Verilog, another IEEE-1364/SDF-compliant simulator, or hardware measurements is reported. The description of lupdt/varwait in §III.B does not establish correct handling of inertial delay/pulse rejection, min:typ:max SDF selection, or timing checks. Since the full-timing MTD of 18,341 traces in Table III and the claim that glitches are modeled depend entirely on this scheduler, the authors should add differential tests against a reference simulator (e.g., Icarus) on the same ICE40 netlist and, ideally, a hardware measurement. Without this, the full-timing column of Table III may be an artifact of Vogls' timing model.","section":"§V, §III.B"},{"comment":"The headline performance comparison is stated in a way that is misleading about end-to-end cost. The '5.9x faster than Icarus Verilog' figure compares only simulation time (76.164 s vs 12.798 s) and excludes Vogls' compilation time of 93.167 s versus Icarus' 0.417 s. For a single run, Vogls is not faster; the claim is only valid when compilation is amortized over many traces. The paper should state this amortization explicitly. Additionally, 'only 30% slower than Verilator' is an overstatement: 1.799 s vs 1.441 s is 24.8% slower. Please correct the percentage and discuss the amortization caveat.","section":"§IV.A, Table II"},{"comment":"The claim that forking 'preserv[es] timing and leakage characteristics' (Abstract and §III.C) is not empirically demonstrated. The argument that the design is read-only and the entire state is copied is plausible, but a concrete equivalence check — e.g., that a forked simulation produces bit-identical signal traces to a non-forked simulation — would be straightforward and should be reported. This is particularly important because the forked workflow is one of the three headline contributions and is used for all MTD measurements in Table III.","section":"§IV.B, forking workflow"}],"minor_comments":[{"comment":"MTD (Minimum Traces to Disclosure) is used without a formal definition. Define it precisely (e.g., the smallest trace count at which all 16 key bytes are ranked first) and state the attack parameters (number of key hypotheses, ranking criterion, etc.) for reproducibility.","section":"§IV.B, Table III"},{"comment":"The text says 'a specification is available for VIR' but no URL or reference is given. Please provide a stable link or citation.","section":"§III.B"},{"comment":"The paper says the source-code repository includes a full overview of supported Verilog concepts, but no repository URL appears anywhere in the manuscript. Since the paper promises open-sourcing 'upon acceptance,' include the URL now or state clearly that it will be added.","section":"§V"},{"comment":"The benchmark environment is described, but not the exact versions of Verilator and Icarus Verilog, nor the C compiler flags used for Vogls' native code path. State versions and flags for reproducibility.","section":"§IV.A"},{"comment":"The phrase 'first simulator to combine...' is a strong novelty claim. It would help to cite the specific features in Table I and explicitly contrast with CVC, which is listed as efficient and versatile but not interactive. The current text does not make clear whether CVC's interactive limitations are architectural or simply unverified.","section":"Abstract"}],"recommendation":"major_revision","confidential_remarks":"The paper is well-written and the tool is potentially useful, but the central full-timing fidelity claim needs validation before publication. The authors' own §V admission about the test suite is honest but severe. If they add differential testing against Icarus Verilog or an FPGA measurement, the paper would be a solid accept. The missing repository URL and artifact availability are also worth checking during revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Vogls is a solid systems paper. The core contribution - a Verilog simulator that compiles full-timing designs to native code and separates design from state so you can fork simulations - is real and worth knowing about. The 5.9x speedup over Icarus on a timing-annotated AES/UART design recomputes cleanly from Table II, and the forking workflow is a practical answer to the trace-collection bottleneck that Liu et al. describe. The VIR intermediate representation is a thoughtful piece of engineering; extending LLHD-style IRs with specify-block/SDF timing is the right move. The load-bearing claim is that Vogls implements full-timing semantics faithfully enough that gate-level glitches in simulation match what silicon would do. That premise is not established. Section V owns up to the test suite being mostly bugs found during development, and there is no differential testing against Icarus or against hardware. The stress-test note is right: inertial delay, pulse rejection, min:typ:max SDF, timing checks - none of these are discussed in enough detail to trust the delay scheduler. So the monotonic MTD trend in Table III is consistent with the glitch literature but does not validate the scheduler. An incorrect simulator could produce that same trend. Also, no repository or commit hash is provided; will be open-sourced upon acceptance caps confidence, especially for an artifact paper. The first simulator claim is on the edge - the open-source survey is fine, but the paper does not engage with commercial save/restore capabilities, and a hedged claim would be safer. Fork equivalence is argued structurally, not measured; an A/B fork test would close that. One small arithmetic nit: 30% slower than Verilator is actually about 25% (1.799 vs 1.441 s). Minor. Who this is for: anyone doing pre-silicon SCA who needs to collect large trace sets on gate-level designs. The paper deserves a serious referee - the artifact, once available, will be widely used if the semantics hold. I would send it to review, with a request for differential testing and artifact release.","headline":"Vogls is a practical tool paper with a real contribution, but the full-timing fidelity claim needs differential testing and the artifact must be released.","tokens_in":658,"tokens_out":941,"would_cite":true,"duration_ms":19845,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Vogls is a Verilog simulator that combines compiled-code speed, full-timing semantics, and forkable simulation state for pre-silicon side-channel analysis.","keywords":["pre-silicon side-channel analysis","full-timing simulation","Verilog simulator","state forking","differential power analysis","gate-level timing","Vogls Intermediate Representation","trace collection"],"falsifier":"Take a timing-annotated gate-level netlist, simulate the same input vector in Vogls and in a mature full-timing reference simulator (or measure a fabricated FPGA/ASIC implementation), and compare per-transition signal activity and glitch behavior at each timestamp. A divergence in glitch count or transition timing in Vogls relative to the reference would invalidate the claim that Vogls preserves full-timing leakage characteristics and would make the reported minimum-trace-to-disclosure numbers an artifact of Vogls' model rather than a property of the design.","tokens_in":11567,"feed_emoji":"⚡","tokens_out":4462,"duration_ms":34177,"temperature":0.7,"pith_summary":"The paper argues that pre-silicon power side-channel analysis needs a simulator that is fast enough to collect thousands of traces, accurate enough to model gate-level timing including glitches and delays, and controllable enough to fork, mutate, and resume around a point of interest. It presents Vogls, which compiles Verilog designs to C, supports full-timing semantics via specify blocks and SDF annotations, and separates design from state so that a simulation can be copied inexpensively. In benchmarks, Vogls simulates a timing-annotated gate-level AES design 5.9 times faster than the open-source reference simulator Icarus Verilog and runs a PicoRV32 RTL design only 30% slower than Verilator. A case study demonstrates a differential power analysis attack recovering an AES key at RTL, gate-level, and full-timing gate-level abstractions. The pith is that combining these three properties removes a practical barrier: timing-accurate side-channel evaluation no longer forces analysts to restart from reset for every trace.","feed_headline":"Full-timing Verilog simulation gets 5.9x speedup for side-channel traces","feed_subtitle":"A compiled, forkable open-source simulator makes timing-accurate pre-silicon trace collection practical.","key_machinery":"The load-bearing mechanism is the Vogls Intermediate Representation (VIR), a temporally-aware SSA/control-flow-graph representation that keeps Verilog's scheduling semantics explicit. VIR lowers to either a bytecode interpreter or generated C code, which the host compiler turns into native code. Around VIR, the design is separated from the mutable simulation state (time, signal values, listeners, update times); forking copies only the state. Timing annotations such as specify blocks and SDF delays are compiled into VIR processes using 'last update time' instructions and timed waits, which is how full-timing glitch behavior is preserved. This combination lets Vogls re-run only a short window","core_discovery":"The central claim is that a simulator purpose-built for side-channel analysis can simultaneously deliver compiled-code performance, full-timing (sub-cycle) simulation, and fine-grained control over simulation state, and that this combination changes what is practical in pre-silicon SCA. Vogls achieves this by compiling the design to C while retaining a temporally-aware intermediate representation (VIR) that models Verilog scheduling, specify blocks, and SDF timing annotations. State is separated from design, so a simulation can be forked after expensive setup logic and reused across many traces with mutated inputs, preserving the design's timing and leakage characteristics. The paper reports","pith_inferences":["If Vogls' full-timing semantics prove faithful to real hardware, pre-silicon leakage assessment could routinely catch glitch-based leakages that cycle-accurate simulation misses, shifting countermeasure evaluation toward full-timing by default.","The state-forking model implies a natural parallelization strategy: independent state copies need no synchronization, so trace generation can scale across cores or distributed systems without the usual overhead.","The 30% performance gap to Verilator is measured on RTL; with the VIR optimizations the paper proposes, compiled Vogls may close much of that gap while retaining full-timing fidelity, making it viable for functional verification as well.","A key unresolved question is whether Vogls' timing-accurate glitch behavior on a specific cell library correlates with physical measurements; if it does, Vogls could become a low-cost substitute for FPGA-based leakage assessment in early design iterations."],"forward_implications":["Full-timing gate-level SCA trace collection becomes practical on designs previously too slow to simulate; the paper captures 30,000 full-timing traces in about 100 seconds using 8 worker threads.","The same DPA workflow runs across RTL, GTL, and full-timing GTL abstraction levels without redesign, enabling direct cross-abstraction leakage comparisons on one design.","Adaptive and online side-channel attacks, which need to inspect and mutate simulation state mid-run, are directly supported through the Python interface.","VIR provides a unified intermediate representation that could be reused by other tools needing temporal semantics, such as formal timing-property verification or independent pre-silicon SCA analyzers.","Because the design is never modified, forking preserves the timing and leakage characteristics of the original circuit for each reused trace."],"fun_headline_variants":["Forkable full-timing Verilog simulator: 5.9x faster side-channel traces","Vogls: compiled Verilog sim with timing accuracy, 5.9x speedup","Pre-silicon side-channel analysis gets a 5.9x speed boost","Timing-accurate Verilog simulation, now 5.9x faster for SCA"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The load-bearing premise is that Vogls correctly implements IEEE Verilog full-timing delay scheduling (specify blocks and SDF); the paper reports no differential testing against a reference simulator or against hardware to verify this.","fun_headline_variants_meta":{"raw":{"variants":["Forkable full-timing Verilog simulator: 5.9x faster side-channel traces","Vogls: compiled Verilog sim with timing accuracy, 5.9x speedup","Pre-silicon side-channel analysis gets a 5.9x speed boost","Timing-accurate Verilog simulation, now 5.9x faster for SCA"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000243,"raw_usage":{"total_tokens":1371,"prompt_tokens":756,"completion_tokens":615,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":500,"completion_tokens_details":{"reasoning_tokens":519}},"tokens_in":500,"tokens_out":615,"duration_ms":5233,"temperature":1.0,"reasoning_tokens":519,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-01T22:20:57.943428+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a timing-annotated gate-level netlist, simulate the same input vector in Vogls and in a mature full-timing reference simulator (or measure a fabricated FPGA/ASIC implementation), and compare per-transition signal activity and glitch behavior at each timestamp. A divergence in glitch count or transition timing in Vogls relative to the reference would invalidate the claim that Vogls preserves full-timing leakage characteristics and would make the reported minimum-trace-to-disclosure numbers an artifact of Vogls' model rather than a property of the design.","supporting_citations":[],"review_version":1}